TI SN74LVC32245ZKER

SN74LVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES343D – OCTOBER 2000 – REVISED JULY 2003
D
D
D
D
D
D
Member of the Texas Instruments
Widebus+ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D
D
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
description/ordering information
This 32-bit noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC32245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at
the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the
buses are effectively isolated.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
LFBGA – GKE
–40°C
40°C to 85°C
LFBGA – ZKE (Pb-free)
TOP-SIDE
MARKING
SN74LVC32245GKER
Tape and reel
SN74LVC32245ZKER
NC245
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74LVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES343D – OCTOBER 2000 – REVISED JULY 2003
GKE OR ZKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1B2
1B1
1DIR
1OE
1A1
1A2
B
B
1B4
1B3
GND
GND
1A3
1A4
C
C
1B6
1B5
1A6
D
1B8
1B7
VCC
GND
1A5
D
VCC
GND
1A7
1A8
E
2B2
2B1
GND
GND
2A1
2A2
F
2B4
2B3
2A4
2B6
2B5
VCC
GND
2A3
G
VCC
GND
2A5
2A6
H
2B7
2B8
2DIR
2OE
2A8
2A7
E
F
G
H
J
K
J
3B2
3B1
3DIR
3OE
3A1
3A2
K
3B4
3B3
GND
GND
3A3
3A4
L
3B6
3B5
VCC
GND
3A5
3A6
M
3B8
3B7
VCC
GND
3A7
3A8
M
N
4B2
4B1
GND
GND
4A1
4A2
N
P
4B4
4B3
4A4
R
4B6
4B5
VCC
GND
4A3
P
VCC
GND
4A5
4A6
R
T
4B7
4B8
4DIR
4OE
4A8
4A7
L
T
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
2
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74LVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES343D – OCTOBER 2000 – REVISED JULY 2003
logic diagram (positive logic)
1DIR
A3
2DIR
A4
1A1
H4
1OE
A5
2A1
A2
H3
E5
E2
1B1
To Seven Other Channels
3DIR
2B1
To Seven Other Channels
J3
4DIR
J4
3A1
2OE
T4
3OE
J5
4A1
J2
T3
4OE
N5
N2
3B1
To Seven Other Channels
4B1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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• DALLAS, TEXAS 75265
3
SN74LVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES343D – OCTOBER 2000 – REVISED JULY 2003
recommended operating conditions (see Note 4)
VCC
VIH
Operating
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
MAX
3.6
1.5
UNIT
V
0.65 × VCC
V
1.7
2
0.35 × VCC
0.7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High level output current
High-level
IOL
MIN
1.65
V
0.8
0
5.5
V
High or low state
0
3-state
0
VCC
5.5
V
VCC = 1.65 V
VCC = 2.3 V
–4
VCC = 2.7 V
VCC = 3 V
–12
–8
mA
–24
VCC = 1.65 V
VCC = 2.3 V
4
VCC = 2.7 V
VCC = 3 V
12
8
mA
24
5
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74LVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES343D – OCTOBER 2000 – REVISED JULY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
1.65 V
VCC–0.2
1.2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2.2
IOH = –8 mA
VOH
12 mA
IOH = –12
IOH = –24 mA
IOL = 100 µA
VOL
II
Ioff
Control inputs
IOZ‡
∆ICC
Ci
Control inputs
Cio
A or B ports
TYP†
MAX
UNIT
V
1.65 V to 3.6 V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
VI = 0 to 5.5 V
VI or VO = 5.5 V
3.6 V
±5
µA
0
±10
µA
±5
µA
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V§
ICC
MIN
2.3 V to 3.6 V
IO = 0
One input at VCC – 0.6 V,
20
36V
3.6
Other inputs at VCC or GND
20
2.7 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
500
V
µA
µA
3.3 V
5
pF
3.3 V
7.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This applies in the disabled state only.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
ten
OE
tdis
OE
PARAMETER
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
B or A
1.5
7.1
1
A or B
1.5
8.9
1
A or B
1.5
11.9
1
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MIN
MAX
MAX
4.5
1
4.7
1
4
ns
5.6
1.5
6.7
1.5
5.5
ns
6.8
1.5
7.1
1.5
6.6
ns
1
ns
tsk(o)
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
d
Power dissipation capacitance
per transceiver
Outputs enabled
Outputs disabled
VCC = 1.8 V
TYP
f = 10 MHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
34
37
38
3
3
4
UNIT
pF
5
SN74LVC32245
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES343D – OCTOBER 2000 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPLZ
tPZL
VLOAD/2
VM
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VOH
Output
VI
Output
Control
VM
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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• DALLAS, TEXAS 75265
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