PF777-03
Series
SED1530SED1530
Series
Dot Matrix LCD
Controller Driver
SSC5000Series
● Ultra Low Power Consumption
● Built-in Power Supply Circuit for LCD
● 133 Driver Output
■ DESCRIPTION
The SED1530 series is a single-chip LCD driver for dot-matrix liquid crystal displays (LCD’s) which is directly
connectable to a microcomputer bus. It accepts 8-bit serial or parallel display data directly sent from a
microcomputer and stores it in an on-chip display RAM. It generates an LCD drive signal independent of
microprocessor clock.
The use of the on-chip display RAM of 65 × 132 bits and a one-to-one correspondence between LCD panel pixel
dots and on-chip RAM bits permits implementation of displays with a high degree of freedom.
As a total of 133 circuits of common and segment outputs are incorporated, a single chip of SED1530 series can
make 33 × 100-dot (16 × 16-dot kanji font: 6 columns × 2 lines) displays, and a single chip of SED1531 can make
65 × 132-dot (kanji font: 8 columns x 4 lines) displays when the SED1531 is combined with the common driver
SED1635.
The SED1532 can display the 65x200-dot (or 12-column by 4-line Kanji font) area using two ICs in master and
slave modes. As an independent static indicator display is provided for time-division driving, the low-power display
is realized during system standby and others.
No external operation clock is required for RAM read/write operations. Accordingly, this driver can be operated
with a minimum current consumption and its on-board low-current-consumption liquid crystal power supply can
implement a high-performance handy display system with a minimum current consumption and a smallest LSI
configuration.
Two types of SED1530 series are available: one in which common outputs are arranged on a single side and the
other in which common outputs are arranged on both sides.
■ FEATURES
● Direct RAM data display using the display RAM. When RAM data bit is 0, it is not displayed. When RAM data
bit is 1, it is displayed. (At normal display)
● RAM capacity: 65 × 132 = 8580 bits
● High-speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800.
● Serial interface
● Many command functions: Read/Write Display Data, Display ON/OFF, Normal/Reverse Display, Page
Address Set, Set Display Start Line, Set Column Address, Read Status, All Display ON/OFF, Set LCD Bias,
Electronic contrast Controls, Read Modify Write, Select Segment Driver Direction, Power Save
1
SED1530 Series
■ LINE UP
Type 1 [VREG Temperature gradient 0.2% / °C]
• Specifications (for chip models)
Name
Duty
LCD bias
Segment driver
COM driver
Display area
Remarks
SED1530D0*
1/33
1/5, 1/6
100
33
33 × 100
COM single-side assignment
SED1530DA*
1/33
1/5, 1/6
100
33
33 × 100
COM dual-side assignment
SED1531D0*
1/65
1/6, 1/8
132
0
65 × 132
SED1635 is used for COM.
SED1532D0*
1/65
1/6, 1/8
100
33
65 × 200
COM single-side right assignment
SED1532DB*
1/65
1/6, 1/8
100
33
65 × 200
COM single-side left assignment
Type 2 [VREG Temperature gradient 0.00% / °C]
Name
Duty
LCD bias
Segment driver
COM driver
Display area
Remarks
SED1530DF*
1/33
1/5, 1/6
100
33
33 × 100
COM both-side layout
SED1532DE*
1/65
1/6, 1/8
100
33
65 × 200
COM single-side, right-hand layout
SED1533DF*
1/17
1/5
116
17
17 × 116
COM both-side layout
SED1534DE*
1/9
1/5
124
9
9 × 124
COM single-side layout
Note: The SED1530 series has the following subcodes depending on their shapes. (The SED1530 examples are
given.)
SED1530T
: TCP (The TCP subcode differs from the inherent chip subcode.)
SED1530D
: Bear chips
SED1530D A : Aluminum pad
SED1530D B : Gold bump
**
**
*
*
● On-chip LCD power circuit: Liquid crystal driving power supply booster circuit, voltage regulator circuit, voltage
follower × 4.
● On-chip electronic contrast control functions
● Ultra low power consumption
● Power supply voltages: VDD - VSS -2.4 V to -6.0 V
VDD - V5 -4.5 V to -16.0 V (In the case of external power supply)
● Wide operating temperature range:
Ta = -40 to 85°C
● CMOS process
● Package: TCP and bare chip
● Non-radiation-resistant design
2
SED1530 Series
■ BLOCK DIAGRAM (SED1530D0B)
O0
O99 O100
O15 COMS
···············································
·····················
VSS
COM S
Segment driver
V4
Common driver
Shift register
CAP1+
CAP1–
CAP2+
Display data latch
Power supply
circuit
CAP2–
VOUT
VR
Output
status
selector
circuit
132 x 65-dot
display data RAM
Initial display line register
CAP3–
Line counter
V5
V2
Line address decoder
V3
VDD
I/O buffer circuit
V1
Column address decoder
Page address
register
8-bit column address counter
Display timing
generator circuit
8-bit column address register
Bus holder
Command decoder
Status
register
Microprocessor interface
CS1 CS2
A0
RD WR C86 P/S RES
(E) (R/W)
Oscillator
FRS
FR
CL
DYO
DOF
M//S
VS1
I/O buffer
D7 D6
D5
(SI) (SCL)
D4
D3
D2
D1
D0
3
SED1530 Series
■ PIN LAYOUT
51
1
52
172
86
138
87
137
Chip Size:
Pad Pitch:
4
6.65x4.57 mm
118 µm (Min.)
SED153*D*A
Pad Center Size:
Chip Thickness:
(Aluminum pad model)
90x90 µm
300 µm
SED153*D*B
Bump Size:
Bump Height:
Chip Thickness:
(Gold bump model)
76x76 µm
23 µm (Typ.)
625 µm
SED1530 Series
■ PAD CENTER COORDINATES
Unit: um
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIN
Name
X
0127
2986
0128
2862
0129
2738
0130
2614
0131
2490
COMS 2366
FRS
2242
FR
2124
DYO
2006
CL
1888
DOF
1770
VS1
1652
M/S
1534
RES
1416
P/S
1298
CS1
1180
CS2
1062
C86
944
A0
826
WR(W/R) 708
RD(E)
590
VDD
354
D0
236
D1
236
D2
118
D3
0
D4
-118
D5
-236
D6(SCL) -354
D7(SI) -472
VSS
-590
VOUT
-708
CAP3- -826
CAP1+ -944
CAP1- -1062
CAP2+ -1180
CAP2- -1298
V5
-1416
VR
-1534
VDD
-1652
V1
-1770
V2
-1888
V3
-2006
V4
-2124
V5
-2242
O0
-2366
O1
-2490
O2
-2614
O3
-2738
O4
-2862
Y
2142
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN
Name
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
O21
O22
O23
O24
O25
O26
O27
O28
O29
O30
O31
O32
O33
O34
O35
O36
O37
O38
O39
O40
O41
O42
O43
O44
O45
O46
O47
O48
O49
O50
O51
O52
O53
O54
X
-2986
-3178
Y
2142
2006
1888
1770
1652
1534
1416
1298
1180
1062
944
826
708
590
472
354
236
118
0
-118
-236
-354
-472
-590
-708
-826
-944
-1062
-1180
-1298
-1416
-1534
-1652
-1770
-1888
-2006
-2986 -2142
-2862
-2738
-2614
-2490
-2366
-2242
-2124
-2006
-1888
-1770
-1652
-1534
-1416
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
PIN
Name
X
Y
O55
-1298 -2142
O56
-1180
O57
-1062
O58
-944
O59
-826
O60
-708
O61
-590
O62
-472
O63
-354
O64
-236
O65
-118
O66
0
O67
118
O68
236
O69
354
O70
472
O71
590
O72
708
O73
826
O74
944
O75
1062
O76
1180
O77
1298
O78
1416
O79
1534
O80
1652
O81
1770
O82
1888
O83
2006
O84
2124
O85
2242
O86
2366
O87
2490
O88
2614
O89
2738
O90
2862
O91
2986
O92
3178 -2006
O93
-1888
O94
-1770
O95
-1652
O96
-1534
O97
-1416
O98
-1298
O99
-1180
O100
-1062
O101
-944
O102
-826
O103
-708
O104
-590
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
PIN
Name
O105
O106
O107
O108
O109
O110
O111
O112
O113
O114
O115
O116
O117
O118
O119
O120
O121
O122
O123
O124
O125
O126
X
3178
Y
-472
-354
-236
-118
0
118
236
354
472
590
708
826
944
1062
1180
1298
1416
1534
1652
1770
1888
2006
5
SED1530 Series
■ ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
–0.3 to +7.0
Supply voltage range
Triple boosting
VDD
Quadruple boosting
–0.3 to +6.0
V
–0.3 to +4.5
Supply voltage range (1) (VDD Level)
V5, VOUT
–18.0 to +0.3
V
Supply voltage range (2) (VDD Level)
V1, V2, V3, V4
V5 to +0.3
V
Input voltage range
VIN
–0.3 to VDD+0.3
V
Output voltage range
V0
–0.3 to VDD+0.3
V
TOPR
–40 to +85
°C
–55 to +100
°C
Operating temperature range
Storage temperature range
TCP
TSTR
Bear chip
–55 to +125
VCC
VDD
GND
VSS
VDD
V1 to V4
V5, VOUT
(System)
(SED1530 series)
Notes: 1. V1 to V5 and VOUT voltages are based on VDD=0 V.
2. Voltages VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be satisfied.
3. If an LSI exceeds its absolute maximum rating, it may be damaged permanently. It is desirable to use it
under electrical characteristics conditions during general operation. Otherwise, an LSI malfunction or
reduced LSI reliability may result.
6
SED1530 Series
■ ELECTRICAL CHARACTERISTICS
● DC Characteristics
(VSS = 0 V, VDD = 5 V ±10%, Ta = –40 to +85°C unless otherwise noted.)
Item
Symbol
Power voltage(1) Recommended
Operation
Operational
VDD
Operating voltage Operational
V5
(2) Operational
Operational
High-level input voltage
Condition
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
2.4
–
6.0
VDD level (VDD = 0 V)
–16.0
–
–4.5
V
V5
V1, V2
VDD level (VDD = 0 V)
0.4 × V5
–
VDD
V
V1, V2
V3, V4
VDD level (VDD = 0 V)
V5
–
0.6 × V5
V
V3, V4
0.7 × VDD
–
VDD
V
0.8 × VDD
–
VDD
VSS
–
0.3 × VDD
VDD = 2.7 V
VSS
–
0.2 × VDD
IOH = –1 mA
0.8 × VDD
–
VDD
VDD = 2.7 V, IOH = –0.5 mA
0.8 × VDD
–
VDD
IOL = 1 mA
VSS
–
0.2 × VDD
VDD = 2.7 V, IOL = 0.5 mA
VSS
–
0.2 × VDD
*5
0.85 × VDD
–
VDD
*4
0.8 × VDD
–
VDD
*4
VSS
–
0.15 × VDD
*4
VDD = 2.7 V
VSS
–
0.2 × VDD
*4
VIN = VDD or VSS
–1.0
–
1.0
µA
*6
–3.0
–
3.0
µA
*7
KΩ
VIHC
VDD = 2.7 V
CMOS
Low-level input voltage
High-level output voltage
Low-level output voltage
Schmitt
High-level input voltage
VILC
VOHC
VOLC
VIHS
VDD = 2.7 V
Low-level input voltage
VILS
Input leakage current
ILI
Output leakage current
ILO
LCD driver ON resistance
RON
Pin used
VSS *1
*2
*3
*3
V
*3
*3
V
*5
*5
V
*5
SEG n
COM n
Ta = 25°C
V5 = –14.0 V
–
2.0
3.0
VDD level
V5 = –8.0 V
–
3.0
4.5
VIN = VDD or VSS
–
0.01
5.0
µA
VSS
I5Q
V5 = –18.0 V (VDD level)
–
0.01
15.0
µA
V5
Input pin capacity
CIN
Ta = 25°C, f = 1 MHz
–
5.0
8.0
pF
*3 *4
Oscillation frequency
fOSC
Ta = 25°C
VDD = 5 V
18
22
26
kHz
*9
VDD = 2.7 V
18
22
26
Triple boosting
2.4
–
6.0
V
*10
Quadruple boosting
2.4
–
4.5
Static current consumption
Built-in power circuit
Input voltage
ISSQ
VDD
*8
Booster output voltage
VOUT
Triple voltage conversion (VDD level)
–18.0
–
–
V
VOUT
Voltage regulator operation
VOUT
(VDD level)
–18.0
–
–6.0
V
VOUT
V5
(VDD level)
–18.0
–
–6.0
V
–16.0
–
–4.5
–2.75
–2.55
–2.35
voltage
Voltage follower operation
voltage
Reference voltage
VREG
Ta = 25°C (VDD level)
*11
V
7
SED1530 Series
● Dynamic current consumption (1) when the built-in power supply is OFF
Item
Symbol
SED1530
IDD
(1)
Min.
Typ.
Max.
Unit
VDD = 5.0 V, V5 – VDD = –8.0 V
—
24
40
µA
VDD = 3.0 V, V5 – VDD = –8.0 V
—
22
35
VDD = 5.0 V, V5 – VDD = –11.0 V
—
40
65
VDD = 3.0 V, V5 – VDD = –11.0 V
—
36
60
VDD = 5.0 V, V5 – VDD = –11.0 V
—
39
65
VDD = 3.0 V, V5 – VDD = –11.0 V
—
32
55
SED1533
VDD = 3.0 V, V5 – VDD = –5.0 V
—
20
35
SED1534
VDD = 3.0 V, V5 – VDD = –5.0 V
—
20
35
Min.
Typ.
Max.
Unit
µA
SED1531
SED1532
Condition
Ta = 25°C
● Dynamic current consumption (2) when the built-in power supply is ON
Symbol
SED1530
IDD
VDD = 5.0 V, V5 – VDD = –8.0 V, dual boosting
—
41
70
(1)
VDD = 3.0 V, V5 – VDD = –8.0 V, triple boosting
—
48
80
VDD = 5.0 V, V5 – VDD = –11.0 V, triple boosting
—
96
160
VDD = 3.0 V, V5 – VDD = –11.0 V, quadruple boosting
—
118
190
VDD = 5.0 V, V5 – VDD = –11.0 V, triple boosting
—
95
160
VDD = 3.0 V, V5 – VDD = –11.0 V, quadruple boosting
—
114
190
SED1533
VDD = 3.0 V, V5 – VDD = –5.0 V, dual boosting
—
30
50
SED1534
VDD = 3.0 V, V5 – VDD = –5.0 V, dual boosting
—
32
55
SED1532
● Current consumption during Power Save mode
Item
Symbol
Min.
Typ.
Max.
Unit
µA
During sleep IDDS1
SED1530, SED1531, SED1532
—
0.01
1
During standby IDDS2
SED1530, SED1531, SED1532
—
10
20
● Typical current consumption characteristics
(reference data)
• Dynamic current consumption (1) when LCD
external power mode lamp is ON
20
Conditions: The built-in power supply is
OFF and an external power
supply is used.
SED1530 V5-VDD = –8.0V
SED1531 V5-VDD = –11.0V
SED1532 V5-VDD = –11.0V
SED1533 V5-VDD = –6.0V
SED1534 V5-VDD = –6.0V
Ta = 25°C
(µA)
15
SED1531, SED1532
SED1530
Remarks:
5
SED1533, SED1534
0
1
2
3
4
VDD
8
5
Note
*13
VSS=0V, VDD=2.7 to 5.5V Ta = 25°C
Condition
IDD(1)
(ISS+15)
10
*12
Ta = 25°C
Item
SED1531
Condition
Note
6
7 (V)
*12
Note
SED1530 Series
• Dynamic current consumption (2) when the LCD
built-in power circuit lamp is ON
200
Conditions: The built-in power supply is ON.
SED1530 V5-VDD = –8.0V,
triple boosting
SED1531 V5-VDD = –11.0V,
quadruple boosting
SED1532 V5-VDD = –11.0V,
quadruple boosting
SED1533 V5-VDD = –5.0V,
dual boosting
SED1534 V5-VDD = –5.0V,
dual boosting
Ta = 25°C
(µA)
150
SED1531, SED1532
IDD(1)
(ISS+15)
100
SED1530
50
Remarks:
SED1533, SED1534
0
1
2
3
4
5
6
*13
7 (V)
VDD
*1
Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the microprocessor.
*2 VDD and V5 operating voltage range. (Refer to Fig.)
The operating voltage range applies if an external power supply is used.
*3 A0, D0 - D5, D6, D7 (SI), RD (E), WR (R/W), CS1, CS2, FR, M/S, C86, P/S and DOF pins
*4 CL, SCL (D6) and RES pins
*5 D0 - D5, D6, D7 (SI), FR, FRS, DYO, DOF and CL pins
*6 A0, RD (E), WR (R/W), CS1, CS2, M/S, RES, C86 and P/S pins
*7 Applies when the D0 - D7, FR, CL, DYO and DOF pins are in high impedance,
*8 Resistance value when 0.1 V is applied between the output pin SEGn or COMn and each power supply pin (V1,
V2, V3, V4).
This is specified in the operating voltage (2) range.
R ON = 0.1 V/∆I (∆I: Current flowing when 0.1 V is applied in the ON status.)
*9 For the relationship between oscillation frequency and frame frequency. (Refer to Fig.)
*10 For triple or quadruple boosting using the on-chip power using the primary-side power supply VDD must be used
within the input voltage range.
*11 The voltage regulator adjusts V5 within the voltage follower operating voltage range.
*12, *13 Current that each IC unit consumes. It does not include the current of the LCD panel capacity, wiring capacity,
etc.
This is current consumption under the conditions of display data = checker, display ON, SED1530 = 1/33 duty,
and SED1531 and SED1532 = 1/65 duty.
*12 Applies to the case where the on-chip oscillator circuit is used and no access is made from the microprocessor.
*13 Applies to the case where the on-chip oscillator circuit and the on-chip power circuit are used and no access is
made from the microprocessor.
The current flowing through voltage regulation resistors (R1, R2 and R3) is not included.
The current consumption, when the on-chip voltage booster is used, is for the power supply VDD.
• Relationship between oscillation frequency and frame frequency
The relationship between oscillation frequency fOSC and LCD frame frequency fF can be obtained by the
following expression.
SED1530
SED1531
SED1532
SED1533
SED1534
Duty
1/33
f CL
f OSC/8
fF
f OSC/(8*33)
1/65
f OSC/4
f OSC/(4*65)
1/17
1/9
f OSC/8
f OSC/8
f OSC/(8*17)
f OSC/(8*9)
(fF does not indicate the FR signal cycle but the AC cycle.)
Relationship between clock (fCL) and frame frequency fF
9
SED1530 Series
• VSS and V5 operating voltage range
-20
[V]
V5-VDD
-16
-15
-11
Operating
range
-10
-5
2.4
0
3.5
2
4
VDD
6
8
[V]
• Current consumption at access IDD (2) - Microprocessor access cycle
10
[mA]
1
IDD (2)
0.1
SED1531,
SED1532
SED1530
SED1533
SED1534
0.01
0
10
0.01
0.1
1
fcyc [MHz]
This indicates current consumption when
data is always written on the checker pattern
at fcyc. When no access is made, only IDD
(1) occurs.
Condition: SED1530 V5-VDD=–8.0V,
triple boosting
SED1531 V5-VDD=–11.0V,
quadruple boosting
SED1532 V5-VDD=–11.0V,
quadruple boosting
10
SED1533 V5-VDD=–6.0V,
dual boosting
SED1534 V5-VDD=–6.0V,
dual boosting
Ta = 25°C
SED1530 Series
■ CONNECTION BETWEEN LCD Drivers
The LCD panel display area can easily be expanded by use of multiple SED1530 series chips. The SED1530 series
can also be connected to the common driver (SED1670).
● SED1531 to SED1670
VDD
SED1670D1A
DOFF
DIO
FR
SED1531
(master)
FR
YSCL
CL
DYO
M/S
DOF
● SED1530 to SED1531
VDD
SED1530
(master)
M/S
CL
DYO
FR
SED1530
(slave)
FR
CL
DOF
DYO
M/S
VSS
DOF
● SED1532 to SED1532
VDD
SED1532
(master)
M/S
CL
DYO
FR
DOF
SED1532
(slave)
FR
CL
DYO
M/S
DOF
VSS
11
}
|
{
SED1530 Series
■ LCD PANEL CONNECTION EXAMPLES
SED1530 : 100 × 33dot
SEG (100)
SEG (100)
SED1530D0A
<Master>
SED1530DAA
<Master>
COM (33)
COM (17)
COM (16)
COM(65)
SED1670
132 × 65 dot
DOFF DIO YSCL FR
SEG(132)
FR
CL
DYO
DOF
VDD
M/S
SED1531
@SED1532 : 200 × 65 dot
SEG(100)
SEG(100)
SED1532
<Master>
COM(33)
VDD
12
M/S
FR
DOF
CL
FR
DOF
CL
SED1532
<Slave>
COM(32)
M/S
SED1530 Series
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson
reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Morever, no license to any intellectual property rights is granted
by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any
patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of
International Trade and Industry or other approval from another government agency.
IBM is registered trademark of International Business Machines Corporation, U.S.A.
© Seiko Epson Corporation 1996 All right reserved.
ELECTRONIC DEVICE MARKETING DEPARTMENT
IC Marketing & Engineering Group
421-8 Hino, Hino-shi, Tokyo 191, JAPAN
Phone: 0425-87-5816
FAX: 0425-87-5624
International Marketing Department I (Europe, U.S.A.)
421-8 Hino, Hino-shi, Tokyo 191, JAPAN
Phone: 0425-87-5812
FAX: 0425-87-5564
International Marketing Department II (Asia)
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Phone: 0425-87-5814
FAX: 0425-87-5110
14
First issue Dec., 1996
Printed Nov. 1996 in Japan
H