TI TLC5910PZP

TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
D
D
D
D
D
D
D
D
Drive Capability and Output Counts
– 80 mA (Current Sink) x 16 Bits
Constant Current Output Range
– 5 to 80 mA (Current Value Setting for All
Output Terminals Using External Resistor
and Internal Brightness Control Register)
Constant Current Accuracy
– ± 4% (Maximum Error Between Bits)
Voltage Applied to Constant Current Output
Terminals
– Minimum 0.4 V (Output Current 5 to
40 mA)
– Minimum 0.7 V (Output Current 40 to
80 mA)
1024 Gray Scale Display
– Pulse Width Control 1024 Steps
Brightness Adjustment†
– All Output Current Adjustment for 64
Steps (Adjustment for Brightness
Deviation Between LED Modules)
– Output Current Adjustment by Output
(OUT0 to OUT15) for 64 Steps
(Adjustment for Brightness Deviation
Between Dots)
– Brightness Control by 16 Steps
Frequency Division Gray Scale Control
Clock (Brightness Adjustment for Panel)
Gray Scale Clock Generation
– Gray Scale Control Clock Generation by
Internal PLL or External Input Selectable
Clock Invert/Noninvert Selectable
– Clock Invert Selectable to Reduce
Changes in Duty Ratio at Cascade
Operation
D
D
D
D
D
D
D
D
D
D
Protection
– WDT (Watchdog Timer) Function (Turn
Output Off When Scan Signal Stopped)
– TSD (Thermal Shutdown) Function (Turn
Output Off When Junction Temperature
Exceeds Limit)
LOD
– LED Open Detection (Detection for LED
Disconnection)
Data Input/Output‡
– Port A (for Data Display)
– Clock Synchronized 10 Bit Parallel
Input (Schmitt Triggered Input)
– Clock Synchronized 10 Bit Parallel
Output (3-State Output)
– Port B (for Dot Correction Data)
– Clock Synchronized 6 Bit Parallel
Input (Schmitt-Triggered Input)
– Clock Synchronized 6 Bit Parallel
Output
Input/Output Signal Level
– CMOS Level
Power Supply Voltage
– 4.5 V to 5.5 V (Logic, Analog and
Constant Current)
– 3 V to 5.5 V (Interface)
Maximum Output Voltage . . . 15 V (Max)
Data Transfer Rate . . . 20 MHz (Max)
Gray Scale Clock Frequency
– 16 MHz (Max) Using Internal PLL
– 8 MHz (Max) Using External Clock
Operating Free-Air Temperature Range
–20°C to 85°C
100-Pin HTQFP Package (PD=4.7 W,
TA = 25°C)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† These functions are adjustable independently.
‡ Allows the writting of all the data at port A by setting the logic to 1.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
description
The TLC5910 is a constant current driver, incorporating a shift register, data latch, and constant current circuitry
with current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display
using pulse width control. The output current is a maximum of 80 mA with 16 bits, and the current value of
constant current output can be set by one external resistor. The device has two channel I/O ports. The
brightness deviation between LED modules (ICs) can be adjusted by external data input from a display data
port. The brightness control for the panel can be accomplished by the brightness adjustment circuitry.
Independently of these functions, the device incorporates the shift register and data latch to correct the deviation
between LEDs adjusting output current using data from a dot correction data port. Moreover, the device
incorporates watchdog timer (WDT) circuitry, which turns the constant current output off when a scan signal is
stopped at the dynamic scanning operation. It incorporates thermal shutdown (TSD) circuitry, which turns
constant current output off when the junction temperature exceeds the limit. It also incorporates LOD (LED open
detection) circuitry, which creates an error signal output when LED disconnection occurs and test mode
functions detect LED open or short conditions.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCCLED
XDWN2TST
GNDANA
TEST1
WDCAP
TSENA
IREF
VCCANA
XRST
DCDOUT5
DCDOUT4
DCDOUT3
DCDOUT2
DCDOUT1
DCDOUT0
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GNDLED
OUT0
OUT1
GNDLED
OUT2
OUT3
GNDLED
OUT4
OUT5
GNDLED
OUT6
OUT7
GNDLED
OUT8
OUT9
GNDLED
OUT10
OUT11
GNDLED
OUT12
OUT13
GNDLED
OUT14
OUT15
GNDLED
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TEST4
TEST3
GNDLOG
TEST2
DPOL
DCENA
BCENA
VCCLOG
VCCIF
DCDIN5
DCDIN4
DCDIN3
DCDIN2
DCDIN1
DCDIN0
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
PZP PACKAGE
(TOP VIEW)
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCOIN
RBIAS
MAG0
MAG1
MAG2
PDOUT
GSPOL
GSCLK
BLANK
XENABLE
XOE
DCLK
XLATCH
DCCLK
XDCLAT
RSEL0
RSEL1
LEDCHK
OPEN
WDTRG
XDOWN1
XDOWN2
BOUT
XGSOUT
XPOUT
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
functional block diagram
XOE
BCENA
DCLK
DPOL
XENABLE
DCLK
Control
DOUT
t u
DIN 0–9 ,
XLATCH
t u
DCDINt0–5u,
1 x 10 bit B.C.
Data Shift Register
Data Latch
16 x 10 bit
Data Shift Register
RSEL 0–1
..........
8
16 x 10 bit
Data Latch
XDCLAT,
DCCLK
..........
t u
MAG 0–2 , GSPOL,
GSCLK, RBIAS,
VCOIN, PDOUT
PLL
10 bit
Clock Countor
XPOUT
XGSOUT
16 x 10 bit
Data Comparator
BLANK
XRST
WDCAP
WDTRG
t0–9u
..........
16 bit
LED Driver+LOD
WDT
LEDCHK
XDOWN2TST
..........
TSENA
BOUT
OUT0
···
OUT15
XDOWN1
XDOWN2
16 bit
Current Controller
TSD
..........
IREF
16 x 6 bit
D.C. Data Latch
DCENA
..........
16 x 6 bit
D.C. Data Shift Register
DCDOUT
t0–5u
B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels.
D.C (Dot Control) : Adjustment for brightness deviation between dots.
NOTE: All the input terminals are with Schmitt-triggered inverters except RBIAS, VCOIN, PDOUT, IREF, and WDCAP.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
functional block diagram for shift register and data latch
XOE
DATA
S/R
DCLK
DPOL
XENABLE
DCLK
Controller
a
DATA
LATCH
1†
10 16
DATA
Comparator
A
b
B
DCCLK
10
10 16
a
c
10
b
A
10
0
c
10
DIN<0–9>
HI–Z
A
10
b
DCDIN<0–5>
DOUT<0–9>
10
a
B
10
1
10
B.C.
S/R
10
B.C.
LATCH
Clock Counter
Current Controller
c
6
a
XLATCH
XDCLAT
A
b
B
6
c
DCDOUT<0–5>
2‡
6
RSEL<0–1>
D.C.
S/R
6 16
D.C.
LATCH
6 16
1
6 16
0
6 16
BCENA
Default
DCENA
† 1 : Connect to 16th 10 bit bus
‡ 2 : Connect to 16th 6 bit bus
B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels.
D.C. (dot control) : Adjustment for brightness deviation between dots.
RSEL
4
CONNECTION
RSEL1
RSEL0
0
0
A – a, B – c
0
1
A – b, B – c
1
0
A–c
1
1
INHIBIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DATA
Comparator
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
schematic
Input
VCCIF
INPUT
GNDLOG
DOUT0–9, DCDOUT0–5, XGSOUT, XPOUT, BOUT
VCCLOG
OUTPUT
GNDLOG
XDOWN1, XDOWN2
XDOWN1, XDOWN2
GNDLOG
OUTn
OUTn
GNDLED
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Terminal Functions
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TERMINAL
NAME
BCENA
94
I/O
DESCRIPTION
I
Brightness control enable. When BCENA is low, brightness control latch is set to the default
value. The output current value in this status is 100% of setting the value by an external resistor.
The frequency division ratio of GSCLK is 1/1. When BCENA is high, writing to brightness control
latch is enabled.
BLANK
67
I
Blank(light off). When BLANK is high, all outputs of the constant current driver are turned off.
When GSPOL is high, the output is turned on (LED on), synchronizing to the falling edge of
GSCLK after the next rising edge of GSCLK, when BLANK goes from high to low. When GSPOL
is low, the output is turned on (LED on), synchronizing to the rising edge of GSCLK after the
next falling edge of GSCLK, when BLANK goes from high to low.
BOUT
53
O
BLANK buffered output
DCCLK
62
I
Clock input for data transfer. The input data is from DCDIN (port B) , output data at DCDOUT,
and all data on the shift register for dot correction data, from DCDIN, is shifted by 1 bit
synchronizing to the rising edge of DCCLK.
DCDIN0 –
DCDIN5
86,87,88,
89,90,91
I
Input for 6 bit parallel data (port B). These terminals are used as a shift register input for dot
correction data.
DCDOUT0 –
DCDOUT5
40,39,38,
37,36,35
O
Output for 6 bit parallel data (port B). These terminals are used as a shift register output for dot
correction data.
DCENA
95
I
Latch enable for dot correction data. When DCENA is low, the latch is set to the default value.
At this time, the output current value is 100% of the value set by an external resistor.
DCLK
64
I
Clock input for data transfer. The input data is from DIN (port A) , all data on the shift register
selected by RSEL, 1 and output data at DOUT is shifted by 1 bit synchronizing to DCLK. Note
that synchronizing to either the rising or falling edge of DCLK depends on the value of DPOL.
DIN0 – DIN9
76,77,78,79,80,
81,82,83,84,85
I
Input for 10 bit parallel data (port A). These terminals are inputs to the shift register for gray scale
data, brightness control, and dot correction data. The register selected is determined by RSEL0,
1.
DOUT0 –
DOUT9
50,49,48,47,46,
45,44,43,42,41
O
Output for 10 bit parallel data (port A). These terminals are outputs to the shift register for gray
scale data, brightness control, and dot correction data. The register selected is determined by
RSEL0, 1.
DPOL
96
I
Select the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When
DPOL is low, the falling edge of DCLK is valid.
GNDANA
28
Analog ground (internally connected to GNDLOG and GNDLED)
GNDLOG
98
Logic ground (internally connected to GNDANA and GNDLED)
GNDLED
1,4,7,10,13,
16,19,22,25
LED driver ground (internally connected to GNDANA and GNDLED)
GSCLK
68
I
Clock input for gray scale. When MAG0 to MAG2 are all low, GSCLK is used for pulse width
control, and GSCLK is used for PLL timing control when either MAG is not low. The gray scale
display is accomplished by lighting LEDs on until the number of GSCLK or PLL clocks counted
is equal to data latched.
GSPOL
69
I
Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When
GSPOL is low, the falling edge of GSCLK is valid.
IREF
32
I/O
Constant current value setting. LED current is set to the desired value by connecting an external
resistor between IREF and GND. The 38 times current compares current across the external
resistor sink on the output terminal.
LEDCHK
58
I
LED disconnection detection enable. When LEDCHK is high, LED disconnection detection is
enabled and XDOWN2 is valid. When LEDCHK is low, LED disconnection detection is disabled.
73,72,71
I
PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set.
MAG0 – MAG2
OPEN
6
NO.
57
TEST. Factory test terminal. OPEN should be opened.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Terminal Functions (Continued)
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TERMINAL
I/O
DESCRIPTION
NAME
NO.
OUT0–DOUT15
2,3,5,6,8,9,11,12,
14,15,17,18,20,21,
23,24
O
Constant current output
PDOUT
70
I/O
Resistor connection for PLL feedback adjustment
RBIAS
74
I/O
Resistor connection for PLL oscillation frequency setting
60
59
I
Input/output port selection and shift register data latch switching.
When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected
to port A and the dot correction register latch is selected to port B.
When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to
port A and the dot correction register latch is selected to port B.
When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port
A and no register latch is selected to port B.
TEST1–TEST4
29,97,99,100
I
TEST. Factory test terminal. These terminals should be connected to GND.
THERMAL PAD
package bottom
RSEL0
RSEL1
Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.
TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is
low, TSD is disabled.
TSENA
31
I
VCOIN
75
I/O
VCCANA
33
Analog power supply voltage
VCCLOG
93
Logic power supply voltage
VCCIF
92
Interface power supply voltage
VCCLED
26
LED driver power supply voltage
WDTRG
56
I
WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan
signal can be monitored by turning the constant current output off and protecting the LED
from damage when the scan signal stopped during the constant period designed.
WDCAP
30
I/O
WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor
between WDCAP and GND. When WDCAP is directly connected to GND, WDT function
is disabled. In this case, WDTRG should be tied to a high or low level.
Capacitance connection for PLL feedback adjustment
XDCLAT
61
I
Data latch for dot correction. When XDCLAT is high, data on the shift register for dot
correction data from DCDIN (port B) goes through latch. When XDCLAT is low, data is
latched. Accordingly, if data on the shift register is changed during XDCLAT high, this new
value is latched (level latch).
XDOWN1
55
O
Shutdown. XDOWN1 is configured as an open collector. It goes low when constant current
output is shut down by WDT or TSD function.
XDOWN2
54
O
LED disconnection detection output. XDOWN2 is configured as an open collector.
XDOWN2 goes low when an LED disconnection is detected.
XDWN2TST
27
I
Test for XDOWN2. When XDWN2TST is low, XDOWN2 goes low. (This terminal is internally
pulled up with 50 kΩ)
XENABLE
66
I
DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the
valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred.
XGSOUT
52
O
Clock output for gray scale. When MAG0 to MAG2 are all low, the clock with GSCLK inverted
appears on this terminal. When either MAG is not low, PLLCLK appears on this terminal.
XLATCH
63
I
Latch. When XLATCH is high, data on the shift register from DIN (port A) goes through latch.
When XLATCH is low, data is latched. Accordingly, if data on the shift register is changed
during XLATCH high, this new value is latched (level latch).
XOE
65
I
Data output enable. When XOE is low, DOUT0–9 terminals are driven. When XOE is high,
DOUT0–9 terminals go to a high-impedance state.
XPOUT
51
O
GSPOL output inverted
XRST
34
I
Blank (Light off). When XRST is low, all the output of the constant current driver is turned
off. (This terminal is internally pulled up with 50 kΩ)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
absolute maximum ratings (see Note 1)†
Logic supply voltage, VCCLOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Supply voltage for interface circuit, VCCIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Supply voltage for constant current circuit, VCCLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Analog supply voltage, VCCANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output current (dc), IO(LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mA
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V
Output voltage range, VO(DOUT), VO(DCDOUT), VBOUT, VXPOUT
and VXGSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V
Output voltage range, VO(OUT) and VO(XDOWNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 16 V
Storage temperature range, Tstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Continuous total power dissipation at (or below) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W
Power dissipation rating at (or above) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.2 mW/°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GNDLOG terminal.
recommended operating conditions
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dc characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Logic supply voltage, VCCLOG
4.5
5
5.5
V
Supply voltage for interface circuit,
VCCIF
3.0
5
5.5
V
Supply voltage for constant current
circuit, VCCLED
4.5
5
5.5
V
Analog power supply, VCCANA
4.5
5
5.5
V
Voltage between VCC, VDIFF1
VDIFF1 = VCCLOG – VCCANA
VCCLOG – VCCLED
VCCANA – VCCLED
– 0.3
0
0.3
V
Voltage between GND, VDIFF2
VDIFF2 = GNDLOG – GNDANA
GNDLOG – GNDLED
GNDANA – GNDLED
– 0.3
0
0.3
V
Voltage applied to constant current
output, VOUT
OUT0 to OUT15 off
15
V
0.8 VCCLOG
VCCLOG
V
GNDLOG
0.2 VCCLOG
V
High-level input voltage, VIH
Low-level input voltage, VIL
High–level output current, IOH
Low–level output current, IOL
VCCLOG = 4.5 V,
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
BOUT, XGSOUT, XPOUT
– 1.0
VCCLOG = 4.5V,
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
BOUT, XGSOUT, XPOUT
1.0
mA
VCCLOG = 4.5 V, XDOWN1, XDOWN2
Constant output current, IOLC
OUT0 to OUT15
Operating free-air temperature range,
TA
PLL capacitance, CVCO
PLL resistor, RBIAS
At 16 MHz oscillation
PLL resistor, RPD
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
mA
5
80
mA
– 20
85
°C
1
µF
22
kΩ
30
kΩ
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
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ac characteristics, VCCLOG= VCCANA = VCCLED = 4.5 V to 5.5 V, TA = – 20 to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCLK DCCLK clock frequency,
DCLK,
frequency fDCLK,
DCLK fDCCLK
MIN
TYP
MAX
At single operation
20
At cascade operation
15
DCLK, DCCLK pulse duration (high or low level), twh/twl
20
GSCLK clock frequency, fGSCLK
GSCLK pulse duration (high or low level), twh/twl
WDT pulse duration (high or low level), twh/twl
40
XLATCH, XDCLAT pulse duration (high level), twh
30
Rise / fall time, tr/tf
MHz
ns
8
MHz
8
MHz
40
WDT clock frequency, fWDT
UNIT
ns
ns
ns
100
ns
Setup time, tsu
DINn – DCLK
DCDINn – DCCLK
BLANK – GSCLK
XENABLE – DCLK
XLATCH – DCLK
XLATCH – GSCLK
XDCLAT – DCCLK
RSEL – DCLK
RSEL – DCCLK
RSEL – XLATCH
RSEL – XDCLAT
5
5
10
15
10
10
10
10
15
30
15
ns
Hold time, th
DINn – DCLK
DCDINn – DCCLK
XENABLE – DCLK
XLATCH – DCLK
XDCLAT – DCCLK
RSEL – DCLK
RSEL – DCCLK
RSEL – XLATCH
RSEL – XDCLAT
15
15
20
30
20
20
20
20
10
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
electrical characteristics, LEDCHK = L,
MIN/MAX: VCCLOG = VCCANA = VCCLED = 4.5 V to 5.5 V, TA = – 20 to 85°C
TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted)
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PARAMETER
TEST CONDITIONS
MIN
DOUTn, DCOUTn, XGSOUT, XPOUT,
BOUT IOH = –1 mA
VOH
High-level output voltage
VOL
Low-level output voltage
g
DOUTn, DCOUTn, XGSOUT, XPOUT,
BOUT IOL = 1 mA
Input current
XDOWN1, XDOWN2 IOL = 5 mA
VIN = VCCLOG or GNDLOG
II
ILOG
IANA
ILED
Supply current (logic)
Supply current (analog)
Supply current (constant current driver)
TYP
MAX
VCCLOG
–0.5
UNIT
V
0.5
V
0.5
±1
µA
Input signal is static,
TSENA = H, WDCAP = OPEN,
No PLL is used
0.1
mA
Input signal is static,
TSENA = H, WDCAP = OPEN,
PLL multiple ratio = 1042
1
mA
Data transfer,
DCLK = 20 MHz, GSCLK = 8 MHz
No PLL is used
35
45
Data transfer,
DCLK = 20 MHz, GSCLK = 15 kHz
PLL multiple ratio = 1042
39
49
BLANK = L, RIREF = 1200 Ω
6.5
8
BLANK = L, RIREF = 600 Ω
LED turn off, RIREF = 1200 Ω
13
15
12
20
LED turn off, RIREF =600 Ω
20
35
VOUT = 1V, RIREF = 1200Ω
All output bits turn on
12
20
VOUT = 1V, RIREF = 600 Ω
All output bits turn on
20
35
mA
mA
mA
IOLC1
Constant output current (includes error
between bits)
VOUT = 1V, VIREF = 1.21 V,
RIREF = 1200Ω
35
40
45
mA
IOLC2
Constant output current (includes error
between bits)
VOUT = 0.7 V, VIREF = 1.21 V,
RIREF = 600 Ω
70
80
90
mA
0.1
µA
XDOWN1,2 (VXDOWNn = 15 V)
1
µA
DOUTn, DCDOUTn
(VOUTn = VCCLOG or GND)
1
µA
OUT0 to OUT15 (VOUTn = 15 V)
IOLK
Constant out
output
ut leakage current
∆IOLC
Constant output current error between bit
VCCLOG=VCCANA=VCCLED=
VOUT = 1 V, RIREF = 600 Ω
All output bits turn on
I∆OLC1
Changes in constant output current
depend on supply voltage
I∆OLC2
5 V,
± 1%
± 4%
VOUT = 1V, RIREF = 600 Ω,
VIREF = 1.21 V
±1
±4
%/V
Changes in constant output current
depend on output voltage
VOUT = 1 V to 3 V, RIREF = 600 Ω,
VIREF = 1.21 V,
1 bit output turn on
±1
±3
%/V
Ttsd
Twdt
TSD detection temperature
Junction temperature
150
160
170
°C
WDT detection temperature
No external capacitor
5
10
15
ms
VIREF
Voltage reference
BCENA = L, RIREF = 590 Ω,
VLEDDET
Voltage applied to LED disconnection
detection
PLLJITTER
PLL jitter
10
1.21
0.2
RBIAS = 22 kΩ, RPD = 30 kΩ,
CVCO = 0.1 µF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
0.3
0.4
0.4%
2%
V
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
switching characteristics, CL = 15pF,
MIN/MAX: VCCLOG= VCCANA = VCCLED = 4.5 V to 5.5 V, TA = – 20 to 85°C,
TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted)
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PARAMETER
TEST CONDITIONS
MIN
DOUTn, DCDOUTn
tr
tf
Rise time
Fall time
XGSOUT, BOUT, XPOUT
30
12
30
110
DOUTn, DCDOUTn
10
30
10
30
XGSOUT, BOUT, XPOUT
30
45
BLANK↑ – OUT0
40
50
105
BLANK – BOUT
10
20
40
GSCLK – XGSOUT
10
20
40
DCLK – DOUTn
15
30
45
DCLK – DCDOUTn
15
30
45
DCCLK – DCDOUTn
15
30
45
XOE↓ – DOUTn (see Note 3)
10
20
35
XOE↑ – DOUTn (see Note 3)
10
15
25
RSEL – DOUTn
10
20
40
GSCLK – OUT0 (see Note 2)
LEDCHK – XDOWN2
UNIT
ns
ns
130
OUTn+1 – OUTn
Propagation delay time
MAX
12
OUTn (see Figure 1)
OUTn (see Figure 1)
td
TYP
7
ns
1000
NOTES: 2. MAG0 to MAG2 are all low level.
3. Until DOUT will be turned on (drive) or turned off (Hi-Z).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC
51 Ω
VCC
IREF
OUTn
GND
600 Ω
15pF
Figure 1. Rise Time and Fall Time Test Circuit for OUTn
VIH or VOH
100%
VIH
90%
50%
10%
VIL
tr
VIL or VOL
0%
tf
td
100%
VIH
50%
100%
50%
0%
VIL
twh
0%
twl
Figure 2. Timing Requirements
12
VIH or VOH
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VIL or VOL
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
setting for output constant current value
On the constant current output terminals (OUT0–15), approximately 38 times the current which flows through
external resistor, RIREF (connected between IREF and GND), can flow. The external resistor value is calculated
using the following equation:
RIREF (Ω) ≅ 38 × 1.21 (V)/IO(LC)(A) where both BCENA and DCENA are low.
Note that more current flows if IREF is connected to GND directly.
constant output current operation
If GSPOL is high, the constant current output turns on the sink constant current if all the gray scale data in the
gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale
clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 10 bit gray
scale counter. Then, the output counted corresponding to the gray scale data is turned off (stop to sink constant
current). The gray scale clock can be selected from GSCLK or that generated by internal PLL circuitry. If the
shift register for gray scale is updated during XLATCH high, data on the gray scale data latch is also updated
affecting the constant current output number of the gray scale. Accordingly, during the on-state of the constant
current output, keep the XLATCH to a low level and hold the gray scale data latch.
input/output port and shift register selection
The TLC5910 supplies two parallel input ports such as DIN (10 bits) and DCDIN (6 bits). The DIN and DCDIN
ports also supply DCLK and DCCLK for shift clock, XLATCH and XDCLAT for latch, and DOUT and DCDOUT
for output, respectively. The device has three types of shift register latches, gray scale data, brightness control,
and dot correction. The port and shift register can be selected by RSEL0 and RSEL1. Table 1 shows the
selection using RESL0 and RSEL1. Note that the RSELn setting should be done at DCLK low, (when DPOL
is high, and at DCLK high when DPOL is low). When only port A is used, DCDIN, DCDOUT, DCCLK, and
XDCLAT should be connected to GND.
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Table 1. Shift Register Latch Selection
SELECTED SHIFT REGISTER LATCH
RSEL1
RSEL0
PORT A
PORT B
DIN, DCLK, XLATCH, DOUT
DCDIN, DCCLK, XDCLATCH
DCDOUT
L
L
Gray scale data displayed
Dot correction
Dot correction
L
H
Brightness control
Dot correction
Dot correction
H
L
Dot correction (see Note)
Not connected
Dot correction
H
H
N/A (inhibit)
N/A (inhibit)
N/A (inhibit)
NOTE: Zero is output to DOUT6 to DOUT9.
shift register latch for gray scale data
The shift register latch for gray scale data is configured with 16 x 10 bits. The gray scale data, configured with
10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023
(00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on(light off). When
the gray scale data is 1023, the time is longest, and it turns on during time of 1023 clocks from the gray scale
clock. The configuration of the shift register and latch for gray scale data is shown in Figure 3.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
Latch for Gray Scale Data
XLATCH
OUT15
Data
OUT14
Data
OUT1
Data
OUT0
Data
(10 bits)
(10 bits)
(10 bits)
(10 bits)
2nd byte
DIN9 MSB
DIN0 LSB
1st byte
DIN9 MSB
DIN0 LSB
Shift Register for Gray Scale Data
DOUT0 to 9
16th byte
DIN9 MSB
DIN0 LSB
15th byte
DIN9 MSB
DIN0 LSB
DCLK
DIN0 to 9
Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data
shift register latch for brightness control
The shift register latch for brightness control is configured with 1 × 10 bits. Using the shift register latch for
brightness control, the division ratio of the gray scale clock can be set and the output current value on constant
current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not
initialized. Data should be written to the shift register latch prior to lighting-on (BLANK=L) when these functions
are used. Also, the latch value for brightness control cannot be rewritten when the constant current output is
turned on. When these functions are not used, the latch value can be set to the default value setting BCENA
to low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current control to maintain
the compatibility with TLC5901/02/03 family. The configuration of the shift register and the latch for brightness
control is shown below.
Latch for Brightness Control
Gray Scale Clock Division Ratio Data Set
XLATCH
0
0
0
MSB
Current Data Adjusted On Constant Current Output
0
1
LSB
MSB
1
1
1
1
1
(Note A)
LSB
Shift Register for Brightness Control
DOUT0 to 9
DIN8
DATA
DIN7
DATA
DIN6
DATA
DIN5
DATA
DIN4
DATA
DIN3
DATA
DIN2
DATA
DIN1
DATA
DIN0
DATA
DIN9
DATA
DCLK
DIN0 to 9
Note A: Indicates default value at BCENA low.
Figure 4. Relationship Between Shift Register and Latch for Brightness Control
shift register latch for dot correction
The shift register latch for dot correction is configured with 16 × 6 bits. Using the shift register latch for dot
correction, the current value on the constant current output can be set individually. When powered up, the latch
data is indeterminate and the shift register is not initialized. Data should be written to the shift register latch prior
to lighting-on (BLANK=L) when these functions are used. Also, the latch value for dot correction cannot be
rewritten when the constant current output is turned on. When these functions are not used, the latch value can
be set to the default value setting of DCENA to low level (connect to GND). The configuration of the shift register
and the latch for dot correction is shown in Figure 5.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
Latch for Dot Correction
XLATCH
OUT15
Data
OUT14
Data
OUT1
Data
OUT0
Data
(6 bits)
(6 bits)
(6 bits)
(6 bits)
2nd byte
DCDIN5 MSB
DCDIN0 LSB
1st byte
DCDIN5 MSB
DCDIN0 LSB
Shift Register for Dot Correction
DCDOUT0 to 5
16th byte
DCDIN5 MSB
DCDIN0 LSB
15th byte
DCDIN5 MSB
DCDIN0 LSB
DCCLK
DCDIN0 to 5
Using Port B (RSEL0=L or H, RSEL1=L)
Latch for Dot Correction
XLATCH
OUT15
Data
OUT14
Data
OUT1
Data
OUT0
Data
(6 bits)
(6 bits)
(6 bits)
(6 bits)
2nd byte
DCDIN5 MSB
DCDIN0 LSB
1st byte
DCDIN5 MSB
DCDIN0 LSB
Shift Register for Dot Correction
DOUT0 to 5
16th byte
DCDIN5 MSB
DCDIN0 LSB
15th byte
DCDIN5 MSB
DCDIN0 LSB
DCLK
DIN0 to 5
Using Port A (RSEL0=L, RSEL1=H)
Figure 5. Relationship Between Shift Register and Latch for Dot Correction
write data to shift register latch
The shift register latch written to is selected using the RSEL0 and RSEL1 terminals. At port A, the data is applied
to the DIN data input terminal and clocked into the shift register synchronizing to the rising edge of DCLK after
XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal and clocked into the
shift register synchronizing to the rising edge of DCCLK. The shift register for the gray scale data is configured
with 16 × 10 bits and the shift register for dot correction is configured with 16 x 6 bits resulting in sixteen times
DCLK, and the shift register for brightness control is configured with 1 x 10 bits resulting in one times DCLK.
At number of DCLK input for each case, data can be written into the shift register. In this condition, when
XLATCH at port A or XDCLAT at port B is pulled high, data in the shift register is clocked into latch (data through),
and when XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
brightness control function
By writting data into the brightness control latch, the current on all constant current outputs can be adjusted to
control the variation of brightness between ICs and the division ratio for the gray scale clock can be set to control
the variation of brigtness for the total panel system. Furthermore, by writing data into the dot correction latch,
the current on each constant current output can be adjusted.
output current adjustment on all constant current outputs – brightness adjustment between ICs
By using the lower 6 bits of the brightness control latch, the output current can be adjusted to 64 steps. 1 step
of 0.8% current ratio between 100% and 50.8% when the set output current is 100% by an external resistor (note
that the current value is lower if the constant current output is corrected using the dot correction function). By
using this function, the brightness control between modules (ICs) can be adjusted sending the desired data
externally even if the ICs are mounted on a print-circuit board. When BCENA is pulled low, output current is set
to 100%.
Table 2. Relative Current Ratio For Total Constant Current Output
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CODE
CURRENT RATIO
(%)
20
(mA)
80
(mA)
VIREF
(TYP)
MSB 000000 LSB
50.8
10.2
40.6
0.61
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
111110
111111†
99.2
19.8
79.7
1.20
100
20.0
80.0
1.21
† BCENA is low.
frequency division ratio setting for gray scale clock – panel brightness adjustment
By using the upper 4 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/16.
If the gray scale clock is set to 16 times the speed (1024×16=16384) of frequency during horizontal scanning
time, the brightness can be adjusted to 16 steps selecting the frequency division ratio. By using this function,
the total panel brightness can be adjusted at once, and it applies to the brightness of day or night circumstances.
When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can
be adjusted (see Table 3).
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Table 3. Relative Brightness Ratio For Total Constant Current Output
CODE
FREQUENCY
DIVISION RATIO
RELATIVE BRIGHTNESS RATIO
(%)
MSB 0000 LSB†
1/1
6.3
.
.
.
.
.
.
.
.
.
.
.
.
1110
1/15
93.8
1/16
100
1111
† BCENA is low.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
output current adjustment on each constant current output – LED brightness adjustment
By using the 6 bits of the dot correction latch, the output current on each constant current output can be adjusted
to 64 steps. 1 step of 0.8% current ratio between 100% and 50.8% when the set output current is 100% by an
external resistor at 111111h of the latched value and the lower 6 bits of the brightness control register. By using
this function, the brightness deviation due to LED brightness variation can be minimized. When DCENA is pulled
low, the output current is set to 100% without dot correction.
Table 4. Relative Current Ratio By Constant Current Output
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CODE
CURRENT RATIO (%)
MSB 000000 LSB
50.8
IOLC=40 (mA)
20.3
.
.
.
.
.
.
.
.
.
.
.
.
111110
111111†
99.2
39.7
100
40
† DCENA is low.
clock edge selection
The high speed clock signal is delayed due to the duty ratio change through multiple stages of an IC or through
the module stages shown in Figure 6.
IN
A
OUT
IN
IN
IN’
A
A’
OUT
OUT
a) Propagate through multiple stages buffer
with slow falling edge
A
A’
OUT
OUT’
b) Insert inverter between buffers
Figure 6. Clock Edge Selection
As shown in Figure 6 a), if the falling at the internal buffer is behind the rising, the clock will disappear as multiple
cascade connections are made. To resolve this problem, the duty ratio can be held unchanged using the
connection as shown in Figure 6 b) if the valid clock edge can be selected (arrow in Figure 6). Note that the clock
delay is not avoided even in this case.
The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function,
the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL.
Thus the degradation for the duty ratio can be reduced. The relation between each signals is shown in
Table 5.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
clock edge selection (continued)
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Table 5. Valid Edge For DCLK and GSCLK
DPOL
DCLK valid edge
Operation at XENABLE = H
H
DCLK↑
Pull DCLK to low level
L
DCLK↓
Pull DCLK to high level
GSPOL
GSCLK valid edge
PLL operation
H
GSCLK↑
Synchronize to the high level of DCLK
L
GSCLK↓
Synchronize to the low level of DCLK
The device supplies XPOUT and XGSOUT output terminals for the cascade operation which invert GSPOL and
GSCLK respectively. It also supplies the BOUT output terminal as a buffered BLANK to make easy timing with
GSCLK and XGSOUT.
gray scale clock generation
When MAG<0:2> are all low, the clock input from GSCLK terminal is used as the gray scale clock with no
change, and except for this case internal PLL generates the clock for the gray scale control clock. When using
the PLL, the gray scale clock is generated by adjusting the clock having the same number of pulses as the
multiple ratio of the GSCLK reference period (when GSCLK and GSPOL are keeping the same level). Note that
the reference period is required above 40% of the GSCLK period. The ratio in this case is determined depending
on MAG 0 to MAG 2 as shown in Table 6.
When using PLL, internal PLLCLK is clocked out at the XGSOUT terminal. Therefore, this clock can be utilized
for other devices on the same print-circuit board. Note that the number of ICs connected is limited depending
on the frequency.
Table 6. PLL Multiple Ratio
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18
MAG2
MAG1
MAG0
MULTIPLE RATIO
XGSOUT
L
L
L
Inverted GSCLK
L
L
H
1 (Signal to control GSCLK by GSPOL)
28+6(=262)
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
29+10(=522)
210+18(=1042)
211+34(=2082)
212+66(=4162)
213+130(=8322)
214+258(=16642)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PLLCLK
(Gray scale clock internally generated)
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
gray scale clock generation (continued)
MAG<0–2>
Except all low level
Except all low level
GSPOL
GSCLK
XGSOUT
PLLCLK
Same number of pulse as ratio
Same number of pulse as ratio
a) GSPOL is low
a) GSPOL is high
Figure 7. Gray Scale Clock Generation
The oscillation frequency bandwidth as referenced for PLL can be set by an external resistor connected
between RBIAS and GND. The relation between the external resistor and oscillation frequency is shown in
Table 7.
ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
Table 7. PLL Oscillation Frequency
RBIAS
22 kΩ
30 kΩ
62 kΩ
120 kΩ
FREQUENCY
13 to 20 MHz
8 to 14 MHz
4 to 9 MHz
3 to 5 MHz
To make PLL stabilization, a resistor and acapacitor connection is required between VCOIN, PDOUT, and GND.
The recommended value is shown in the following table in Figure 8.
PDOUT
VCOIN
CVCO
Rpd
Recommeded Value
0.1 to 1 µF
Rpd
22 to 62 kΩ
CVCO
Figure 8. Resistor and Capacitor Connection
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
protection
This device incorporates WDT and TSD functions. If WDT or TSD functions, the constant current output is
stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be
detected immediately. Since the XDOWN1 output is configured as an open collector, outputs of multiple ICs are
brought together.
WDT (watchdog timer)
The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapses after the
signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (signal to control line
displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned
off. This prevents the LED from burning and damage caused by continuous LED turnon at the dynamic scanning
operation. The detection time can be set using an external capacitor, Cext. The typical value is approximately
10 ms without a capacitor, 160 ms with a 1000 pF capacitor, and 1500 ms with a0.01 µF capacitor. During static
operation, the WDT function is disabled connecting WDCAP to GND (high or low level should be applied to
WDTRG). Note that normal operations will resume changing the WDTRG level when WDT functions.
WDT operational time: T (ms) ≅ 10 + 0.15 × Cext (pF)
t – Time – ms
TLC5910
Scan Signal
1500
WDTRG
WDCAP
Cext
160
10
0
0.001
0.01
Cext – External Capacitor – µF
Figure 9. WDT Operational Time and Usage Example
TSD (thermal shutdown)
When the junction temperature exceeds the limit, TSD starts to function and turns constant current output off,
and XDOWN1 goes low. When TSD is used, TSENA should be pulled high. When TSD is not used, TSENA
should be pulled low. To recover from constant current output off-state to normal operation, the power supply
should be turned off or TSENA should be pulled low once.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
LOD function (LED open detection)
When LEDCHK is low, the LED disconnection detection function is disabled and XDOWN2 goes to a
high-impedance state. When LEDCHK is high, the LED disconnection detection function is enabled, and
XDOWN2 goes low if any LED is disconnected monitoring OUTn terminals to be turned on. This function is
operational for sixteen OUTn terminals individually. To know which constant current output is disconnected, the
level of XDOWN2 is repeatedly checked 16 times from OUT0 to OUT15 turning one constant current output on.
The power supply voltage should be set so the constant current output is applied to above 0.4 V when the LED
is lighting normally. Also, since the time of approximately 1000 ns is required from turning the constant current
output on to XDOWN2 output, the gray scale data to be turned on during that period should be applied.
Table 8 is an example for XDOWN2 output status using four LEDs .
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Table 8. XDOWN2 Output Example
LED NUMBER
1
2
3
4
LED STATUS
GOOD
NG
GOOD
NG
OUTn
ON
ON
ON
ON
XDOWN2
LOW (by case 2, 4)
LED NUMBER
1
2
3
LED STATUS
GOOD
NG
GOOD
NG
OUTn
ON
ON
OFF
OFF
DETECTION RESULT
GOOD
NG
GOOD
GOOD
LED NUMBER
1
2
3
LED STATUS
GOOD
NG
GOOD
NG
OUTn
OFF
OFF
OFF
OFF
DETECTION RESULT
GOOD
GOOD
GOOD
GOOD
XDOWN2
4
LOW (by case 2)
XDOWN2
4
HIGH–IMPEDANCE
noise reduction
concurrent switching noise reduction
Concurrent switching noise has the potential to occur when multiple outputs turn on or off at the same time. To
prevent this noise, the device has a delay output terminal such as XGSOUT and BOUT for GSCLK (gray scale
clock) and BLANK (blanking signal) respectively. Connecting these outputs to the GSCLK and BLANK terminals
of next stage IC allows differences of the switching time between ICs. When GSCLK is output to GSOUT through
the device, duty will be changed between input and output. The number of stages to be connected will be limited
depending on frequency.
delay between constant current output
The constant current output has a delay time of approximately 20 ns between outputs. This means
approximately 300 ns delay time exists between OUT0 and OUT15. This time differences by delay reduces the
concurrent switching noise.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
power supply
The followings should be taken into consideration:
D
D
VCCLOG, VCCANA and VCCLED should be supplied by a single power supply to minimize voltage
differences between these terminals.
The bypass capacitor should be located between the power supply and GND to eliminate the variation of
power supply voltage.
GND
Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally
connected to reduce noise influence.
thermal pad
The thermal pad should be connected to GND to eliminate the noise influence when it is connected to the bottom
side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with
better thermal conductivity.
4.7
3.2
2.4
1.48
0
–20
Output Voltage (Constant Current) – V
PD – Total Power Dissipation – W
†
power rating – free-air temperature
0
0
25
85
TA – Free–Air Temperature – °C
† VCCLOG=VCCANA=VCCLED=5.0V, IOLC = 80mA, ICC is typical value.
NOTES: A. IC is mounted on PCB.
PCB size: 102 × 76 x 1.6 [mm3], four layers with the internal two layer being plane. The thermal pad is soldered to the PCB pattern
of 10 × 10 [mm2]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
B. The thermal impedance will be varied depending on mounting conditions. Since the PZP package established low thermal
impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with a low thermal impedance.
C. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad.
Figure 10. Power Rating
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
constant output current
90
80
70
I OLC – mA
60
50
40
30
20
10
0
0.1
1.0
10.0
RIREF – kΩ
Conditions: VOUT = 1.0V, VIREF = 1.21V
V IREF(V)
R IREF(k )
≅
I OLC(mA)
W
W
R IREF (k ) ≅
38
47
I OLC(mA)
NOTE: The brightness control and dot corrected value are 100%. The resistor, RIREF, should be located as close to the IREF terminal as possible
to avoid the noise influence.
Figure 11. Current on Constant Current Output vs External Resistor
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
XENABLE
1/fDCLK
tsu (XENABLE–DCLK)
th (XENABLE–DCLK)
DCLK
tsu (DIN–DCLK)
twl (DCLK)
twh (DCLK)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DIN0
D00_A
D01_A
D02_A
D0E_A
D0F_A
D00_B
D0D_B
D0E_B
D0F_B
D00_C
D01_C
DIN9
D90_A
D91_A
D92_A
D9E_A
D9F_A
D90_B
D9D_B
D9E_B
D9F_B
D90_C
D91_C
th (DIN–DCLK)
th (XLATCH–DCLK)
tsu (XLATCH–DCLK)
XLATCH
twh (XLATCH)
DOUT0
Hi-Z
D00_A
D01_A
D0E_A
D0F_A
D00_B
DOUT9
Hi-Z
D90_A
D91_A
D9E_A
D9F_A
D90_B
td (XOE↓–DOUT)
td (DCLK–DOUT)
td (XOE↑–DOUT)
DPOL
DCLK
DPOL and DCLK can be replaced with the combination of these signals enclosed by the parenthesis (Both are inverted with each other).
Figure 12. Timing Diagram (Shift Register for Gray Scale Data)
Template Release Date: 7–11–94
XOE
TLC5910
LED DRIVER
SLLS392 –OVEMBER 1999
24
DPOL
BCENA
RSEL0
tsu (RSEL–XLATCH)
th (RSEL–XLATCH)
RSEL1
XOE
td (XOE↓–DOUT)
DPOL
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
XENABLE
tsu (RSEL–DCLK)
tsu (RSEL–DCLK)
DCLK
DIN0
D0_A
D0_B
D0_C
D0_J
D0_K
D0_L
D0_M
D0_N
D0_O
DIN9
D9_A
D9_B
D9_C
D9_J
D9_K
D9_L
D9_M
D9_N
D9_O
th (XLATCH–DCLK)
XLATCH
twh (XLATCH)
BCL_0–5
Default Value “1”
D<5:0>_A
Default Value “1”
D<9:6>_A
Default Value “0”
(Brightness Control Latch: Internal Signal)
BCL_6–9
Default Value “0”
tsu (RSEL–DOUT)
td (DCLK–DOUT)
td (XOE↑–DOUT)
D0_A
D0_C
D0_E
D0_F
D0_G
D0_H
D0_I
DOUT9
Hi-Z
D9_A
D9_C
D9_E
D9_F
D9_G
D9_H
D9_I
DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.
25
Figure 13. Timing Diagram (Shift Register for Brightness Control)
TLC5910
LED DRIVER
Hi-Z
SLLS392 – NOVEMBER 1999
DOUT0
tsu(XENABLE–DCLK)
RSEL1
tsu (RSEL–XDCLAT)
th (RSEL–XDCLAT)
tsu (RSEL–DCCLK)
tsu(RSEL–DCCLK)
DCCLK
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCDIN0
D0_A
D0_B
D0_C
D0_J
D0_K
D0_L
D0_M
D0_N
D0_O
DCDIN5
D5_A
D5_B
D5_C
D5_J
D5_K
D5_L
D5_M
D5_N
D5_O
th (XDCLAT–DCCLK)
XDCLAT
twh (XDCLAT)
DCL_0–15
Default Value “1”
Dx<15:0>_A
(Note)
(Dot Correction Latch: Internal Signal: 6 bit x 16)
Default Value “1”
td (DCCLK–DCDOUT)
DCDOUT0
D0_A
D0_C
D0_E
D0_F
D0_G
D0_H
D0_I
DCDOUT5
D5_A
D5_C
D5_E
D5_F
D5_G
D5_H
D5_I
NOTE: Register value is immediately before DCLAT↓.
Figure 14. Timing Diagram (Shift Register for Dot Correction : Using Port B)
Template Release Date: 7–11–94
RSEL0
TLC5910
LED DRIVER
SLLS392 –OVEMBER 1999
26
DCENA
RSEL0
RSEL1
tsu (RSEL–XLATCH)
th (RSEL–XLATCH)
XOE
td (XOE↓–DOUT)
DPOL
XENABLE
tsu (RSEL–DCLK)
tsu (RSEL–DCLK)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCLK
DIN0
D0_A
D0_B
D0_C
D0_J
D0_K
D0_L
D0_M
D0_N
D0_O
DIN9
D9_A
D9_B
D9_C
D9_J
D9_K
D9_L
D9_M
..
D9_N
.
D9_O
th (XLATCH–DCLK)
XLATCH
td (DCLK–DOUT)
twh (XLATCH)
tsu (RSEL–DOUT)
DOUT0
DOUT5
DOUT
<9:6>
td (XOE↑–DOUT)
Hi-Z
D0_A
D0_C
D0_E
D0_F
D0_G
D0_H
D0_I
Hi-Z
D5_A
D5_C
D5_E
D5_F
D5_G
D5_H
D5_I
td (XOE↓–DOUT)
Hi-Z
td (DCLK–DCDOUT)
..
.
D0_C
D0_E
D0_F
D0_G
D0_H
D0_I
D5_A
D5_C
D5_E
D5_F
D5_G
D5_H
D5_I
DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.
27
Figure 15. Timing Diagram (Shift Register for Dot Correction : Using Port A)
TLC5910
LED DRIVER
DCDOUT5
D0_A
SLLS392 – NOVEMBER 1999
DCDOUT0
BLANK
GSPOL
tsu (BLANK–GSCLK)
1/fGSCLK
td (BLANK–OUT0)
GSCLK
twl (GSCLK)
1/fWDT
twh (GSCLK)
WDTRG
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
twl (WDTRG)
twh (WDTRG)
td (GSCLK–OUT0)
td (GSCLK–OUT0)
td (BLANK–OUT0)
ON(Note A)
OFF
OUT0
(Note A)
OFF
td (OUTn+1–OUTn)
ON(Note A)
OFF
OUT15
(Note A)
OFF
td (OUTn+1–OUTn)
OUT1
twdt
OFF
OFF
ON(Note A)
OFF
(Note A)
(Note A)
OFF
OFF
(Note A)
(Note A)
NOTE A: ON or OFF, or ON time is varied depend on the gray scale data and BLANK.
HI–Z
XDOWN1
(Note B)
XDOWN2
td (GSCLK–XDOWN2)
BOUT
(Note B)
NOTE B: When LED is disconnected.
td (BLANK–BOUT)
td (GSCLK–XGSOUT)
XGSOUT
td (LEDCHK–XDOWN2)
td (LEDCHK–XDOWN2)
LEDCHK
GSPOL, GSCLK and XGSOUT can be replaced with signals inverted with each other.
Figure 16. Timing Diagram (Constant Current Output) – MAG0 to MAG2 are all zero
(Note B)
Template Release Date: 7–11–94
tsu (XLATCH–GSCLK)
TLC5910
LED DRIVER
SLLS392 –OVEMBER 1999
28
XLATCH
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
50
76
Thermal Pad
(see Note D)
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
1,05
0,95
0,25
0,15
0,05
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146929/A 04/99
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.. The demensions of the
thermal pad are 2 mm x 2 mm. The pad is centered on the bottom of the package.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
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Copyright  1999, Texas Instruments Incorporated