TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 D D D D D D D Drive Capability and Output Counts – 80 mA (Current Sink) x 16 Bits – 120 mA (Current Sink) x 8 Bits Constant Current Output Range – 5 to 80 mA/10 to 120mA (Selectable by MODE Terminal) (Current Value Setting for All Output Terminals Using External Resistor and Internal Brightness Control Register) Constant Current Accuracy – ± 4% (Maximum Error Between Bits) Voltage Applied to Constant Current Output Terminals – Minimum 0.4 V (Output Current 5 mA to 40 mA) – Minimum 0.7 V (Output Current 40 to 80 mA) 256 Gray Scale Display – Pulse Width Control 256 Steps Brightness Adjustment – Output Current Adjustment for 32 Steps (Adjustment for Brightness Deviation Between LED Modules) – 8 Steps Brightness Control by 8 Times Speed Gray Scale Control Clock (Brightness Adjustment for Panel) Error Output Signal Check – Check Error Output Signal Line Such as Protection Circuit When Operating D D D D D D D D D D D D D Data Output Timing Selectable – Select Data Output Timing for Shift Register Relative to Clock OVM (Output Voltage Monitor) – Monitor Voltage on Constant Current Output Terminals (Detect LED Disconnection and Short Circuit) WDT (Watchdog Timer) – Turn Output Off When Scan Signal Stopped TSD (Thermal ShutDown) – Turn Output Off When Junction Temperature Exceeds Limit Data Input – Clock Synchronized 8 Bit Parallel Input (Schmitt-Triggered Input) Data Output – Clock Synchronized 8 Bit Parallel Output (3-State Output) Input Signal Level . . . CMOS Level Power Supply Voltage . . . 4.5 V to 5.5 V Maximum Output Voltage . . . 17 V (Max) Data Transfer Rate . . . 15 MHz (Max) Gray Scale Clock Frequency 8 MHz (Max) Operating Free-Air Temperature Range –20_C to 85_C 100-Pin HTQFP Package (PD=4.7 W, TA = 25°C) description The TLC5904 is a constant current driver incorporating shift register, data latch, and constant current circuitry with current value adjustable and a 256 gray scale display using pulse width control. The output current can be selected as maximum 80 mA with 16 bits or 120 mA with 8 bits, and the current value of constant current output can be set by one external resistor. After this device is mounted on a PCB, the brightness deviation between LED modules (ICs) can be adjusted by external data input, and the brightness control for the panel can be accomplished by the brightness adjustment circuitry. Also, the device incorporates the output voltage monitor (OVM) used for LED open detection (LOD) by monitoring the constant current output. Moreover, the device incorporates watchdog time (WDT) circuitry, which turns the constant current output off when a scan signal is stopped at the dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns the constant current output off when the junction temperature exceeds the limit. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 OUT12 NC NC GNDLED NC NC OUT13 OUT14 NC NC GNDLED NC NC OUT15 IREF VCCLED WDCAP GNDANA NC VCCANA MCENA DOUT7 DOUT6 DOUT5 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC OUT4 NC GNDLED NC OUT5 OUT6 NC GNDLED NC OUT7 OUT8 NC GNDLED NC OUT9 OUT10 NC GNDLED NC OUT11 NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 OUT3 NC NC NC GNDLED NC OUT2 OUT1 NC NC GNDLED NC NC OUT0 NC BCENA GNDLOG MODE NC VCCLOG TSENA DIN7 DIN6 DIN5 DIN4 PZP PACKAGE (TOP VIEW) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST2 DOMODE DIN3 DIN2 DIN1 DIN0 GSCLK BLANK RSEL1 RSEL0 DCLK XENABLE XOE WDTRG XLATCH XDOWN1 XDOWN2 TEST1 BOUT GSOUT DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 functional block diagram Shift Register and Data Latch OVM Shift Register Data Latch MCENA BCENA RSEL0 8 RSEL1 8 DIN<0:7> XENABLE DCLK Controller DCLK DOUT<0:7> Brightness Control Shift Register Data Latch DOMODE Gray Scale Control Shift Register Data Latch XOE XLATCH MODE GSCLK BLANK 8 bits Gray Scale Counter DELEY GSOUT DELEY BOUT 16 x 8 bits Comparator TSENA XDOWN1 TSD WDTRG WDCAP IREF XDOWN2 WDT Current Reference Circuit 16 bits Constant Current Driver OUT0 16 bits OVM Comp LATCH OUT15 NOTE: All the input terminals are with Schmitt-triggered inverter except IREF and WDCAP. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 functional block diagram for shift register and data latch MCENA DIN<0:7> 16 bit OVM Comparator XDOWN1, 2 Output Driver OVM Data Latch (1 x 8 bit) 8 BCENA OVM Shift Register (1 x 8 bit) 8 Constant Current Driver Control Gray Scale Clock Counter Brightness Control Data Latch (1 x 8 bit) Brightness Control Shift Register 8 (1 x 8 bit) XLATCH Gray Scale Control Data Latch (16 x 8 bit) XENABLE DCLK MODE 16 x 8 bit Data Comparator DCLK Controller Gray Scale Control Shift Register (16 x 8 bit / 8 x 8 bit) 8 8 Note: Enclosed in () is dependent on MODE pin selection. 1 bit S/R RSEL<0:1> DOMODE 8 8 XOE 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DOUT<0:7> TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 equivalent input and output schematic diagrams Input VCCLOG INPUT GNDLOG DOUT0–7, GSOUT, BOUT VCCLOG OUTPUT GNDLOG XDOWN1, XDOWN2 XDOWN1, XDOWN2 GNDLOG OUTn OUTn GNDLED POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 Terminal Functions ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME BCENA 85 I/O DESCRIPTION I Brightness control enable. When BCENA is low, the brightness control latch is set to the default value. The output current value in this status is 100% of the setting value by an external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to brightness control latch is enabled. BLANK 68 I Blank(light off). When BLANK is high, all the output of the constant current driver is turned off. The constant current output, which the gray scale data is not zero, is turned on (LED on) synchronizing to the falling edge of GSCLK after the next rising edge of GSCLK when BLANK goes from high to low. BOUT 57 O Blank signal delay. BOUT is the output with addition of delay time to BLANK. 65 I Clock input for data transfer. The input data is from DIN. All data on the shift register is selected by RSEL0 and RSEL1, and output data at DOUT is shifted by 1 bit synchronizing to DCLK. The data except for DOUT is synchronized to the rising edge, and the edge for data from DOUT is determined by the level of DOMODE. 70,71,72,73, 76,77,78,79 I Input for 8 bit parallel data. These terminals are inputs to the shift register for gray scale data, brightness control, and OVM. The register selected is determined by RSEL0, 1. 74 I Timing select for data output. When DOMODE is low, DOUT0–7 is changed synchronizing to the rising edge of DCLK. When DOMODE is high, DOUT0–7 is changed synchronizing to the falling edge of DCLK. 55,54,53,52, 51,49,48,47 O Output for 8 bit parallel data with 3-state. These terminals are outputs to the shift register for gray scale data, brightness control, and OVM. The register selected is determined by RSEL0, 1. DCLK DIN0 – DIN7 DOMODE DOUT0 – DOUT7 GNDANA 43 Analog ground (internally connected to GNDLOG and GNDLED) GNDLOG 84 Logic ground (internally connected to GNDANA and GNDLED) GNDLED 5,10,15,20, 29,36,90,96 LED driver ground (internally connected to GNDANA and GNDLOG) GSCLK 69 I Clock input for gray scale. The gray scale display is accomplished by lighting LEDs until the number of GSCLK counted is equal to data latched. GSOUT 56 O Clock delay for gray scale. GSOUT is the output with the addition of delay time to GSCLK. IREF 40 I/O Constant current value setting. LED current is set to the desired value by connecting an external resistor between IREF and GND. The 37 times current compares current across the external resistor sink on the output terminal. MCENA 46 I OVM enable. When MCENA is low, the OVM latch is set to the default value. The comparison voltage in this status is 0.3V. When MCENA is high, writing to the OVM latch is enabled. MODE 83 I 8/16 bits select. When MODE is high, 16 bits output is selected. When MODE is low, 8 bits output is selected. NC OUT0 – OUT15 RSEL0 RSEL1 6 NO. 1,2,4,6,9,11,14,16, 19,21,23,24,25,27, 28,30,31,34,35,37, 38,44,50,82,86,88, 89,91,92,95,97,98, 99 87,93,94,100, 3,7,8,12,13, 17,18,22,26, 32,33,39 66 67 No internal connection O Constant current output I Shift register data latch switching. When RSEL1 is low, gray scale data shift register latch is selected at RSEL0 low, and the brightness control register latch is selected at RSEL0 high. When RSEL1 is high, the OVM register latch is selected at RSEL0 low, and no register latch is selected at RSEL0 high. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 Terminal Functions (Continued) ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME NO. I/O DESCRIPTION TSENA 80 I TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled. TEST1 TEST2 58 75 I TEST. Factory test terminal. TEST1 and TEST2 should be connected to GND for normal operation. THERMAL PAD package bottom Heat sink pad. This pad is connected to the lowest potential IC or thermal layer. VCCANA 45 Analog power supply voltage VCCLOG 81 Logic power supply voltage VCCLED 41 LED driver power supply voltage WDTRG 62 I WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan signal can be monitored by turning the constant current output off to protect the LED from damage if the scan signal stops during the constant period designed. WDCAP 42 I WDT (watchdog timer) detection time adjustment. WDT detection time is adjusted by connecting a capacitor between WDCAP and GND. When WDCAP is directly connected to GND, WDT function is disabled. In this case, WDTRG should be tied to a high or a low level. XDOWN1 60 O Shutdown. XDOWN1 is configured as open collector. It goes low when constant current output is shut down by WDT or TSD function. XDOWN2 59 O OVM comparator output. XDOWN2 is configured as an open collector. It monitors terminal voltage when constant current output is turned on. XDOWN2 goes low when this voltage is lower than the level selected by OVM latch. When BLANK is set high, the previous level is held. XENABLE 64 I DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the rising edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred. XLATCH 61 I Latch. When XLATCH is high, data on the shift register goes through latch. When XLATCH is low, data is latched. Accordingly, if data on the shift register is changed during XLATCH high, this new value is latched (level latch). XOE 63 I Data output enable. When XOE is low, DOUT0–7 terminals are drived. When XOE is high, DOUT0–7 terminals go to a high-impedance state. absolute maximum ratings (see Note 1)† Logic supply voltage, VCC(LOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage for constant current circuit, VCC(LED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Analog supply voltage, VCCANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output current (dc), IO(LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 mA Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V Output voltage range, VO(DOUTn), VO(BOUT) and VO(GSOUT) . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V Output voltage range, VO(OUTn) and VO(DOWNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C Continuous total power dissipation at (or below) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W Power dissipation rating at (or above) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.2m W/°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GNDLOG terminal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ dc characteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Logic supply voltage, VCCLOG 4.5 5 5.5 V Supply voltage for constant current circuit, VCCLED 4.5 5 5.5 V Analog power supply, VCCANA 4.5 5 5.5 V Voltage between VCC, VDIFF1 VDIFF1 = VCCLOG – VCCANA VCCLOG – VCCLED, VCCANA – VCCLED – 0.3 0 0.3 V Voltage between GND, VDIFF2 VDIFF2 = GNDLOG – GNDANA GNDLOG – GNDLED, GNDANA – GNDLED – 0.3 0 0.3 V Voltage applied to constant current output, VOUTn OUT0 to OUT15 off 17 V 0.8 VCCLOG VCCLOG V GNDLOG 0.2 VCCLOG V High-level input voltage, VIH Low-level input voltage, VIL High-level output current, IOH Low-level output current,, IOL Constant output current, IO(LC) VCCLOG = 4.5V, BOUT, GSOUT DOUT0 to DOUT7, VCCLOG = 4.5V, BOUT, GSOUT DOUT0 to DOUT7, VCCLOG = 4.5V, XDOWN1, XDOWN2 OUT0 to OUT15 Operating free-air temperature range, TA –1 mA 1 5 mA 5 80 mA – 20 85 °C ac characteristics, VCCLOG = VCCANA = VCCLED = 4.5 V to 5.5 V, TA = – 20 to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN At cascade operation (DOMODE = L) 10 DCLK clock frequency twh/twl fGSCLK DCLK pulse duration (high or low level) twh/twl fWDT GSCLK pulse duration (high or low level) twh/twl twh WDTRG pulse duration (high or low level) 40 XLATCH pulse duration (high) 50 tr/tf Rise/fall time tsu th 8 20 Frequency division ratio 1/1 Hold time 10 BLANK – GSCLK 20 XENABLE – DCLK 15 XLATCH – DCLK 15 XLATCH – GSCLK 15 RSEL – DCLK↑ 10 RSEL – XLATCH 20 DINn – DCLK 15 XENABLE – DCLK 20 XLATCH – DCLK 30 RSEL – DCLK↓ 20 RSEL – XLATCH 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MHz ns MHz 8 MHz ns ns ns 100 DINn – DCLK UNIT 8 40 WDTRG clock frequency Setup time MAX 15 fDCLK GSCLK clock frequency TYP At single operation ns ns ns TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 electrical characteristics, MIN/MAX: VCCLOG= VCCANA = VCCLED = 4.5 V to 5.5 V, TA = – 20 to 85°C TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER VOH High-level output voltage VOL g Low-level output voltage II Input current ILOG Supply current (logic) IANA TEST CONDITIONS DOUTn, GSOUT, BOUT, IOH = – 1.0mA Supply current (analog) MIN TYP Supply current (constant current driver) UNIT V DOUTn, GSOUT, BOUT, IOL = 1.0mA, 0.5 XDOWN1, XDOWN2, IOL = 5 mA 0.5 VIN = VCCLOG or GNDLOG Input signal is static,T SENA = H, WDCAP = OPEN ±1 µA 1 mA 18 30 mA Data transfer,D GSCLK = 8 MHz CLK = 15 MHz, LED turnon, RIREF = 590 Ω 3 5 LED turnoff RIREF = 590 Ω 3 5 LED turnoff, RIREF = 1180 Ω 15 20 RIREF =590 Ω VOUT = 1 V. RIREF = 1180 Ω All output bits turn on 30 40 25 35 50 70 LED turnoff, ILED MAX VCCLOG – 0.5 VOUT = 1, RIREF = 590 Ω All output bits turn on V mA mA IOLC1 Constant output current (includes error between bits) VOUT = 1 V, RIREF = 1180 Ω 35 40 45 mA IOLC2 Constant output current (includes error between bits) VOUT = 1 V, RIREF = 590 Ω 70 80 90 mA 0.1 µA XDOWN1,2 (VXDOWNn = 15 V) 1 µA DOUTn, (VOUTn = VCCLOG or GND) 1 µA OUT0 to OUT15 (VOUTn = 15 V) IOLK Constant out output ut leakage current ∆IOLC Constant output current error between bit VCCLOG=VCCANA=VCCLED=5 V, VOUT = 1 V, RIREF = 590 Ω All output bits turn on I∆OLC1 Changes in constant output current depend on supply voltage VOUT = 1 V, VIREF = 1.24 V, I∆OLC2 ±1% ±4% RIREF = 1180 Ω, 1 bit output turn on ±1 ±4 %/V Changes in constant output current depend on output voltage VOUT = 1 V to 3 V, RIREF = 1180 Ω, VIREF = 1.24 V, 1 bit output turn on ±1 ±2 %/V Ttsd Twdt TSD detection temperature Junction temperature 150 160 170 °C WDT detection temperature No external capacitor 5 10 15 ms VIREF Voltage reference BCENA = L, POST OFFICE BOX 655303 RIREF = 590 Ω • DALLAS, TEXAS 75265 1.24 V 9 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 switching characteristics, CL = 15pF, MIN/MAX: VCCLOG= VCCANA = VCCLED = 4.5 V to 5.5, TA = –20 to 85°C TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS MIN DOUTn tr Rise time GSOUT, BOUT OUTn (see Figure 1) Fall time GSOUT, BOUT OUTn (see Figure 1) 30 8 20 10 25 35 60 BLANK↑ – OUT0 350 500 40 70 20 350 500 GSCLK – GSOUT 20 40 70 DCLK – DOUTn 15 30 50 XOE↓ – DOUTn (see Note 2) 10 20 35 XOE↑ – DOUTn (see Note 2) 10 15 GSCLK – XDOWN2 (∆0.1 V) NOTE 2: Until DOUT will be turned on (drive) or turned off (Hi-Z). 10 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns 200 GSCLK↓ – OUT0 Propagation delay time 30 OUTn+1 – OUTn BLANK – BOUT td MAX 12 250 DOUTn tf TYP 25 5000 ns TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC 51 Ω VCC IREF OUTn GND 590 Ω 15 pF Figure 1. Rise Time and Fall Time Test Circuit for OUTn VIH or VOH 100% VIH 90% 50% 10% VIL tr VIL or VOL 0% tf td 100% VIH 50% 100% VIH or VOH 50% 0% VIL twh 0% VIL or VOL twl Figure 2. Timing Requirements POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION constant current output selection by user (80 mA × 16 bits or 120 mA × 8 bits) When the MODE terminal is set to high, output is selected as 80 mA × 16 bits. When the MODE terminal is set to low, output is selected as 120 mA × 8 bits. By this setting, the shift register latch for gray scale data is changed to the configuration corresponding to the bit selected. Note that two constant output terminals should be tied to an LED such as OUT0-to-OUT1 and OUT2-to-OUT3 because they operate in a pair when the 8 bits output mode is selected. Also, in this case, the current value of the constant current output is the same as the 16 bits output mode. Therefore, when an output current of 120 mA is desired, the resister connected to the IREF terminal should be selected to the same value as the output current of 60 mA. ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Table 1. Operation Mode Selection MODE OUTPUT H 80 mA × 16 bits L 120 mA × 8 bits On the constant current output terminals (OUT0–15), approximately 37 times the current which flows through external resistor, RIREF (connected between IREF and GND), can flow. The external resistor value is calculated using the following equation: RIREF (Ω) ≅ 37 × 1.24 (V)/IO(LC)(A) where BCENA is low. Note that more current flows if IREF is connect to GND directly. constant output current operation The constant current output turns on the sink constant current if all the gray scale data in the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 8-bit gray scale counter. Then, the output counted corresponding to gray scale data is turned off (stop to sink constant current). If the shift register for gray scale is updated during XLATCH high, data on the gray scale data latch is also updated affecting the constant current output number of the gray scale. Accordingly, during the on-state of constant current output, the XLATCH should be kept to a low level and the gray scale data latch should be held. If there are constant current output terminals unconnected (includes LED disconnection), the LED should be turned on after writing zero to the gray scale data latch corresponding to output unconnected. Unless this action is taken, the supply current on the constant current driver will increase resulting in the influence of the current value for the constant current output light on. shift register latch The device provides three kinds of shift register latchs including the gray scale data, brightness control, and OVM. To write data into a shift register, DCLK and DIN are utilized. The selection of a shift register will be done by RSEL0 and RSEL1 as shown in below table. Note that RSEL0 and RSEL1 should be changed when both DCLK and XLATCH are low. ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Table 2. Shift Register Latch Selection 12 RSEL0 RSEL1 L L Shift register latch for gray scale data SHIFT REGISTER LATCH SELECTED L H Shift register latch for brightness control H L Shift register latch for OVM H H N/A (DOUTn is tied to low level) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION shift register latch for gray scale data The shift register latch for the gray scale data is set as an 8 × 1 byte configuration at the 8 bit mode, and as a 16 × 1 byte configuration at the 16 bit mode. The gray scale data, configured as 8 bits, represents the time when constant current output is being turned on, and the data range is 0 to 255 (00h to FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on(light off). On the other hand, when the gray scale data is 255, the time is longest, and it turns on during the time of the 255 clocks from GSCLK. The configuration of the shift register and latch for gray scale data is shown below. Latch for Gray Scale Data XLATCH OUT15 Data OUT14 Data OUT1 Data OUT0 Data (8 bits) (8 bits) (8 bits) (8 bits) 2nd byte DIN7 MSB DIN0 LSB 1st byte DIN7 MSB DIN0 LSB Shift Register for Gray Scale Data DOUT0 to 7 16th byte DIN7 MSB DIN0 LSB 15th byte DIN7 MSB DIN0 LSB DCLK DIN0 to 7 16 Bit Mode (MODE=H, RSEL0 and RSEL1=L) Latch for Gray Scale Data XLATCH OUT15, 14 Data OUT13, 12 Data OUT3, 2 Data OUT1, 0 Data (8 bits) (8 bits) (8 bits) (8 bits) 2nd byte DIN7 MSB DIN0 LSB 1st byte DIN7 MSB DIN0 LSB Shift Register for Gray Scale Data DOUT0 to 7 8th byte DIN7 MSB DIN0 LSB 7th byte DIN7 MSB DIN0 LSB DCLK DIN0 to 7 8 Bit Mode (MODE=L, RSEL0 and RSEL1=L) Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION shift register latch for brightness control and OVM The shift register latch for both brightness control and OVM (Output Voltage Monitor) is configured with a 1 x 1 byte. In the shift register latch for brightness control, the division ratio of GSCLK can be set and the output current value on the constant current output can be adjusted. In the shift register latch for OVM, the comparison voltage at OVM comparator on the constant current output terminals (OUT0 to OUT15) can be set and the output signal for both XDOWN1 and XDOWN2 can be forced to low level. When power up, the latch data is indeterminate and the shift register is not initialized. Data should be written to the shift register latch prior to turning the constant current output on (BLANK=L) when these functions are used. Also, it is inhibited to rewrite the latch value for brightness control when the constant current output is turned on. When these functions are not used, the latch value can be set to the default value setting BCENA or MCENA to low level (tied to GND). The configuration of the shift register and the latch for brightness control and monitor control is shown in below. Latch for Brightness Control GSCLK Division Ratio Data Set XLATCH 0 0 MSB Current Data Adjusted On Constant Current Output 0 1 LSB MSB 1 1 1 1 (Note A) LSB Shift Register for Brightness Control DOUT0 to 7 DIN7 DATA DIN6 DATA DIN5 DATA DIN4 DATA DIN3 DATA DIN2 DATA DIN1 DATA DIN0 DATA DCLK DIN0 to 7 Latch for OVM Monitor Control Data XLATCH 0 N/A 0 0 MSB 1 (Note B) LSB Shift Register for OVM DOUT0 to 7 DIN7 DATA DIN6 DATA DIN5 DATA DIN4 DATA DIN3 DATA DIN2 DATA DIN1 DATA DIN0 DATA DCLK DIN0 to 7 Note A: Indicates default value at the BCENA terminal = 0 if the brightness control latch = 1 Note B: Indicates default value at the MCENA terminal = 0 if the OVM latch =1 Figure 4. Relationship Between Shift Register and Latch for Brightness Control and OVM write data to shift register latch The shift register latch written to is selected using the RSEL0 and RSEL1 terminals. The data is applied to the DIN data input terminal and is clocked into the shift register synchronizing to the rising edge of DCLK after XENABLE is pulled low. The shift register for the gray scale data is 8 bits length at 8 bit mode resulting in eight times DCLK, and 16 bit length at 16 bit mode resulting in sixteen times DCLK, and as for the brigtness control and monitor control resulting one times DCLK input. At the number of DCLK input for each case, data can be written into the shift register. In this condition, when XLATCH is pulled high, data in the shift register is clocked into the latch (data through), and when XLATCH is pulled low, the data is held (latch). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION brightness control function By writting data into the brightness control latch, the current on all constant current outputs can be adjusted to control the variation of brightness between ICs and the division ratio for the gray scale clock can be set to control the variation of brigtness for the total panel system. output current adjustment on all constant current outputs – brightness adjustment between ICs By using the lower 5 bits of the brightness control latch, the output current can be adjusted to 32 steps. 1 step is 1.6% of the current ratio between 100% and 51.6% when the set output current is 100% by an external resistor. By using this function, the brightness control between modules (ICs) can be adjusted sending desired data externally even if ICs are mounted on print-circuit board. When BCENA is pulled low, output current is set to 100%. ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Table 3. Relative Current Ratio For Total Constant Current Output CODE CURRENT RATIO (%) 20 (mA) 80 (mA) MSB 00000 LSB 51.6 10.3 41.3 VIREF (TYP) 0.63 . . . . . . . . . . . . . . . . . . . . 11110 11111† 98.4 19.7 78.7 1.22 100 20.0 80.0 1.24 † BCENA is low. frequency division ratio setting for gray scale clock – panel brightness adjustment By using the upper 3 bits of the brightness control latch, the gray scale clock can be divided into a frequency division ratio of 1/1 to 1/8. If the gray scale clock is set to 8 times the speed (256x8=2048) of frequency during horizontal scanning time, the brightness can be adjusted to 8 steps selecting the frequency division ratio. By using this function, the total panel brightness can be adjusted at once, and it applies to the brightness of day or night circumstances. When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can be adjusted (see Table 4). ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Table 4. Relative Brightness Ratio For Total Constant Current Output CODE FREQUENCY DIVISION RATIO RELATIVE BRIGHTNESS RATIO (%) MSB 000 LSB† 1/1 12.5 . . . . . . . . . . . . 110 1/7 87.5 111 1/8 100 † BCENA is low. OVM (output voltage monitor) function By writing data into the OVM latch, the comparison voltage for the voltage comparator of OUT0 to OUT15 can be set, and the output signal for XDOWN1 and XDOWN2 can be checked. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION OVM comparator The OVM comparator compares the voltage on the constant current output terminal during turnon with comparison voltage set by the OVM latch. When the voltage on the constant current output terminal is lower, XDOWN2 goes low. As shown in Figure 5, the comparator is provided in every output portion, and the comparison result corresponding to the output to be turned on appears in the XDOWN2 terminal. Since the XDOWN2 terminal is an open-collector output, outputs of multiple ICs are brought together. The output terminal for comparison result is only XDOWN2. The voltage on all the constant current output can be checked to monitor XDOWN2 turning output on in turn. The voltage on the constant current output, when turned on, can be also measured changing the comparison voltage set by the OVM latch. Using this function, sensing (LOD function) an LED disconnection (output voltage is below 0.3 V) and short circuit (output voltage is extremely high) can be detected and specifies which LED encountered this failure. Also, by monitoring the output voltage and controlling the voltage across anode of the LED to minimize the voltage on the constant current output (approximately 0.7 V at IO = 80 mA), the temperature rising of the chip can be minimized. Furthermore, by setting BLANK to low during LED on, the comparison result immediately before can be held. Thus, synchronizing timing to check XDOWN2 from the system to the LED lighting timing is not required. Note that the gray scale data being turned on should be a minimum of 5 µs since XDOWN2 output is required approximately 5 µs after the constant current output is turned on. The comparison result is also required approximately 5 µs after the changed latch data. OUT0 – + Internal OUT0 Turn ON Signal OUT1 – + Internal OUT1 Turn ON Signal XDOWN2 D Q OUT14 LATCH – + Internal OUT014 Turn ON Signal OUT15 Internal OUT015 Turn ON Signal – + BLANK Comparison Voltage When BLANK is high, hold the data When BLANK is low, data is out. Figure 5. OVM functional diagram 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION output signal check for XDOWN1, XDOWN2 XDOWN1 or XDOWN2 can be forced to low level by setting the appropriate latch value for OVM. This allows the investigation of the correct connection of XDOWN1 or XDOWN2 to the external system. OVM comparator setting Setting the OVM latch is shown in Table 5. Note that the comparison voltage is set to the default value of 0.3 V when MCENA is tied to the low level. ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Table 5. OVM Setting MONITOR CONTROL DATA COMPARISON VOLTAGE XDOWN1 0000 0001† NO COMPARISON DEPEND ON TSD/WDT HI–Z 0.3 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0010 0.4 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0011 0.5 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0100 0.6 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0101 0.7 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 0110 0.8 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR MSB LSB XDOWN2 0111 0.9 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1000 1.0 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1001 1.1 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1010 1.2 V DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1011 1/3 × VCCANA DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1100 1/2 × VCCANA DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1101 2/3 × VCCANA DEPEND ON TSD/WDT DEPEND ON OVM COMPARATOR 1110 0.3 V L DEPEND ON OVM COMPARATOR 1111 0.3 V DEPEND ON TSD/WDT L † MCENA is low. DOUT output timing selection The timing for the DOUT output change can be switched by selecting the DOMODE level. When DOMODE is low, the DOUT is changed synchronizing to the rising edge of DCLK. When DOMODE is high, the DOUT is changed synchronizing to the falling edge of DCLK. When the shift operation with DOMODE is high, data can be protected from a shift error even if the DCLK signal is buffered externally in serial. In this case, when ICs are connected in cascade, the maximum data transfer speed at will be slower than the case of DOMODE low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION protection This device incorporates WDT and TSD functions. If WDT or TSD functions, constant current output is stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be detected immediately. Since the XDOWN1 output is configured as an open collector, outputs of multiple ICs are brought together. WDT (watchdog timer) The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapsed after the signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (signal to control line displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned off. This prevents the LED from burning and damage caused by continuous LED turnon at the dynamic scanning operation. The detection time can be set using an external capacitor, Cext. The typical value is approximately 10 ms without a capacitor, 160 ms with a 1000 pF capacitor and 1500 ms with a 0.01 µF capacitor. During static operation, the WDT function is disabled connecting WDCAP to GND (high or low level should be applied to WDTRG). Note that normal operations will resume changing the WDTRG level when WDT functions. t – Time – ms WDT operational time: T (ms) ≅ 10 + 0.15 × Cext (pF) 1500 TLC5904 Scan Signal WDTRG WDCAP 160 Cext 10 0 0.001 0.01 Cext – External Capacitor – µF Figure 6. WDT Operational Time and Usage Example TSD (thermal shutdown) When the junction temperature exceeds the limit, TSD starts to function and turns the constant current output off, and XDOWN1 goes low. When TSD is used, TSENA should be pulled high. When TSD is not used, TSENA should be pulled low. To recover from the constant current output off-state to normal operations, the power supply should be turned off or TSENA should be pulled low once. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION noise reduction concurrent switching noise reduction The concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time. To prevent this noise, the device has delay output terminals such as XGSOUT and BOUT for GSCLK (gray scale clock) and BLANK (blanking signal) respectively. By connecting these outputs to the GSCLK and BLANK terminals of next stage IC, it allows differences in the switching time between ICs. When GSCLK is output to GSOUT through the device, duty will be changed between input and output, and the number of stages to be connected will be limited depending on frequency. output slope When the output current is 80 mA, the time to change constant current output to turnon and turnoff is approximately 150 ns and 250 ns respectively. This allows reduced concurrent switching noise when multiple outputs turn on or off at the same time. delay between constant current output The constant current output has a delay time of approximately 30 ns between outputs. This means approximately 450 ns delay time exists between OUT0 and OUT15. This time differences by delay allows reduced concurrent switching noise as well as the output slope previously described. This delay time has the same value at the 8 bits or 16 bits operation mode. power supply The followings should be taken into consideration: 1) VCCLOG, VCCANA, and VCCLED should be supplied by a single power supply to minimize voltage differences between these terminals. 2) The bypass capacitor should be located between the power supply and GND to eliminate the variation of power supply voltage. GND Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally connected to reduce noise influence. thermal pad The thermal pad should be connected to GND to eliminate the noise influence when it is connected to the bottom side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with better thermal conductivity. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION 4.7 3.2 2.4 1.48 0 Output Voltage (Constant Current) – V † PD – Total Power Dissipation – W power rating – free-air temperature 0 –20 0 25 85 TA – Free–Air Temperature – °C † VCCLOG=VCCANA=VCCLED=5.0V, IOLC = 80 mA, ICC is typical value. NOTES: A. IC is mounted on PCB. PCB size: 102 x 76 × 1.6 [mm3], four layers with the internal two layer being plane. The thermal pad is soldered to the PCB pattern of 10 × 10 [mm2]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C. B. The thermal impedance will be varied depending on mounting conditions. Since the PZP package established low thermal impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with low a thermal impedance. C. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad. Figure 7. Power Rating 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 PRINCIPLES OF OPERATION constant output current 90 80 70 I OLC – mA 60 50 40 30 20 10 0 0.1 1.0 10.0 RIREF – kΩ NOTE: Conditions: VOUT = 1.0V, VIREF = 1.24V I OLC(mA) ≅ W R IREF (k ) ≅ V IREF(V) R IREF(k ) W 37 47 I OLC(mA) NOTE: Shows the output current at the 16 bit mode. and at the 8 bit mode (MODE=L). Output current is the sum of both outputs. This sum current should be set from 10 mA to 120 mA. The resistor, RIREF, should be located as close to the IREF terminal as possible to avoid the noise influence. Figure 8. Current on Constant Current Output vs External Resistor POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 XOE XENABLE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tsu (XENABLE–DCLK) th (XENABLE–DCLK) 1/fDCLK DCLK tsu (DIN–DCLK) twl (DCLK) twh (DCLK) DIN0 D00_A D01_A D02_A D0E_A D0F_A D00_B D0D_B D0E_B D0F_B D00_C D01_C DIN7 D70_A D71_A D72_A D7E_A D7F_A D70_B D7D_B D7E_B D7F_B D70_C D71_C th (DIN–DCLK) th (XLATCH–DCLK) tsu (XLATCH–DCLK) XLATCH twh (XLATCH) DOUT0 HI–Z D00_A D01_A D0E_A D0F_A D00_B DOUT7 HI–Z D70_A D71_A D7E_A D7F_A D70_B td (XOE↓–DOUT) td (DCLK–DOUT) NOTE: MODE = H Figure 9. Timing Diagram (Shift Register for Gray Scale Data) td (XOE↑–DOUT) Template Release Date: 7–11–94 RSEL1 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 22 RSEL0 MCENA RSEL0 RSEL1 tsu (RSEL–XLATCH) th (RSEL–XLATCH) XOE XENABLE tsu (RSEL–DCLK) tsu (RSEL–DCLK) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCLK DIN0 D0_A D0_B D0_C D0_J D0_K D0_L D0_M D0_N D0_O DIN7 D7_A D7_B D7_C D7_J D7_K D7_L D7_M D7_N D7_O th (XLATCH–DCLK) XLATCH twh (XLATCH) MCL_0 Default Value “1” Default Value “1” D<0>_A (Monitor Control Latch Internal Signal) MCL_1–3 D<1:3>_A Default Value “0” td (XOE↓–DOUT) Default Value “0” td (DCLK–DOUT) td (XOE↑–DOUT) D0_A D0_C D0_E D0_F D0_G D0_H D0_I DOUT7 HI–Z D7_A D7_C D7_E D7_F D7_G D7_H D7_I 23 Figure 10. Timing Diagram (Shift Register for Monitor Control) TLC5904 LED DRIVER HI–Z SLLS391 – NOVEMBER 1999 DOUT0 tsu (RSEL–XLATCH) th (RSEL–XLATCH) RSEL1 XOE XENABLE tsu (RSEL–DCLK) tsu (RSEL–DCLK) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCLK DIN0 D0_A D0_B D0_C D0_J D0_K D0_L D0_M D0_N D0_O DIN7 D7_A D7_B D7_C D7_J D7_K D7_L D7_M D7_N D7_O th (XLATCH–DCLK) XLATCH twh (XLATCH) BCL_0–4 Default Value “1” Default Value “1” D<0:4>_A (Brightness Control Latch Internal Signal) BCL_5–7 D<5:7>_A Default Value “0” td (XOE↓–DOUT) Default Value “0” td (DCLK–DOUT) td (XOE↑–DOUT) DOUT0 HI–Z D0_A D0_C D0_E D0_F D0_G D0_H D0_I DOUT7 HI–Z D7_A D7_C D7_E D7_F D7_G D7_H D7_I Figure 11. Timing Diagram (Shift Register for Brightness Control) Template Release Date: 7–11–94 RSEL0 TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 24 BCENA XLATCH tsu (XLATCH–GSCLK) BLANK 1/fGSCLK tsu (BLANK–GSCLK) td (BLANK–OUT0) GSCLK twl (GSCLK) twh (GSCLK) 1/fWDT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 WDTRG twl (WDTRG) twh (WDTRG) td (GSCLK–OUT0) td (BLANK–OUT0) OFF OUT0 twdt td (GSCLK–OUT0) ON(Note A) OFF td (OUTn+1–OUTn) (Note A) OFF (Note A) td (OUTn+1–OUTn) OFF OUT1 OUT15 ON(Note A) OFF ...... OFF ON(Note A) OFF (Note A) (Note A) OFF OFF (Note A) (Note A) NOTE A: ON or OFF, or ON time is varied dpend on the gray scale data and BLANK. HI–Z XDOWN1 XDOWN2 (Note B) td (GSCLK–GSOUT) GSOUT 25 Figure 12. Timing Diagram (Constant Current Output) TLC5904 LED DRIVER BOUT NOTE B: LED disconnection SLLS391 – NOVEMBER 1999 td (GSCLK–XDOWN2) td (BLANK–BOUT) (Note B) TLC5904 LED DRIVER SLLS391 – NOVEMBER 1999 MECHANICAL DATA PZP (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 50 76 Thermal Pad (see Note D) 26 100 0,13 NOM 1 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,25 0,15 0,05 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4146929/A 04/99 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The demensions of the thermal pad are 5 mm x 5 mm. The pad is centered on the bottom of the package. E. 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