TI LMK03806BISQE

LMK03806
LMK03806 Ultra Low Jitter Clock Generator with 14 Programmable Outputs
Literature Number: SNAS522(
LMK03806
Ultra Low Jitter Clock Generator with 14 Programmable
Outputs
1.0 General Description
3.0 Features
The LMK03806 is a high performance, ultra low-jitter, multirate clock generator capable of synthesizing 8 different frequencies on 14 outputs at frequencies of up to 2.6 GHz. Each
output clock is programmable in LVDS, LVPECL or LVCMOS
format. The LMK03806 integrates a high performance integer-N PLL, low noise VCO, and programmable output dividers to generate multiple reference clocks for SONET,
Ethernet, Fiber Channel, XAUI, Backplane, PCIe, SATA and
Network Processors from a low cost crystal.
■ High performance, ultra low jitter clock generator
■ Low Jitter
2.0 Target Applications
■
■
■
■
Ultra High Speed Serial Interfaces in SONET/SDH
Multi-Gigabit Ethernet & Fiber Channel Line Cards
Base Band Units (BBUs) for RAN applications
GPON OLT/ONU , High Speed Serial Interface such as
PCIe, XAUI, SATA, SAS
■ Clocking ADC and DACs
■ Clocking DSP, Microprocessors and FPGAs
■
■
■
■
■
■
■
■
— < 50 fs jitter (1.875 MHz - 20 MHz) at 312.5 MHz Output
Frequency
— < 150 fs jitter (12 kHz - 20 MHz) at 312.5 MHz Output
Frequency
Generates multiple clocks from a low cost crystal or
external clock.
14 outputs with programmable output format (LVDS,
LVPECL, CMOS)
Up to 8 unique output frequencies.
Industrial Temperature Range: -40 to 85 °C
Tunable VCO frequency from 2.37 - 2.6 GHz
Programmable dividers to generate multiple clocks from a
low cost crystal.
3.15 V to 3.45 V operation
Package: 64-pin LLP (9.0 x 9.0 x 0.8 mm)
30170163
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 Texas Instruments Incorporated
301701
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LMK03806 Ultra Low Jitter Clock Generator with 14 Programmable Outputs
November 22, 2011
LMK03806
4.0 Common Frequency Plans
Standard/Application
Output Frequencies (MHz)
Infiniband
100, 200
SATA
75, 150, 300, 600
SAS
37.5, 75, 120, 150
Fast Ethernet
25
1 GbE
125
10 GbE
156.25, 312.5, 625
XAUI
78.125, 156.25, 312.5
VCO Frequency
Recommended Crystal Value
2400 MHz
2500 MHz
20 MHz
Backplane
227.27...
2G/4G/16G Fiber Channel
106.25, 212.5
10G Fiber Channel
159.375
40/100 GbE
644.53125, 322.265625,
161.1328125
2578.125 MHz
12.5 MHz
SONET
19.44, 38.88, 77.76, 155.52,
311.04, 622.08
2488.32 MHz
19.44 MHz
A/D Clocking
30.72, 61.44, 122.88, 153.6,
245.76, 491.52, 983.04
2457.6 MHz
19.2 MHz or
12.288 MHz
2550 MHz
5.0 Achievable Frequencies
By using the tunable range of the VCO followed by a programmable divider, the LMK03806 can achieve any of the frequencies in
the table below
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Output Divider Value
Achieved Frequency (MHz)
1
2370 - 2600
2
1185 - 1300
3
790 - 866.7
4
592.5 - 650
5
474 - 520
6
395.7 - 433
7
338.6 - 371.4
8
296.25 - 325
9
263.3 - 288.9
10
237 - 260
11 to 1045
Any frequency in the range of 2.27 - 236.36
2
LMK03806
6.0 Functional Block Diagrams
6.1 10 Gigabit Ethernet Reference Clocks
30170109
FIGURE 1.
6.2 Fiber Channel Reference Clocks
30170110
FIGURE 2.
3
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LMK03806
6.3 SONET/SDH Reference Clocks
30170111
FIGURE 3.
6.4 Detailed LMK03806 Block Diagram
Figure 4 illustrates the complete LMK03806 block diagram.
30170101
FIGURE 4. Detailed LMK03806 Block Diagram
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4
LMK03806
7.0 Connection Diagram
64-Pin LLP Package
30170102
5
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LMK03806
8.0 Pin Descriptions
Pin Number
Name(s)
I/O
Type
1, 2
CLKout0,
CLKout0*
O
Programmable
Clock output 0 (clock group 0).
3, 4
CLKout1*,
CLKout1
O
Programmable
Clock output 1 (clock group 0).
5, 7, 8, 9, 25, 26,
28,29, 34
NC
-
Do Not Connect
These pins must be left floating. Do NOT ground.
6
SYNC
I
CMOS
Clock synchronization input.
10
Vcc1
-
PWR
Power supply for VCO LDO.
11
LDObyp1
-
ANLG
LDO Bypass, bypassed to ground with 10 µF
capacitor.
12
LDObyp2
-
ANLG
LDO Bypass, bypassed to ground with a 0.1 µF
capacitor.
13, 14
CLKout2,
CLKout2*
O
Programmable
Clock output 2 (clock group 1).
15, 16
CLKout3*,
CLKout3
O
Programmable
Clock output 3 (clock group 1).
17
Vcc2
-
PWR
Power supply for clock group 1: CLKout2 and
CLKout3.
18
Vcc3
-
PWR
Power supply for clock group 2: CLKout4 and
CLKout5.
19, 20
CLKout4,
CLKout4*
O
Programmable
Clock output 4 (clock group 2).
21, 22
CLKout5*,
CLKout5
O
Programmable
Clock output 5 (clock group 2).
23
GND
-
PWR
Ground
Power supply for digital.
24
Vcc4
-
PWR
27
Readback
O
CMOS
30
Vcc5
-
PWR
31, 32
OSCout1,
OSCout1*
O
LVPECL
33
Ftest/LD
O
Programmable
35
Vcc6
-
PWR
36, 37
OSCin, OSCin*
I
ANLG
38
Vcc7
-
PWR
39, 40
OSCout0,
OSCout0*
O
Programmable
Description
Pin that can be used to readback register information.
Power supply for clock inputs.
Buffered output 1 of OSCin port.
Multiplexed Lock Detect and Test output pin.
Power supply. No bypassing required on this pin.
Reference input to PLL. Reference input may be:
— A Crystal for use with the internal crystal oscillator
circuit.
— A XO, TCXO, or other external clock. Must be AC
Coupled.
Power supply for OSCin port.
Buffered output 0 of OSCin port.
41
Vcc8
-
PWR
Power supply for PLL charge pump.
42
CPout
O
ANLG
Charge pump output.
43
Vcc9
-
PWR
Power supply for PLL.
44
LEuWire
I
CMOS
MICROWIRE Latch Enable Input.
45
CLKuWire
I
CMOS
MICROWIRE Clock Input.
46
DATAuWire
I
CMOS
MICROWIRE Data Input.
47
Vcc10
-
PWR
48, 49
CLKout6,
CLKout6*
O
Programmable
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6
Power supply for clock group 3: CLKout6 and
CLKout7.
Clock output 6 (clock group 3).
Name(s)
I/O
Type
50, 51
CLKout7*,
CLKout7
O
Programmable
52
Vcc11
-
PWR
53, 54
CLKout8,
CLKout8*
O
Programmable
Clock output 8 (clock group 4).
55, 56
CLKout9*,
CLKout9
O
Programmable
Clock output 9 (clock group 4).
57
Vcc12
-
PWR
58, 59
CLKout10,
CLKout10*
O
Programmable
Clock output 10 (clock group 5).
60, 61
CLKout11*,
CLKout11
O
Programmable
Clock output 11 (clock group 5).
62, 63
GPout0, GPout1
O
CMOS
64
Vcc13
-
PWR
Power supply for clock group 0: CLKout0 and
CLKout1.
DAP
DAP
-
GND
DIE ATTACH PAD, connect to GND.
7
LMK03806
Pin Number
Description
Clock output 7 (clock group 3).
Power supply for clock group 4: CLKout8 and
CLKout9.
Power supply for clock group 5: CLKout10 and
CLKout11.
These pins can be programmed for general purpose
output.
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LMK03806
9.0 Absolute Maximum Ratings (Note 1, Note 2, Note 3)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
Parameter
Ratings
Units
Supply Voltage (Note 4)
Symbol
VCC
-0.3 to 3.6
V
Input Voltage
VIN
-0.3 to (VCC + 0.3)
V
Storage Temperature Range
TSTG
-65 to 150
°C
Lead Temperature (solder 4 seconds)
TL
+260
°C
Junction Temperature
TJ
150
°C
Differential Input Current (OSCin/OSCin*)
IIN
±5
mA
Moisture Sensitivity Level
MSL
3
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only to the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 750 V
Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.
Note 3: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.
Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure
to absolute maximum ratings for extended periods can adversely affect device reliability.
Note 4: Never to exceed 3.6 V.
10.0 Recommended Operating Conditions
Parameter
Ambient
Temperature
Junction
Temperature
Supply Voltage
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Symbol
Condition
Min
Typical
Max
Unit
TA
VCC = 3.3 V
-40
25
85
°C
TJ
VCC = 3.3 V
125
°C
3.45
V
VCC
3.15
8
3.3
(3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Junction Temperature TJ ≤ 125 °C. Typical values represent most likely parametric
norms at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions at the time of product characterization and are not
guaranteed.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Current Consumption
ICC_PD
Power Down Supply Current
No DC path to ground on OSCout1/1*
(Note 5)
1
mA
ICC_CLKS
Supply Current with all clocks enabled
(Note 6)
CLKoutX_Y_DIV = 16,
CLKoutX_TYPE = 1 (LVDS),
PLL locked
445
mA
External Clock (OSCin) Specifications
fOSCin
PLL Reference Input
(Note 8)
SLEWOSCin
PLL Reference Clock minimum slew
rate on OSCin(Note 13)
20% to 80%
0.15
VOSCin
Input Voltage for OSCin or OSCin*
(Note 13)
AC coupled; Single-ended (Unused
pin AC coupled to GND)
0.2
2.4
Vpp
Differential voltage swing
Figure 6
AC coupled
0.2
1.55
|V|
0.4
3.1
Vpp
VOSCin-offset
DC offset voltage between OSCin/
OSCin*
OSCinX* - OSCinX
Each pin AC coupled
fdoubler_max
Doubler input frequency (Note 13)
EN_PLL_REF_2X = 1;
OSCin Duty Cycle 40% to 60%
VIDOSCin
VSSOSCin
1
500
0.5
MHz
V/ns
20
mV
155
MHz
16
20.5
MHz
6
16
MHz
Crystal Oscillator Mode Specifications
RESR ≤ 40 Ω
fXTAL
CL ≤ 20 pF
Crystal Frequency Range
(Note 13)
RESR ≤ 80 Ω
CL ≤ 22 pF
Vectron VXB1 crystal, 20.48 MHz,
PXTAL
Crystal Power Dissipation
CIN
Input Capacitance of the OSCin port
RESR ≤ 40 Ω
120
µW
-40 to +85 °C
6
pF
CL ≤ 20 pF
9
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LMK03806
11.0 Electrical Characteristics
LMK03806
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RMS Jitter Performance
Integration Bandwidth
10 kHz to 1 MHz
XO Mode
(Note 18)
(Note 19)
(Note 20)
Integration Bandwidth
12 kHz to 20 MHz
Integration Bandwidth
637 kHz to 10 MHz
Integration Bandwidth
1.875 MHz to 20 MHz
Integration Bandwidth
10 kHz to 1 MHz
Crystal Mode
Jitter
(Note 14)
(Note 15)
(Note 16)
Integration Bandwidth
12 kHz to 20 MHz
Integration Bandwidth
637 kHz to 10 MHz
Integration Bandwidth
1.875 MHz to 20 MHz
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156.25 MHz, LVDS/LVPECL
81
312.5 MHz, LVDS/LVPECL
85
100 MHz, LVDS
139
100 MHz, LVPECL
117
106.25 MHz, LVDS
145
106.25 MHz, LVPECL
126
156.25 MHz, LVDS
111
156.25 MHz, LVPECL
100
312.5 MHz, LVDS
108
312.5 MHz, LVPECL
95
622.08 MHz, LVDS/LVPECL
141
106.25 MHz, LVDS
78
106.25 MHz, LVPECL
60
156.25 MHz, LVDS
70
156.25 MHz, LVPECL
57
312.5 MHz, LVDS
57
312.5 MHz, LVPECL
43
156.25 MHz, LVDS/LVPECL
190
312.5 MHz, LVDS/LVPECL
200
100 MHz, LVDS
235
100 MHz, LVPECL
210
106.25 MHz, LVDS
280
106.25 MHz, LVPECL
250
156.25 MHz, LVDS
200
156.25 MHz, LVPECL
195
312.5 MHz, LVDS
220
312.5 MHz, LVPECL
190
622.08 MHz, LVDS/LVPECL
255
106.25 MHz, LVDS
90
106.25 MHz, LVPECL
65
156.25 MHz, LVDS
75
156.25 MHz, LVPECL
65
312.5 MHz, LVDS
60
312.5 MHz, LVPECL
45
10
fs
fs
Parameter
Conditions
Min
Typ
Max
Units
Phase Noise Performance
100 MHz (LVDS/LVPECL)
(Note 18)
106.25 MHz (LVDS/LVPECL)
(Note 19)
XO Mode Phase
Noise
156.25 MHz (LVDS/LVPECL)
(Note 18)
312.5 MHz (LVDS/LVPECL)
(Note 18)
622.08 MHz (LVDS/LVPECL)
(Note 20)
10 kHz
-142
100 kHz
-143
1 MHz
-157
10 MHz (LVDS)
-159
20 MHz (LVDS)
-160
10 MHz (LVPECL)
-160
20 MHz (LVPECL)
-161
10 kHz
-141
100 kHz
-140
1 MHz
-156
10 MHz (LVDS)
-159
20 MHz (LVDS)
-160
10 MHz (LVPECL)
-162
20 MHz (LVPECL)
-163
10 kHz
-139
100 kHz
-140
1 MHz
-153
10 MHz (LVDS)
-159
20 MHz (LVDS)
-159
10 MHz (LVPECL)
-160
20 MHz (LVPECL)
-160
10 kHz
-132
100 kHz
-133
1 MHz
-148
10 MHz (LVDS)
-154
20 MHz (LVDS)
-155
10 MHz (LVPECL)
-157
20 MHz (LVPECL)
-158
10 kHz
-123
100 kHz
-121
1 MHz
-143
10 MHz (LVDS)
-154
20 MHz (LVDS)
-154
10 MHz (LVPECL)
-157
20 MHz (LVPECL)
-158
11
dBc/Hz
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LMK03806
Symbol
LMK03806
Symbol
Parameter
100 MHz (LVDS/LVPECL)
(Note 14)
106.25 MHz (LVDS/LVPECL)
(Note 15)
Crystal Mode
Phase Noise
156.25 MHz (LVDS/LVPECL)
(Note 14)
312.5 MHz (LVDS/LVPECL)
(Note 14)
622.08 MHz (LVDS/LVPECL)
(Note 16)
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Conditions
Min
Typ
10 kHz
-129
100 kHz
-137
1 MHz
-156
10 MHz (LVDS)
-158
20 MHz (LVDS)
-159
10 MHz (LVPECL)
-160
20 MHz (LVPECL)
-161
10 kHz
-124
100 kHz
-137
1 MHz
-156
10 MHz (LVDS)
-158
20 MHz (LVDS)
-159
10 MHz (LVPECL)
-160
20 MHz (LVPECL)
-161
10 kHz
-125
100 kHz
-132
1 MHz
-153
10 MHz (LVDS)
-158
20 MHz (LVDS)
-159
10 MHz (LVPECL)
-160
20 MHz (LVPECL)
-160
10 kHz
-119
100 kHz
-126
1 MHz
-147
10 MHz (LVDS)
-153
20 MHz (LVDS)
-154
10 MHz (LVPECL)
-156
20 MHz (LVPECL)
-157
10 kHz
-110
100 kHz
-120
1 MHz
-140
10 MHz (LVDS)
-153
20 MHz (LVDS)
-153
10 MHz (LVPECL)
-154
20 MHz (LVPECL)
-154
12
Max
Units
dBc/Hz
Parameter
fPD
Phase Detector Frequency
Conditions
Min
Typ
Max
Units
155
MHz
PLL Phase Detector and Charge Pump Specifications
ICPoutSOURCE
ICPoutSINK
PLL Charge Pump Source Current
PLL Charge Pump Sink Current
VCPout=VCC/2, PLL_CP_GAIN = 0
100
VCPout=VCC/2, PLL_CP_GAIN = 1
400
VCPout=VCC/2, PLL_CP_GAIN = 2
1600
VCPout=VCC/2, PLL_CP_GAIN = 3
3200
VCPout=VCC/2, PLL_CP_GAIN = 0
-100
VCPout=VCC/2, PLL_CP_GAIN = 1
-400
VCPout=VCC/2, PLL_CP_GAIN = 2
-1600
VCPout=VCC/2, PLL_CP_GAIN = 3
-3200
3
4
%
4
%
ICPout%MIS
Charge Pump Sink/Source Mismatch
VCPout=VCC/2, TA = 25 °C
ICPoutVTUNE
Magnitude of Charge Pump Current
vs. Charge Pump Voltage Variation
0.5 V < VCPout < VCC - 0.5 V
TA = 25 °C
ICPout%TEMP
Charge Pump Current vs.
Temperature Variation
ICPoutTRI
Charge Pump Leakage
0.5 V < VCPout < VCC - 0.5 V
PLL_CP_GAIN = 400 µA
-118
PN10kHz
PLL 1/f Noise at 10 kHz offset
(Note 9). Normalized to
1 GHz Output Frequency
PLL_CP_GAIN = 3200 µA
-121
PN1Hz
Normalized Phase Noise Contribution
(Note 10)
PLL_CP_GAIN = 400 µA
-222.5
PLL_CP_GAIN = 3200 µA
-227
L(f)
PLL Phase Noise
(Assumes a very wide bandwidth,
noiseless crystal, 2500 MHz output
frequency, and 25 MHz phase
detector frequency)
µA
µA
10
10
1 kHz Offset
-93
10 kHz
-103
100 kHz Offset
-116
1 MHz Offset
-116
%
nA
dBc/Hz
dBc/Hz
dBc/Hz
Internal VCO Specifications
fVCO
VCO Tuning Range
KVCO
Fine Tuning Sensitivity
(The range displayed in the typical
column indicates the lower sensitivity
is typical at the lower end of the tuning
range, and the higher tuning
sensitivity is typical at the higher end
of the tuning range).
|ΔTCL|
Allowable Temperature Drift for
Continuous Lock
(Note 11, Note 13)
After programming R30 for lock, no
changes to output configuration are
permitted to guarantee continuous
lock
Phase Noise
(Assumes a very narrow loop
bandwidth)
10 kHz Offset
-87
L(f)
100 kHz Offset
-112
1 MHz Offset
-133
2370
2600
16 to 21
13
MHz
MHz/V
125
°C
dBc/Hz
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LMK03806
Symbol
LMK03806
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Skew
LVDS-to-LVDS, T = 25 °C,
fCLK = 800 MHz, RL= 100 Ω
AC coupled
30
LVPECL-to-LVPECL,
T = 25 °C,
fCLK = 800 MHz, RL= 100 Ω
emitter resistors =
240 Ω to GND
AC coupled
30
Maximum skew between any two
LVCMOS outputs, same CLKout or
different CLKout (Note 12, Note 13)
RL = 50 Ω, CL = 5 pF,
T = 25 °C, FCLK = 100 MHz.
(Note 12)
100
MixedSKEW
LVDS or LVPECL to LVCMOS
Same device, T = 25 °C,
250 MHz
750
fCLKout
Operating Frequency
(Note 13, Note 17)
Maximum CLKoutX to CLKoutY
(Note 12, Note 13)
|TSKEW|
ps
ps
LVDS Clock Outputs (CLKoutX), CLKoutX_TYPE = 1
VOD
VSS
Differential Output Voltage
Figure 7
ΔVOD
Change in Magnitude of VOD for
complementary output states
VOS
Output Offset Voltage
ΔVOS
Change in VOS for complementary
output states
RL = 100 Ω
T = 25 °C, DC measurement
AC coupled to receiver input
R = 100 Ω differential termination
1300
MHz
250
400
450
|mV|
500
800
900
mVpp
50
mV
1.375
V
35
|mV|
-50
1.125
1.25
Output Rise Time
20% to 80%, RL = 100 Ω
Output Fall Time
80% to 20%, RL = 100 Ω
ISA
ISB
Output short circuit current - singleended
Single-ended output shorted to GND,
T = 25 °C
-24
24
mA
ISAB
Output short circuit current differential
Complimentary outputs tied together,
T = 25 °C
-12
12
mA
TR / TF
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14
200
ps
Parameter
fCLKout
Operating Frequency
(Note 13, Note 17)
Conditions
Min
Typ
Max
Units
1300
MHz
LVPECL Clock Outputs (CLKoutX)
20% to 80% Output Rise
TR / TF
80% to 20% Output Fall Time
RL = 100 Ω, emitter resistors = 240 Ω
to GND
CLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)
150
ps
VCC 1.03
V
VCC 1.41
V
700 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 2
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Output Voltage
Figure 7
VSS
T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.4 V
305
380
440
|mV|
610
760
880
mVpp
1200 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 3
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Output Voltage
Figure 7
VSS
T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.7 V
VCC 1.07
V
VCC 1.69
V
545
625
705
|mV|
1090
1250
1410
mVpp
1600 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 4
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Output Voltage
Figure 7
VSS
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.0 V
VCC 1.10
V
VCC 1.97
V
660
870
965
|mV|
1320
1740
1930
mVpp
2000 mVpp LVPECL (2VPECL) Clock Outputs (CLKoutX), CLKoutX_TYPE = 5
VOH
Output High Voltage
VOL
Output Low Voltage
VOD
Output Voltage
Figure 7
VSS
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.3 V
15
VCC 1.13
V
VCC 2.20
V
800
1070
1200
|mV|
1600
2140
2400
mVpp
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LMK03806
Symbol
LMK03806
Symbol
Parameter
Conditions
fCLKout
Operating Frequency
(Note 13)
5 pF Load
VOH
Output High Voltage
1 mA Load
Min
Typ
Max
Units
250
MHz
LVCMOS Clock Outputs (CLKoutX)
VCC 0.1
V
VOL
Output Low Voltage
1 mA Load
IOH
Output High Current (Source)
VCC = 3.3 V, VO = 1.65 V
28
mA
IOL
Output Low Current (Sink)
VCC = 3.3 V, VO = 1.65 V
28
mA
DUTYCLK
Output Duty Cycle
(Note 13)
VCC/2 to VCC/2, FCLK = 100 MHz, T =
25 °C
TR
Output Rise Time
20% to 80%, RL = 50 Ω,
CL = 5 pF
400
ps
TF
Output Fall Time
80% to 20%, RL = 50 Ω,
CL = 5 pF
400
ps
0.1
45
50
55
V
%
Digital Outputs (Ftest/LD, Readback, GPoutX)
VOH
High-Level Output Voltage
IOH = -500 µA
VOL
Low-Level Output Voltage
IOL = 500 µA
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
VCC 0.4
V
0.4
V
VCC
V
0.4
V
VCC
V
Digital Inputs (SYNC)
1.6
Digital Inputs (CLKuWire, DATAuWire, LEuWire)
VIH
High-Level Input Voltage
1.6
VIL
Low-Level Input Voltage
0.4
V
IIH
High-Level Input Current
VIH = VCC
5
25
µA
IIL
Low-Level Input Current
VIL = 0
-5
5
µA
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16
Parameter
Conditions
Min
Typ
Max
Units
TECS
LE to Clock Set Up Time
See MICROWIRE Input Timing
25
ns
MICROWIRE Interface Timing
TDCS
Data to Clock Set Up Time
See MICROWIRE Input Timing
25
ns
TCDH
Clock to Data Hold Time
See MICROWIRE Input Timing
8
ns
TCWH
Clock Pulse Width High
See MICROWIRE Input Timing
25
ns
TCWL
Clock Pulse Width Low
See MICROWIRE Input Timing
25
ns
TCES
Clock to LE Set Up Time
See MICROWIRE Input Timing
25
ns
TEWH
LE Pulse Width
See MICROWIRE Input Timing
25
ns
TCR
Falling Clock to Readback Time
See MICROWIRE Readback Timing
25
ns
Note 5: If emitter resistors are placed on the OSCout1/1* pins, there will be a DC current to ground which will cause powerdown Icc to increase.
Note 6: Load conditions for output clocks: LVDS: 100 Ω differential. See applications section Section 16.4.1 Current Consumption / Power Dissipation
Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.
Note 7: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is
0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the
device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible
to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest
possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
Note 8: FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.
Note 9: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f)
can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of
LPLL_flicker(f) and LPLL_flat(f).
Note 10: A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) 20log(N) - 10log(fPD). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPD is the phase detector frequency
of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
Note 11: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a
frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift
for continuous lock, then it will be necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed
at, the temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.
Note 12: Equal loading and identical clock output configuration on each clock output is required for specification to be valid.
Note 13: Guaranteed by characterization.
Note 14: Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values
are C1 = 220 pF, C2 = 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re =
240 Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 20 MHz the loop bandwidth = 62 kHz and phase margin =
76°.
Note 15: Jitter and phase noise data for 106.25 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values are C1 = 220 pF, C2
= 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler
disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 32 kHz and phase margin = 69°.
Note 16: Jitter and phase noise data for 622.08 MHz collected using a Vectron crystal, part number VXB1-1137-15M360. Loop filter values are C1 = 100 pF, C2
= 120 nF, R2 = 470 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference
doubler enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 54 kHz and phase margin = 86°.
Note 17: Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.
Note 18: Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values
are C1 = 39 pF, C2 = 3.3 nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240
Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 100 MHz the loop bandwidth = 80 kHz and phase margin = 60°.
Note 19: Jitter and phase noise data for 106.25 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values are C1 = 39pF, C2
= 3.3 nF, R2 = 820Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler
disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 80 kHz and phase margin = 60°.
Note 20: Jitter and phase noise data for 622.08 MHz collected using a Crystec oscillator, part number CVHD-950. Loop filter values are C1 = 39 pF, C2 = 3.3
nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler
enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 80 kHz and phase margin = 60°.
17
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LMK03806
Symbol
LMK03806
12.0 Measurement Definitions
12.1 SERIAL MICROWIRE TIMING DIAGRAM AND TERMINOLOGY
Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal.
On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A few programming
considerations are listed below:
•
•
•
A slew rate of at least 30 V/us is recommended for the programming signals
After the programming is complete, the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state
If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared
with other parts, the phase noise may be degraded during this programming.
30170103
FIGURE 5. MICROWIRE Timing Diagram
12.2 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY (Note 21)
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading
datasheets or communicating with other engineers. This section will address the measurement and description of a differential
signal so that the reader will be able to understand and discern between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and
non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being
described.
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to
the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this
signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes
with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description.
Figure 6 illustrates the two different definitions side-by-side for inputs and Figure 7 illustrates the two different definitions side-byside for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle between
with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference,
the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the
peak-to-peak voltage of the differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
30170175
30170174
FIGURE 6. Two Different Definitions for Differential Input
Signals
FIGURE 7. Two Different Definitions for Differential
Output Signals
Note 21: Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.
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18
LMK03806
13.0 Typical Performance Characteristics
13.2 CLOCK OUTPUT AC CHARACTERISTICS
LVDS VOD vs. Frequency
LVPECL /w 240 ohm emitter resistors VOD vs. Frequency
500
1200
450
1000
400
VOD (mV)
350
VOD (mV)
2000 mVpp
1600 mVpp
1200 mVpp
700 mVpp
300
250
200
800
600
400
150
100
200
50
0
0
0
500
1000 1500 2000 2500 3000
FREQUENCY (MHz)
0
30170141
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
30170142
LVPECL /w 120 ohm emitter resistors VOD vs. Frequency
1200
VOD (mV)
1000
2000 mVpp
800
600
1600 mVpp
400
200
0
0
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
30170143
19
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LMK03806
LVPECL, or LVCMOS output type. OSCout1 is fixed as
LVPECL.
Any LVPECL output type can be programmed to 700, 1200,
1600, or 2000 mVpp amplitude levels. The 2000 mVpp
LVPECL output type is a National Semiconductor proprietary
configuration that produces a 2000 mVpp differential swing
for compatibility with many data converters and is also known
as 2VPECL.
14.0 Features
14.1 CRYSTAL SUPPORT WITH BUFFERED OUTPUTS
The LMK03806 provides 2 dedicated outputs which are a
buffered copy of the PLL reference input. This reference input
is typically a low noise external clock or Crystal.
The OSCout0 buffer output type is programmable to LVDS,
LVPECL, or LVCMOS. The OSCout1 buffer is fixed to
LVPECL.
The dedicated output buffers OSCout0 and OSCout1 can
output frequency lower than the Input frequency by programming the OSC Divider. The OSC Divider value range is 1 to
8. Each OSCoutX can individually choose to use the OSC
Divider output or to bypass the OSC Divider.
Crystal buffered outputs cannot be synchronized to the VCO
clock distribution outputs. The assertion of SYNC will still
cause these outputs to become low. Since these outputs will
turn off and on asynchronously with respect to the VCO
sourced clock outputs during a SYNC, it is possible for glitches to occur on the buffered clock outputs when SYNC is
asserted and unasserted. If the NO_SYNC_CLKoutX_Y bits
are set these outputs will not be affected by the SYNC event
except that the phase relationship will change with the other
synchronized clocks unless a buffered clock output is used as
a qualification clock during SYNC.
14.4.3 CLOCK OUTPUT SYNCHRONIZATION
Using the SYNC input causes all active clock outputs to share
a rising edge.
By toggling the SYNC_POL_INV bit, it is possible to generate
a SYNC through uWire eliminating the need for connecting
the external SYNC pin to external circuitry.
14.5 DEFAULT STARTUP CLOCKS
Before the LMK03806 is programmed some clocks will operate at default frequencies upon power up. The active output
clocks depend upon the reference input type. If a crystal reference is used with OSCin, only CLKout8 will operate at a
nominal VCO frequency /25. When an XO or other external
reference is used as a reference with OSCin, OSCout0 will
buffer the OSCin frequency in addition to CLKout8 operating
at a nominal VCO frequency /25. These clocks can be used
to clock external devices such as microcontrollers, FPGAs,
CPLDs, etc. before the LMK03806 is programmed. Refer to
Figure 8 or Figure 9 for illustration of startup clocks.
The nominal VCO frequency of CLKout8 on power up will
typically be 98 MHz.
Note during programming CLKout8 may momentarily stop or
glitch during the VCO calibration routine.
14.2 INTEGRATED LOOP FILTER POLES
The LMK03806 features programmable 3rd and 4th order
loop filter poles for PLL. These internal resistors and capacitor
values may be selected from a fixed range of values to
achieve either a 3rd or 4th order loop filter response. The integrated programmable resistors and capacitors compliment
external components mounted near the chip.
These integrated components can be effectively disabled by
programming the integrated resistors and capacitors to their
minimum values.
14.3 INTEGRATED VCO
The output of the internal VCO is routed to a mux which allows
the user to select either the direct VCO output or a divided
version of the VCO for the Clock Distribution Path. This same
selection is also fed back to the PLL phase detector through
a prescaler and N-divider.
30170196
14.4 CLOCK DISTRIBUTION
The LMK03806 features a total of 12 outputs driven from the
internal or external VCO.
All VCO driven outputs have programmable output types.
They can be programmed to LVPECL, LVDS, or LVCMOS.
When all distribution outputs are configured for LVCMOS or
single-ended LVPECL a total of 24 outputs are available.
FIGURE 8. Startup Clock using Crystal Reference
14.4.1 CLKout DIVIDER
Each clock group, which is a pair of outputs such as CLKout0
and CLKout1, has a single clock output divider. The divider
supports a divide range of 1 to 1045 (even and odd) with 50%
output duty cycle. When divides of 26 or greater are used, the
divider block uses extended mode.
30170197
14.4.2 PROGRAMMABLE OUTPUT TYPE
For increased flexibility all LMK03806 clock outputs (CLKoutX) and OSCout0 can be programmed to an LVDS,
www.ti.com
FIGURE 9. Startup Clock using XO or other External
Reference
20
LMK03806 devices are programmed using 32-bit registers.
Each register consists of a 5-bit address field and 27-bit data
field. The address field is formed by bits 0 through 4 (LSBs)
and the data field is formed by bits 5 through 31 (MSBs). The
contents of each register is clocked in MSB first (bit 31), and
the LSB (bit 0) last. During programming, the LEuWire signal
should be held low. The serial data is clocked in on the rising
edge of the CLKuWire signal. After the LSB (bit 0) is clocked
in the LEuWire signal should be toggled low-to-high-to-low to
latch the contents into the register selected in the address
field. It is recommended to program registers in numeric order, for example R0 to R14, R16, R24, R26, and R28 to R31
to achieve proper device operation. Refer to the electric specifications sections for the timing for the programming.
To achieve proper frequency calibration, the OSCin port must
be driven with a valid signal before programming register R30.
Changes to PLL R divider or the OSCin port frequency require
register R30 to be reloaded in order to activate the frequency
calibration process.
15.3 READBACK
At no time should the MICROWIRE registers be programmed
to any value other than what is specified in the datasheet.
For debug of the MICROWIRE interface or programming, it is
recommended to simply program an LD_MUX to active low
and then toggle the output type register between output and
inverting output while observing the output pin for a low to high
transition. For example, to verify MICROWIRE programming,
set the LD_MUX = 0 (Low) and then toggle the LD_TYPE
register between 3 (Output, push-pull) and 4 (Output inverted,
pushpull). The result will be that the Ftest/LD pin will toggle
from low to high.
Readback from the MICROWIRE programming registers is
available. The MICROWIRE readback function can be accessed on the Readback pin. The READBACK_TYPE register can be programmed to "Output (push-pull)" for active
output, or for communication with FPGAs/microcontrollers
with lower voltage rails than 3.3 V the READBACK_TYPE
register can be programmed to "Output (Open-Drain)" while
connecting an external pull-up resistor to the voltage rail
needed.
To perform a readback operation:
1. Write the register address to be read back by
programming the READBACK_ADDR register in R31.
2. With the LEuWire pin held low continue to clock the
CLKuWire pin. On every rising edge of the CLKuWire pin
a new data bit is clocked onto the Readback pin.
3. Data is clocked out MSB first. After 32 clocks all the data
values will have been read and the read operation is
complete. The 5 LSB bits which are the address will be
undefined during readback.
15.1 SPECIAL PROGRAMMING CASE FOR R0 to R5 for
CLKoutX_Y_DIV > 25
When programming register R0 to R5 to change the
CLKoutX_Y_DIV divide value, the register must be programmed twice if the CLKoutX_Y_DIV value is greater than
25.
15.2 RECOMMENDED INITIAL PROGRAMMING
SEQUENCE
The registers are to be programmed in numeric order with R0
being the first and R31 being the last register programmed as
shown below:
1. Program R0 with RESET bit = 1. This ensures that the
device is configured with default settings. When RESET
= 1, all other R0 bits are ignored.
— If R0 is programmed again during the initial
configuration of the device, the RESET bit must be
cleared.
2. R0 through R5: CLKouts.
— Program as necessary to configure the clock outputs,
CLKout0 to CLKout11 as desired. These registers
configure clock output controls such as powerdown,
divider value, and clock source select.
3. R6 through R8: CLKouts.
— Program as necessary to configure the clock outputs,
CLKout0 to CLKout11 as desired. These registers
configure the output format for each clock output.
4. R9: Undisclosed bits.
— Program this register as shown in the register map for
proper operation.
5. R10: OSCouts.
6. R11: SYNC, and XTAL.
7. R12: LD pin and SYNC.
15.3.1 Readback example
To readback register R3 perform the following steps:
1. Write R31 with READBACK_ADDR = 3. DATAuWire and
CLKuWire are toggled as shown in Figure 5 with new
data being clocked in on rising edges of CLKuWire
2. Toggle LEuWire high and low as shown in Figure 5.
3. Toggle CLKuWire high and then low 32 times to read
back all 32 bits of register R3. Data is read MSB first.
Data is valid on falling edge of CLKuWire.
15.4 REGISTER MAP
Table 1 provides the register map for device programming. At
no time should registers be programmed to undefined values.
Only valid register values should be written.
21
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LMK03806
8. R13: Readback pin & GPout0.
9. R14: GPout1.
10. R16: Undisclosed bits.
— Program this register as shown in the register map for
proper operation.
11. R24: Partially integrated PLL filter values.
12. R26, R28, R29, and R30: PLL.
13. R31: uWire readback and uWire lock.
15.0 General Programming
Information
www.ti.com
0
CLKout
2_3_PD
Register
R0
R1
22
1
0
1
OSCout0_TYPE
[27:24]
1
0
0
R10
1
0
0
1
0
0
0
0
0
0
R9
0
0
0
0
CLKout10_TYPE
[27:24]
0
0
0
0
0
0
CLKout11_TYPE
[31:28]
0
0
0
0
0
0
R8
0
0
0
0
0
24
CLKout6_TYPE
[27:24]
0
0
0
0
25
CLKout7_TYPE
[31:28]
0
0
0
26
R7
0
0
27
CLKout2_TYPE
[27:24]
0
0
0
28
29
CLKout3_TYPE
[31:28]
CLKout CLKout CLKout CLKout
4_5_PD 6_7_PD 8_9_PD 10_11_PD
OSCout1
_TYPE
[31:30]
R6
R5
R4
R3
0
0
CLKout
0_1_PD
R2
30
31
0
0
0
0
0
0
22
0
0
0
0
0
0
21
0
0
0
0
0
0
20
18
17
0
0
0
1
0
OSCout1_MUX
1
0
1
OSCout_DIV
[18:16]
1
0
0
0
0
0
0
0
0
0
CLKout8_TYPE
[19:16]
0
0
0
0
0
0
0
0
CLKout4_TYPE
[19:16]
0
0
0
15
0
0
0
0
16
CLKout0_TYPE
[19:16]
0
0
Data [26:0]
19
OSCout0_MUX
EN_OSCout0
0
CLKout9_TYPE
[23:20]
CLKout5_TYPE
[23:20]
CLKout1_TYPE
[23:20]
0
0
0
0
0
0
23
1
1
0
0
0
14
TABLE 1. Register Map
RESET POWERDOWN
EN_OSCout1
0
0
0
0
0
13
11
10
9
8
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
CLKout10_11_DIV [15:5]
CLKout8_9_DIV [15:5]
CLKout6_7_DIV [15:5]
CLKout4_5_DIV [15:5]
CLKout2_3_DIV [15:5]
CLKout0_1_DIV [15:5]
12
0
0
0
0
0
7
0
1
0
0
0
6
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
4
2
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
Address [4:0]
3
0
1
0
1
0
1
0
1
0
1
0
0
LMK03806
23
0
0
0
0
0
0
0
0
0
PLL_P
0
0
0
R31
1
0
0
1
R30
0
PLL_CP
_GAIN
[27:26]
1
0
0
0
R29
0
0
PLL_C3_LF
[27:24]
PLL_R
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
PLL_R4_LF
[22:20]
1
0
0
18
17
0
0
0
0
0
1
0
0
0
GPout0
[18:16]
0
0
1
0
0
0
0
13
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11
0
0
0
0
0
PLL_N [22:5]
0
0
0
PLL_DLD_CNT
[19:6]
0
0
0
0
0
0
14
PLL_N_CAL [22:5]
0
0
0
0
1
0
0
0
15
16
PLL_R3_LF
[18:16]
1
0
1
0
Data [26:0]
19
READBACK_ADDR
[20:16]
0
0
OSCin_FREQ
[26:24]
0
0
0
R28
1
EN_PLL_
REF_2X
R26
1
1
0
0
1
GPout1
[26:24]
0
1
0
27
28
READBACK
_TYPE
[26:24]
26
1
0
25
NO_SYNC_CLKout10_11
0
24
NO_SYNC_CLKout8_9
0
23
NO_SYNC_CLKout6_7
Ftest/LD
_TYPE
[26:24]
22
NO_SYNC_CLKout4_5
R24
0
0
1
0
21
NO_SYNC_CLKout2_3
SYNC_PLL
_DLD
1
0
1
0
1
20
NO_SYNC_CLKout0_1
PLL_C4_LF
[31:28]
1
R16
0
R13
0
0
R12
0
29
SYNC_POL_INV
R14
0
Register
R11
30
SYNC_TYPE
[13:12]
0
0
0
1
0
0
0
0
10
0
0
0
0
0
0
0
0
9
0
0
0
0
0
0
0
0
8
0
0
0
0
0
0
0
0
7
0
0
0
0
0
0
1
0
6
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
1
2
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
0
0
1
0
0
1
Address [4:0]
0
3
4
5
1
0
1
0
0
0
0
0
1
0
1
0
LMK03806
31
EN_PLL_XTAL
uWire_LOCK
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Table 2 illustrates the default register settings programmed in silicon for the LMK03806 after power on or asserting the reset bit.
Capital X and Y represent numeric values.
Clock Output Control
Group
TABLE 2. Default Device Register Settings after Power On/Reset
Osc Buffer Control Mode
LMK03806
15.5 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON RESET
Default
Value
(decimal)
Default State
CLKout0_1_PD
1
PD
CLKout2_3_PD
1
PD
CLKout4_5_PD
1
PD
CLKout6_7_PD
0
Normal
CLKout8_9_PD
0
Normal
CLKout10_11_PD
1
PD
RESET
0
Not in reset
POWERDOWN
0
Disabled
(device is
active)
CLKout0_1_DIV
25
Divide-by-25
R0
CLKout2_3_DIV
25
Divide-by-25
R1
CLKout4_5_DIV
25
Divide-by-25
CLKout6_7_DIV
1
Divide-by-1
CLKout8_9_DIV
25
Divide-by-25
R4
CLKout10_11_DIV
25
Divide-by-25
R5
CLKout3_TYPE
0
Powerdown
R6
CLKout7_TYPE
0
Powerdown
R7
CLKout11_TYPE
0
Powerdown
R8
CLKout2_TYPE
0
Powerdown
R6
CLKout6_TYPE
8
LVCMOS
(Norm/Norm)
R7
CLKout10_TYPE
0
Powerdown
CLKout1_TYPE
0
Powerdown
CLKout5_TYPE
0
Powerdown
R7
CLKout9_TYPE
0
Powerdown
R8
CLKout0_TYPE
0
Powerdown
R6
CLKout4_TYPE
0
Powerdown
R7
CLKout8_TYPE
1
LVDS
R8
OSCout1_TYPE
2
1600 mVpp
LVPECL
OSCout0_TYPE
1
LVDS
EN_OSCout1
0
EN_OSCout0
1
Field Name
Field Description
Bit Location
(MSB:LSB)
R0
R1
Powerdown control for divider, and both
output buffers
R2
R3
31
R4
R5
Performs power on reset for device
R0
17
Device power down control
R1
17
Divide for clock outputs
Individual clock output format. Select
from LVDS/LVPECL/LVCMOS.
R2
R3
15:5 [11]
31:28 [4]
27:24 [4]
R8
R6
23:20 [4]
19:16 [4]
Set LVPECL amplitude
R10
31:30 [2]
OSCout0 default clock output
R10
27:24 [4]
Disabled
Disable OSCout1 output buffer
R10
23
Enabled
Enable OSCout0 output buffer
R10
22
R10
21
Select OSCout divider for OSCout0 or
bypass
R10
20
OSCout divider value
R10
18:16 [3]
OSCout1_MUX
0
Select OSCout divider for OSCout1 or
Bypass Divider
bypass
OSCout0_MUX
0
Bypass Divider
OSCout_DIV
0
Divide-by-8
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Register
24
Group
SYNC Control
Other Mode Control
GPout
PLL Control
uWire
Default State
NO_SYNC_CLKout10_11
0
Will sync
NO_SYNC_CLKout8_9
1
Will not sync
NO_SYNC_CLKout6_7
1
Will not sync
NO_SYNC_CLKout4_5
0
Will sync
NO_SYNC_CLKout2_3
0
NO_SYNC_CLKout0_1
0
Register
Bit Location
(MSB:LSB)
R11
25
R11
24
R11
23
R11
22
Will sync
R11
21
Will sync
R11
20
Sets the polarity of the SYNC pin when
input. (Use for software SYNC)
R11
16
13:12 [2]
Field Description
Disable individual clock groups from
becoming synchronized.
SYNC_POL_INV
1
Logic Low
SYNC_TYPE
1
Input /w
Pull-up
SYNC IO pin type
R11
EN_PLL_XTAL
0
Disabled
Enable Crystal oscillator for OSCin
R11
5
LD_MUX
3
Reserved
Ftest/LD pin selection when output
R12
31:27 [5]
LD_TYPE
3
Output
(Push-Pull)
LD IO pin type
R12
26:24 [3]
SYNC_PLL_DLD
0
No effect
When set, force SYNC until PLL locks
R12
23
READBACK_TYPE
3
R13
26:24 [3]
GPout0
2
Weak pulldown
GPout0 output state
R13
18:16 [3]
GPout1
2
Weak pulldown
GPout1 output state
R14
28:26 [3]
PLL_C4_LF
0
10 pF
PLL integrated capacitor C4 value
R24
31:28 [4]
PLL_C3_LF
0
10 pF
PLL integrated capacitor C3 value
R24
27:24 [4]
PLL_R4_LF
0
200 Ω
PLL integrated resistor R4 value
R24
22:20 [3]
PLL_R3_LF
0
PLL integrated resistor R3 value
R24
18:16 [3]
EN_PLL_REF_2X
0
200 Ω
Disabled, 1x
Doubles reference frequency of PLL.
R26
29
PLL_CP_GAIN
3
3.2 mA
PLL Charge Pump Gain
R26
27:26 [2]
PLL_DLD_CNT
8192
8192 Counts
Number of PDF cycles which phase
error must be within DLD window before
LD state is asserted.
R26
19:6 [14]
PLL R Divider (1 to 4095)
R28
31:20 [12]
R29
26:24 [3]
Output (PushReadback Pin Type
Pull)
PLL_R
4
OSCin_FREQ
7
Divide-by-4
PLL_N_CAL
48
Divide-by-48
Must be programmed to PLL_N value.
R29
22:5 [18]
PLL_P
2
Divide-by-2
PLL N Divider Prescaler (2 to 8)
R30
26:24 [3]
PLL_N
48
Divide-by-48
PLL N Divider (1 to 262143)
R30
22:5 [18]
uWire_LOCK
0
Writable
The values of registers R0 to R30 are
lockable
R31
5
448 to 500 MHz OSCin frequency range
25
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LMK03806
Default
Value
(decimal)
Field Name
LMK03806
15.6.3 POWERDOWN
The POWERDOWN bit is located in register R1 only. Setting
the bit causes the device to enter powerdown mode. Normal
operation is resumed by clearing this bit with MICROWIRE.
15.6 REGISTER R0 TO R5
Registers R0 through R5 control the 12 clock outputs CLKout0 to CLKout11. Register R0 controls CLKout0 and CLKout1, Register R1 controls CLKout2 and CLKout3, and so on.
The X and Y in CLKoutX_Y_PD, CLKoutX_Y_DIV denote the
actual clock output which may be from 0 to 11 where X is even
and Y is odd. Two clock outputs CLKoutX and CLKoutY form
a clock output group and are often run together in bit names
as CLKoutX_Y.
Two additional bits within the R0 to R5 register range are:
• The RESET bit, which is only in register R0.
• The POWERDOWN bit, which is only in register R1.
POWERDOWN
R1[17]
State
0
Normal operation
1
Powerdown
15.6.4 CLKoutX_Y_DIV, Clock Output Divide
CLKoutX_Y_DIV sets the divide value for the clock group.
The divide may be even or odd. Both even and odd divides
output a 50% duty cycle clock.
Using a divide value of 26 or greater will cause the clock group
to operate in extended mode.
Programming CLKoutX_Y_DIV can require special attention.
15.6.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output
Path
This bit powers down the clock group as specified by CLKoutX
and CLKoutY. This includes the divider and output buffers.
CLKoutX_Y_PD
R0-R5[31]
State
0
Power up clock group
1
Power down clock group
CLKoutX_Y_DIV, 11 bits
15.6.2 RESET
The RESET bit is located in register R0 only. Setting this bit
will cause the silicon default values to be loaded. When programming register R0 with the RESET bit set, all other programmed values are ignored. After resetting the device, the
register R0 must be programmed again (with RESET = 0) to
set non-default values in register R0.
The reset occurs on the falling edge of the LEuWire pin which
loaded R0 with RESET = 1.
The RESET bit is automatically cleared upon writing any other
register. For instance, when R0 is written to again with default
values.
RESET
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R0-R5[15:5]
Divide Value
0 (0x00)
Reserved
1 (0x01)
1
2 (0x02)
2 (Note 22)
3 (0x03)
3
4 (0x04)
4 (Note 22)
5 (0x05)
5 (Note 22)
6 (0x06)
6
...
...
24 (0x18)
24
25 (0x19)
25
26 (0x1A)
26
27 (0x1B)
27
...
...
R0[17]
State
1044 (0x414)
1044
0
Normal operation
1045 (0x415)
1045
1
Reset (automatically cleared)
Power Mode
Normal Mode
Extended Mode
Note 22: After programming PLL_N value, a SYNC must occur on channels
using this divide value. Programming PLL_N does generate a SYNC event
automatically which satisfies this requirement, but NO_SYNC_CLKoutX_Y
must be set to 0 for these clock groups.
26
15.7.1 CLKoutX_TYPE
The clock output types of the LMK03806 are individually programmable. The CLKoutX_TYPE registers set the output
type of an individual clock output to LVDS, LVPECL, LVCMOS, or powers down the output buffer. Note that LVPECL
supports four different amplitude levels and LVCMOS supports single LVCMOS outputs, inverted, and normal polarity
of each output pin for maximum flexibility.
The programming addresses table shows at what register and
address the specified clock output CLKoutX_TYPE register is
located.
The CLKoutX_TYPE table shows the programming definition
for these registers.
15.9 REGISTER R10
15.9.1 OSCout1_TYPE, LVPECL Output Amplitude
Control
The OSCout1 clock output can only be used as an LVPECL
output type. OSCout1_TYPE sets the LVPECL output amplitude of the OSCout1 clock output.
OSCout1_TYPE, 2 bits
R10[31:30]
CLKoutX_TYPE Programming Addresses
CLKoutX
Programming Address
CLKout0
R6[19:16]
CLKout1
R6[23:20]
CLKout2
R6[27:24]
CLKout3
R6[31:28]
CLKout4
R7[19:16]
CLKout5
R7[23:20]
CLKout6
R7[27:24]
CLKout7
R7[31:28]
CLKout8
R8[19:16]
CLKout9
R8[23:20]
CLKout10
R8[27:24]
CLKout11
R8[31:28]
Output Format
0 (0x00)
LVPECL (700 mVpp)
1 (0x01)
LVPECL (1200 mVpp)
2 (0x02)
LVPECL (1600 mVpp)
3 (0x03)
LVPECL (2000 mVpp)
15.9.2 OSCout0_TYPE
The OSCout0 clock output has a programmable output type.
The OSCout0_TYPE register sets the output type to LVDS,
LVPECL, LVCMOS, or powers down the output buffer. Note
that LVPECL supports four different amplitude levels and
LVCMOS supports dual and single LVCMOS outputs with inverted, and normal polarity of each output pin for maximum
flexibility.
To turn on the output, the OSCout0_TYPE must be set to a
non-power down setting and enabled with Section 15.9.3
EN_OSCoutX, OSCout Output Enable.
OSCout0_TYPE, 4 bits
CLKoutX_TYPE, 4 bits
R10[27:24]
Definition
0 (0x00)
Powerdown
Definition
1 (0x01)
LVDS
0 (0x00)
Power down
2 (0x02)
LVPECL (700 mVpp)
1 (0x01)
LVDS
3 (0x03)
LVPECL (1200 mVpp)
2 (0x02)
LVPECL (700 mVpp)
4 (0x04)
LVPECL (1600 mVpp)
LVPECL (1200 mVpp)
5 (0x05)
LVPECL (2000 mVpp)
4 (0x04)
LVPECL (1600 mVpp)
6 (0x06)
LVCMOS (Norm/Inv)
5 (0x05)
LVPECL (2000 mVpp)
7 (0x07)
LVCMOS (Inv/Norm)
6 (0x06)
LVCMOS (Norm/Inv)
8 (0x08) (Note 24)
LVCMOS (Norm/Norm)
7 (0x07)
LVCMOS (Inv/Norm)
9 (0x09) (Note 24)
LVCMOS (Inv/Inv)
8 (0x08) (Note 23)
LVCMOS (Norm/Norm)
10 (0x0A) (Note 24)
LVCMOS (Low/Norm)
LVCMOS (Inv/Inv)
11 (0x0B) (Note 24)
LVCMOS (Low/Inv)
10 (0x0A) (Note 23)
LVCMOS (Low/Norm)
12 (0x0C) (Note 24)
LVCMOS (Norm/Low)
11 (0x0A) (Note 23)
LVCMOS (Low/Inv)
13 (0x0D) (Note 24)
LVCMOS (Inv/Low)
LVCMOS (Norm/Low)
14 (0x0E) (Note 24)
LVCMOS (Low/Low)
R6-R8[31:28, 27:24, 23:20]
3 (0x03)
9 (0x09) (Note 23)
12 (0x0C) (Note 23)
13 (0x0D) (Note 23)
LVCMOS (Inv/Low)
14 (0x0E) (Note 23)
LVCMOS (Low/Low)
Note 24: It is recommended to use one of the complementary LVCMOS
modes. Best noise performance is achieved using LVCMOS (Norm/Inv) or
LVCMOS (Inv/Norm) due to the differential switching of the outputs. The next
best performance is achieved using an LVCMOS mode with only one output
on. Finally, LVCMOS (Norm/Norm) or LVCMOS (Inv/Inv) have the create
the most switching noise.
Note 23: It is recommended to use one of the complementary LVCMOS
modes. Best noise performance is achieved using LVCMOS (Norm/Inv) or
LVCMOS (Inv/Norm) due to the differential switching of the outputs. The next
best performance is achieved using an LVCMOS mode with only one output
on. Finally, LVCMOS (Norm/Norm) or LVCMOS (Inv/Inv) have the create
the most switching noise.
27
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LMK03806
15.8 REGISTER R9
Register 9 contains no user programmable bits, but must be
programmed as described in the register map.
15.7 REGISTERS R6 TO R8
LMK03806
15.10 REGISTER R11
15.9.3 EN_OSCoutX, OSCout Output Enable
EN_OSCoutX is used to enable an oscillator buffered output.
15.10.1 NO_SYNC_CLKoutX_Y
The NO_SYNC_CLKoutX_Y bits prevent individual clock
groups from becoming synchronized during a SYNC event. A
reason to prevent individual clock groups from becoming synchronized is that during synchronization, the clock output is
in a fixed low state or can have a glitch pulse.
By disabling SYNC on a clock group, it will continue to operate
normally during a SYNC event.
Setting the NO_SYNC_CLKoutX_Y bit has no effect on
clocks already synchronized together.
EN_OSCout1
R10[23]
Output State
0
OSCout1 Disabled
1
OSCout1 Enabled
EN_OSCout0
R10[22]
Output State
0
OSCout0 Disabled
1
OSCout0 Enabled
NO_SYNC_CLKoutX_Y Programming Addresses
OSCout0 note: In addition to enabling the output with EN_OSCout0. The OSCout0_TYPE must be programmed to a nonpower down value for the output buffer to power up.
NO_SYNC_CLKoutX_Y
Programming Address
CLKout0 and 1
R11:20
CLKout2 and 3
R11:21
15.9.4 OSCoutX_MUX, Clock Output Mux
Sets OSCoutX buffer to output a divided or bypassed OSCin
signal. .
CLKout4 and 5
R11:22
CLKout6 and 7
R11:23
CLKout8 and 9
R11:24
OSCout1_MUX
CLKout10 and 11
R11:25
R10[21]
Mux Output
0
Bypass divider
1
NO_SYNC_CLKoutX_Y
Divided
R11[25, 24, 23, 22, 21, 20]
Definition
0
CLKoutX_Y will synchronize
1
CLKoutX_Y will not
synchronize
OSCout0_MUX
R10[20]
Mux Output
0
Bypass divider
1
Divided
15.10.2 SYNC_POL_INV
Sets the polarity of the SYNC pin when input. When SYNC is
asserted the clock outputs will transition to a low state.
15.9.5 OSCout_DIV, Oscillator Output Divide
The OSCout divider can be programmed from 2 to 8. Divide
by 1 is achieved by bypassing the divider with Section 15.9.4
OSCoutX_MUX, Clock Output Mux.
SYNC_POL_INV
OSCout_DIV, 3 bits
R11[16]
Polarity
0
SYNC is active high
1
SYNC is active low
R10[18:16]
Divide
0 (0x00)
8
1 (0x01)
2
2 (0x02)
2
3 (0x03)
3
R11[13:12]
4 (0x04)
4
0 (0x00)
Input
5 (0x05)
5
1 (0x01)
Input /w pull-up resistor
6 (0x06)
6
2 (0x02)
Input /w pull-down resistor
7 (0x07)
7
15.10.3 SYNC_TYPE
Sets the IO type of the SYNC pin.
SYNC_TYPE, 2 bits
Polarity
15.10.4 EN_PLL_XTAL
If an external crystal is being used to implement a discrete
VCXO, the internal feedback amplifier must be enabled with
this bit in order to complete the oscillator circuit.
EN_PLL_XTAL
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28
R11[5]
Oscillator Amplifier State
0
Disabled
1
Enabled
15.12 REGISTER R13
15.11.1 LD_MUX
LD_MUX sets the output value of the Ftest/LD pin.
All the outputs logic is active high when LD_TYPE = 3 (Output). All the outputs logic is active low when LD_TYPE = 4
(Output Inverted). For example, when LD_MUX = 0 (Logic
Low) and LD_TYPE = 3 (Output) then Ftest/LD pin outputs a
logic low. When LD_MUX = 0 (Logic Low) and LD_TYPE = 4
(Output Inverted) then Ftest/LD pin outputs a logic high.
15.12.1 READBACK_TYPE
Sets the IO format of the readback pin. The open drain output
type can be used to interface the LMK03806 with low voltage
IO rails.
READBACK_TYPE, 3 bits
LD_MUX, 5 bits
R13[26:24]
Polarity
0 (0x00)
Reserved
1 (0x01)
Reserved
Divide
2 (0x02)
Reserved
0 (0x00)
Logic Low
3 (0x03)
Output (push-pull)
1 (0x01)
Reserved
4 (0x04)
Output inverted (push-pull)
PLL DLD
5 (0x05)
Output (open source)
Reserved
6 (0x06)
Output (open drain)
R12[31:27]
2 (0x02)
3 (0x03)
...
...
12 (0x0C)
Reserved
13 (0x0D)
PLL N
14 (0x0E)
PLL N/2
15 (0x0F)
Reserved
16 (0x10)
Reserved
17 (0x11)
PLL R (Note 25)
18 (0x12)
PLL R/2 (Note 25)
15.12.2 GPout0
Sets the output state of the GPout0 pin.
GPout0, 3 bits
Note 25: Only valid when LD_MUX is not set to 2 (PLL_DLD).
15.11.2 LD_TYPE
Sets the IO type of the LD pin.
R13[18:16]
Output State
0 (0x00)
Reserved
1 (0x01)
Reserved
2 (0x02)
Weak pull-down
3 (0x03)
Low (0 V)
4 (0x04)
High (3.3 V)
15.13 REGISTER 14
15.13.1 GPout1
Sets the output state of the GPout1 pin.
LD_TYPE, 3 bits
R12[26:24]
Polarity
0 (0x00)
Reserved
1 (0x01)
Reserved
2 (0x02)
Reserved
3 (0x03)
Output (push-pull)
4 (0x04)
Output inverted (push-pull)
5 (0x05)
Output (open source)
6 (0x06)
Output (open drain)
GPout1, 3 bits
R14[26:24]
Output State
0 (0x00)
Reserved
1 (0x01)
Reserved
2 (0x02)
Weak pull-down
3 (0x03)
Low (0 V)
4 (0x04)
High (3.3 V)
15.11.3 SYNC_PLL_DLD
By setting SYNC_PLL_DLD a SYNC mode will be engaged
(asserted SYNC) until the PLL locks.
SYNC_PLL_DLD
R12[23]
Sync Mode Forced
0
No
1
Yes
29
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LMK03806
15.11 REGISTER R12
LMK03806
15.14 REGISTER 16
Register 16 contains no user programmable bits, but must be
programmed as described in the register map.
15.15 REGISTER 24
15.15.1 PLL_C4_LF, PLL Integrated Loop Filter
Component
Internal loop filter components are available for the PLL, enabling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter capacitor C4 can be set according to the
following table.
25 pF
8 (0x08)
29 pF
9 (0x09)
30 pF
10 (0x0A)
33 pF
11 (0x0B)
34 pF
12 (0x0C)
38 pF
13 (0x0D)
39 pF
14 (0x0E)
Reserved
15 (0x0F)
Reserved
15.15.3 PLL_R4_LF, PLL Integrated Loop Filter
Component
Internal loop filter components are available for the PLL, enabling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter resistor R4 can be set according to the following table.
PLL_C4_LF, 4 bits
R24[31:28]
Loop Filter Capacitance (pF)
0 (0x00)
10 pF
1 (0x01)
15 pF
2 (0x02)
29 pF
3 (0x03)
34 pF
4 (0x04)
47 pF
R24[22:20]
Resistance
5 (0x05)
52 pF
0 (0x00)
6 (0x06)
66 pF
200 Ω
1 (0x01)
1 kΩ
7 (0x07)
71 pF
2 (0x02)
8 (0x08)
103 pF
2 kΩ
9 (0x09)
108 pF
3 (0x03)
4 kΩ
10 (0x0A)
122 pF
11 (0x0B)
126 pF
12 (0x0C)
141 pF
13 (0x0D)
146 pF
14 (0x0E)
Reserved
15 (0x0F)
Reserved
PLL_R4_LF, 3 bits
Loop Filter Capacitance (pF)
0 (0x00)
10 pF
16 kΩ
5 (0x05)
Reserved
6 (0x06)
Reserved
7 (0x07)
Reserved
PLL_R3_LF, 3 bits
PLL_C3_LF, 4 bits
R24[27:24]
4 (0x04)
15.15.4 PLL_R3_LF, PLL Integrated Loop Filter
Component
Internal loop filter components are available for the PLL, enabling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter resistor R3 can be set according to the following table.
15.15.2 PLL_C3_LF, PLL Integrated Loop Filter
Component
Internal loop filter components are available for the PLL, enabling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter capacitor C3 can be set according to the
following table.
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7 (0x07)
R24[18:16]
Resistance
0 (0x00)
200 Ω
1 (0x01)
1 kΩ
2 (0x02)
2 kΩ
1 (0x01)
11 pF
3 (0x03)
2 (0x02)
15 pF
4 (0x04)
16 kΩ
3 (0x03)
16 pF
5 (0x05)
Reserved
4 (0x04)
19 pF
6 (0x06)
Reserved
5 (0x05)
20 pF
7 (0x07)
Reserved
6 (0x06)
24 pF
30
4 kΩ
15.17 REGISTER 28
15.16.1 EN_PLL_REF_2X, PLL Reference Frequency
Doubler
Enabling the PLL reference frequency doubler allows for higher phase detector frequencies on the PLL than would normally
be allowed with the given VCXO or Crystal frequency.
Higher phase detector frequencies reduces the PLL N values
which makes the design of wider loop bandwidth filters possible.
15.17.1 PLL_R, PLL R Divider
The reference path into the PLL phase detector includes the
PLL R divider.
The valid values for PLL_R are shown in the table below.
PLL_R, 12 bits
EN_PLL_REF_2X
R28[31:20]
Divide
0 (0x00)
Not Valid
1 (0x01)
1
2
R26[29]
Description
2 (0x02)
0
Reference frequency normal
3 (0x03)
3
1
Reference frequency
doubled (2x)
...
...
4,094 (0xFFE)
4,094
4,095 (0xFFF)
4,095
15.16.2 PLL_CP_GAIN, PLL Charge Pump Current
This bit programs the PLL charge pump output current level.
PLL_CP_GAIN, 2 bits
R26[27:26]
Charge Pump Current (µA)
0 (0x00)
100
1 (0x01)
400
2 (0x02)
1600
3 (0x03)
3200
15.16.3 PLL_DLD_CNT
The reference and feedback of the PLL must be within the
window of acceptable phase error for PLL_DLD_CNT cycles
before PLL digital lock detect is asserted.
PLL_DLD_CNT, 14 bits
R26[19:6]
Divide
0 (0x00)
Reserved
1 (0x01)
1
2 (0x02)
2
3 (0x03)
3
...
...
16,382 (0x3FFE)
16,382
16,383 (0x3FFF)
16,383
31
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LMK03806
15.16 REGISTER 26
LMK03806
PLL_N, 18 bits
15.18 REGISTER 29
15.18.1 OSCin_FREQ, PLL Oscillator Input Frequency
Register
The frequency of the PLL reference input to the PLL Phase
Detector (OSCin/OSCin* port) must be programmed in order
to support proper operation of the frequency calibration routine which locks the internal VCO to the target frequency.
OSCin Frequency
0 (0x00)
0 to 63 MHz
1 (0x01)
>63 MHz to 127 MHz
2 (0x02)
>127 MHz to 255 MHz
3 (0x03)
0 (0x00)
Not Valid
1 (0x01)
1
2 (0x02)
2
262,143 (0x3FFFF)
262,143
15.20 REGISTER 31
15.20.1 READBACK_ADDR
READBACK_ADDR
Reserved
4 (0x04)
Divide
...
OSCin_FREQ, 3 bits
R29[26:24]
R30[22:5]
>255 MHz to 500 MHz
R31[20:16]
State
0
R0
1
R1
15.18.2 PLL_N_CAL, PLL N Calibration Divider
During the frequency calibration routine, the PLL uses the divide value of the PLL_N_CAL register instead of the divide
value of the PLL_N register to lock the VCO to the target frequency.
2
R2
3
R3
4
R4
5
R5
PLL_N_CAL, 18 bits
6
R6
Divide
7
R7
Not Valid
8
R8
1 (0x01)
1
9
R9
2 (0x02)
2
10
R10
...
11
R11
262,143
12
R12
13
R13
R29[22:5]
0 (0x00)
...
262,143 (0x3FFFF)
15.19 REGISTER 30
Programming Register 30 triggers the frequency calibration
routine. This calibration routine will also generate a SYNC
event.
15.19.1 PLL_P, PLL N Prescaler Divider
The PLL N Prescaler divides the output of the VCO and is
connected to the PLL N divider.
PLL_P, 3 bits
R30[26:24]
Divide Value
0 (0x00)
8
1 (0x01)
2
2 (0x02)
2
3 (0x03)
3
4 (0x04)
4
5 (0x05)
5
6 (0x06)
6
7 (0x07)
7
R14
15
Reserved
16
R16
17
Reserved
...
...
23
Reserved
24
R24
25
Reserved
26
R26
27
Reserved
28
R28
29
R29
30
R30
15.20.2 uWire_LOCK
Setting uWire_LOCK will prevent any changes to uWire registers R0 to R30. Only by clearing the uWire_LOCK bit in R31
can the uWire registers be unlocked and written to once more.
It is not necessary to lock the registers to perform a readback
operation.
15.19.2 PLL_N, PLL N Divider
The feeback path into the PLL phase detector includes the
PLL N divider.
Each time register 30 is updated via the MICROWIRE interface, a frequency calibration routine runs to lock the VCO to
the target frequency. During this calibration PLL_N is substituted with PLL_N_CAL.
The valid values for PLL_N are shown in the table below.
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14
uWire_LOCK
32
R31[5]
State
0
Registers unlocked
1
Registers locked, Writeprotect
level with RLIM shorted, then a zero value for RLIM can be used.
As a starting point, a suggested value for RLIM is 1.5 kΩ.
16.1 Crystal Interface
The LMK03806 has an integrated crystal oscillator circuit on
that supports a fundamental mode, AT-cut crystal. The crystal
interface is shown in Figure 10.
16.2 External Reference Interface
The LMK03806 has an the ability to be driven by an external
reference. Typical external reference interfaces are shown in
Figure 11 and Figure 12.
In applications where the external reference amplitude is less
than the VOSCin specification of 2.4 Vpp Figure 11 is an appropriate method of interfacing the reference to the LMK03806.
In applications where the external reference amplitude is
greater than the VOSCin specification of 2.4 Vpp Figure 12 is an
appropriate method of interfacing the reference to the
LMK03806.
In both cases C1 and C2 should be present a low impedance
at the reference frequency. A typical value for C1 and C2 is
0.1 µF.
30170194
FIGURE 10. Crystal Interface
The load capacitance (CL) is specific to the crystal, but usually
on the order of 18 - 20 pF. While CL is specified for the crystal,
the OSCin input capacitance (CIN = 6 pF typical) of the device
and PCB stray capacitance (CSTRAY ~ 1~3 pF) can affect the
discrete load capacitor values, C1 and C2.
For the parallel resonant circuit, the discrete capacitor values
can be calculated as follows:
CL = (C1 * C2) / (C1 + C2) + CIN + CSTRAY
30170198
(1)
FIGURE 11. LVCMOS External Reference Interface
Typically, C1 = C2 for optimum symmetry, so Equation 1 can
be rewritten in terms of C1 only:
CL = C12 / (2 * C1) + CIN + CSTRAY
(2)
Finally, solve for C1:
C1 = (CL – CIN – CSTRAY)*2
(3)
Section 11.0 Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the
crystal, but it does not specify crystal power dissipation. The
designer will need to ensure the crystal power dissipation
does not exceed the maximum drive level specified by the
crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level
should be held at a sufficient level necessary to start-up and
maintain steady-state operation.
The power dissipated in the crystal, PXTAL, can be computed
by:
PXTAL = IRMS2 * RESR*(1 + C0/CL)2
30170199
FIGURE 12. 3.3 Vpp External Reference Interface
Using an external reference, such as a crystal oscillator (XO),
may provide better phase noise than a crystal at offsets below
the loop bandwidth. If the jitter integration bandwidth for the
application of interest is above the loop filter bandwidth, the
added phase noise of a crystal will not be a significant jitter
contributor and may be a more cost effective solution than an
XO. Also, operating at higher reference frequencies allows
higher phase detector frequencies, which also improves in
band PLL phase noise performance.
(4)
Where:
• IRMS is the RMS current through the crystal.
• RESR is the max. equivalent series resistance specified for
the crystal
• CL is the load capacitance specified for the crystal
• C0 is the min. shunt capacitance specified for the crystal
IRMS can be measured using a current probe (e.g. Tektronix
CT-6 or equivalent) placed on the leg of the crystal connected
to OSCin* with the oscillation circuit active.
As shown in Figure 10, an external resistor, RLIM, can be used
to limit the crystal drive level, if necessary. If the power dissipated in the selected crystal is higher than the drive level
specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive
33
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LMK03806
16.0 Application Information
LMK03806
A user specified ppm accuracy for lock detect is programmable using a lock count register. By using Equation 5,
values for a "lock count" and "window size" can be chosen to
set the frequency accuracy required by the system in ppm
before the digital lock detect event occurs. Units of PD are
Hertz:
16.3 DIGITAL LOCK DETECT
The digital lock detect circuit is used to determine the lock
status of the PLL. The flowchart in Figure 13 shows the general way this circuit works.
TABLE 3.
Event
PLL
Window size (ε)
Lock count
PLL
Locked
PLL
3.7 ns
PLL_DLD_CNT
(5)
The effect of the "lock count" value is that it shortens the effective lock window size by dividing the "window size" by "lock
count".
If at any time the PLL_R reference and PLL_N feedback signals are outside the time window set by "window size", then
the “lock count” value is reset to 0.
For example, to calculate the minimum PLL digital lock time
given a PLL phase detector frequency of 40 MHz and
PLL_DLD_CNT = 10,000. Then the minimum lock time of PLL
will be 10,000 / 40 MHz = 250 µs.
For a digital lock detect event to occur there must be a number
of PLL phase detector cycles during which the time/phase error of the PLL_R reference and PLL_N feedback signal edges
are within the 3.7 ns window size of the LMK03806. “Lock
count” is the term which is used to specify how many PLL
phase detector cycles have been within the window size of
3.7 ns at any given time. Since there must be a specified
number phase detector events before a lock event occurs, a
minimum digital lock event time can be calculated as "lock
count" / fPD.
30170128
FIGURE 13. Digital Lock Detect Flow Diagram
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34
16.4.1 Current Consumption / Power Dissipation
Calculations
From Table 4 the current consumption can be calculated for
any configuration.
For example, the current for the entire device with 1 LVDS
(CLKout0) and 1 LVPECL 1.6 Vpp /w 240 ohm emitter resistors (CLKout1) output active with a clock output divide = 1,
and no other features enabled can be calculated by adding
up the following blocks: core current, base clock distribution,
clock output group, clock divider, one LVDS output buffer current, and one LVPECL output buffer current. There will also
be one LVPECL output drawing emitter current, which means
some of the power from the current draw of the device is dissipated in the external emitter resistors which doesn't add to
the thermal power dissipation budget for the device. In addition to emitter resistor power, power dissipated in the load for
LVDS/LVPECL do not contribute to the thermal power dissipation budget for the device.
TABLE 4. Typical Current Consumption for Selected Functional Blocks (TA = 25 °C, VCC = 3.3 V)
Typical ICC
(mA)
Power
dissipated
in device
(mW)
Power
dissipated
externally
(mW)
Block
Condition
Core
Internal VCO Locked
122
403
-
Base Clock
Distribution
At least 1 CLKoutX_Y_PD = 0
17.3
57.1
-
CLKout Group
Each CLKout group (CLKout0/1 & 10/11, CLKout2/3 & 4/5, CLKout
6/7 & 8/9)
2.8
9.2
-
Divide < 25
25.5
84.1
-
Divide >= 25
29.6
97.7
-
SYNC Asserted
While SYNC is asserted, this extra current is drawn
1.7
5.6
-
Crystal Mode
Crystal Oscillator Buffer
1.8
5.9
-
OSCin Doubler
EN_OSCin_2X = 1
2.8
9.2
-
14.3
45.7
1.5
LVPECL 2.0 Vpp, AC coupled using 240 ohm emitter resistors
32
70.6
35
LVPECL 1.6 Vpp, AC coupled using 240 ohm emitter resistors
31
67.3
35
LVPECL 1.6 Vpp, AC coupled using 120 ohm emitter resistors
46
91.8
60
LVPECL 1.2 Vpp, AC coupled using 240 ohm emitter resistors
30
59
40
LVPECL 0.7 Vpp, AC coupled using 240 ohm emitter resistors
29
55.7
40
LVCMOS Pair
(CLKoutX_Y_TYPE
= 6 to 10)
CL = 5 pF
3 MHz
24
79.2
-
30 MHz
26.5
87.5
-
150 MHz
36.5
120.5
-
LVCMOS Single
(CLKoutX_Y_TYPE
= 11 to 13)
CL = 5 pF
3 MHz
15
49.5
-
30 MHz
16
52.8
-
150 MHz
21.5
71
-
Core and Functional Blocks
Clock Divider
Clock Output Buffers
LVDS
LVPECL
(Note 26)
LVCMOS
100 ohm differential termination
Note 26: Power is dissipated externally in LVPECL emitter resistors. The externally dissipated power is calculated as twice the DC voltage level of one LVPECL
clock output pin squared over the emitter resistance. That is to say power dissipated in emitter resistors = 2 * Vem2 / Rem.
Note 27: Assuming θJA = 15 °C/W, the total power dissipated on chip must be less than (125 °C – 85 °C) / 16 °C/W = 2.5 W to guarantee a junction temperature
is less than 125 °C.
Note 28: Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.15.
35
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LMK03806
For total current consumption of the device, add up the significant functional blocks. In this example, 212.9 mA =
• 122 mA (core current)
• 17.3 mA (base clock distribution)
• 2.8 mA (CLKout group for 2 outputs)
• 25.5 mA (CLKout0 & 1 divider)
• 14.3 mA (LVDS buffer)
• 31 mA (LVPECL 1.6 Vpp buffer /w 240 ohm emitter
resistors)
Once total current consumption has been calculated, power
dissipated by the device can be calculated. The power dissipation of the device is equation to the total current entering
the device multiplied by the voltage at the device minus the
power dissipated in any emitter resistors connected to any of
the LVPECL outputs or any other external load power dissipation. Continuing the above example which has 212.9 mA
total Icc and one output with 240 ohm emitter resistors and
one LVDS output. Total IC power = 666 mW = 3.3 V * 212.9
mA - 35 mW - 1.5 mW.
16.4 POWER SUPPLY
LMK03806
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 14 should connect these top and bottom
copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
16.5 THERMAL MANAGEMENT
Power consumption of the LMK03806 can be high enough to
require attention to thermal management. For reliability and
performance reasons the die temperature should be limited
to a maximum of 125 °C. That is, as an estimate, TA (ambient
temperature) plus device power consumption times θJA
should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to a printed circuit board. To maximize the removal
of heat from the package a thermal land pattern including
multiple vias to a ground plane must be incorporated on the
PCB within the footprint of the package. The exposed pad
must be soldered down to ensure adequate heat conduction
out of the package.
A recommended land and via pattern is shown in Figure 14.
More information on soldering LLP packages and gerber footprints can be obtained: http:// www.national.com/analog/
packaging/.
A recommended footprint including recommended solder
mask and solder paste layers can be found at: http://
www.national.com/analog/packaging/gerber for the SQA64
package.
30170173
FIGURE 14. Recommended Land and Via Pattern
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36
LMK03806
17.0 Physical Dimensions inches (millimeters) unless otherwise noted
18.0 Ordering Information
Order Number
Packaging
LMK03806BISQE
250 Unit Tape and Reel
LMK03806BISQ
1000 Unit Tape and Reel
LMK03806BISQX
2500 Unit Tape and Reel
37
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