AD ADF7012BRU

Multichannel ISM Band
FSK/GFSK/OOK/GOOK/ASK Transmitter
ADF7012
FEATURES
GENERAL DESCRIPTION
Single-chip, low power UHF transmitter
75 MHz to 1 GHz frequency operation
Multichannel operation using Frac-N PLL
2.3 V to 3.6 V operation
On-board regulator—stable performance
Programmable output power:
−16 dBm to +14 dBm, 0.4 dB steps
Data rates: dc to 179.2 kbps
Low current consumption:
868 MHz, 10 dBm, 21 mA
433 MHz, 10 dBm, 17 mA
315 MHz, 0 dBm, 10 mA
Programmable low battery voltage indicator
24-lead TSSOP
The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK
UHF transmitter designed for short range devices (SRDs). The
output power, output channels, deviation frequency, and modulation type are programmable by using four, 32-bit registers.
The fractional-N PLL and VCO with external inductor enable
the user to select any frequency in the 75 MHz to 1 GHz band.
The fast lock times of the fractional-N PLL make the ADF7012
suitable in fast frequency hopping systems. The fine frequency
deviations available and PLL phase noise performance facilitates
narrow-band operation.
There are five selectable modulation schemes: binary frequency
shift keying (FSK), Gaussian frequency shift keying (GFSK),
binary on-off keying (OOK), Gaussian on-off keying (GOOK),
and amplitude shift keying (ASK). In the compensation register,
the output can be moved in <1 ppm steps so that indirect compensation for frequency error in the crystal reference can be
made.
APPLICATIONS
Low cost wireless data transfer
Security systems
RF remote controls
Wireless metering
Secure keyless entry
A simple 3-wire interface controls the registers. In power-down,
the part has a typical quiescent current of <0.1 μA.
FUNCTIONAL BLOCK DIAGRAM
CREG
PRINTED
INDUCTOR
OSC1
OSC2
CLKOUT CPVDD CPGND
L1
L2
CVCO
VDD
OOK\ASK
÷CLK
VCO
PA
÷R
PFD/
CHARGE
PUMP
DVDD
RFOUT
RF GND
DGND
CREG
OOK\ASK
+FRACTIONAL N
FSK\GFSK
Σ-∆
LDO
REGULATOR
TxCLK
PLL LOCK
DETECT
LE
DATA
SERIAL
INTERFACE
CLK
CE
FREQUENCY
COMPENSATION
MUXOUT
MUXOUT
BATTERY
MONITOR
CENTER
FREQUENCY
AGND
RSET
04617-0-001
TxDATA
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADF7012
TABLE OF CONTENTS
Specifications..................................................................................... 3
GOOK Modulation .................................................................... 15
Timing Characteristics..................................................................... 5
Output Divider ........................................................................... 16
Absolute Maximum Ratings............................................................ 6
MUXOUT Modes....................................................................... 16
Transistor Count........................................................................... 6
Theory of Operation ...................................................................... 17
ESD Caution.................................................................................. 6
Choosing the External Inductor Value.................................... 17
Pin Configuration and Function Descriptions............................. 7
Choosing the Crystal/PFD Value............................................. 17
Typical Performance Characteristics ............................................. 8
Tips on Designing the Loop Filter ........................................... 17
315 MHz ........................................................................................ 8
PA Matching................................................................................ 18
433 MHz ........................................................................................ 9
Transmit Protocol and Coding Considerations ..................... 18
868 MHz ...................................................................................... 10
Application Examples .................................................................... 19
915 MHz ...................................................................................... 11
315 MHz Operation ................................................................... 20
Circuit Description......................................................................... 12
433 MHz Operation ................................................................... 21
PLL Operation ............................................................................ 12
868 MHz Operation ................................................................... 22
Crystal Oscillator........................................................................ 12
915 MHz Operation ................................................................... 23
Crystal Compensation Register................................................ 12
Register Descriptions ..................................................................... 24
Clock Out Circuit ....................................................................... 12
R Register..................................................................................... 24
Loop Filter ................................................................................... 13
N-Counter Latch ........................................................................ 25
Voltage-Controlled Oscillator (VCO) ..................................... 13
Modulation Register .................................................................. 26
Voltage Regulators...................................................................... 13
Function Register ....................................................................... 27
FSK Modulation.......................................................................... 13
Outline Dimensions ....................................................................... 28
GFSK Modulation ...................................................................... 14
Ordering Guide .......................................................................... 28
Power Amplifier.......................................................................... 14
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADF7012
SPECIFICATIONS
DVDD = 2.3 V – 3.6 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +85°C.
Table 1.
Parameter
RF OUTPUT CHARACTERISTICS
Operating Frequency
Phase Frequency Detector
MODULATION PARAMETERS
Data Rate FSK/GFSK
Data Rate ASK/OOK
Deviation FSK/GFSK
GFSK BT
ASK Modulation Depth
OOK Feedthrough (PA Off)
POWER AMPLIFIER PARAMETERS
Max Power Setting, DVDD = 3.6 V
Max Power Setting, DVDD = 3.0 V
Max Power Setting, DVDD = 2.3 V
Max Power Setting, DVDD = 3.6 V
Max Power Setting, DVDD = 3.0 V
Max Power Setting, DVDD = 2.3 V
PA Programmability
POWER SUPPLIES
DVDD
Current Comsumption
315 MHz, 0 dBm/5 dBm
433 MHz, 0 dBm/10 dBm
868 MHz, 0 dBm/10 dBm/14 dBm
915 MHz, 0 dBm/10 dBm/14 dBm
VCO Current Consumption
Crystal Oscillator Current Consumption
Regulator Current Consumption
Power-Down Current
REFERENCE INPUT
Crystal Reference Frequency
Single-Ended Reference Frequency
Crystal Power-On Time 3.4 MHz/26 MHz
Single-Ended Input Level
B Version
Unit
Conditions/Comments
75/1000
MHz min/max
VCO range adjustable using external inductor;
divide-by-2, -4, -8 options may be required
FRF/128
Hz min
179.2
64
kbps
Kbps
PFD/214
511 × PFD/214
0.5
25
−40
−80
Hz min
Hz max
typ
dB max
dBm typ
dBm typ
FRF = Fvco
FRF = Fvco/2
14
13.5
12.5
14.5
14
13
0.4
dBm
dBm
dBm
dBm
dBm
dBm
dB typ
FRF = 915 MHz, PA is matched into 50 Ω
FRF = 915 MHz, PA is matched into 50 Ω
FRF = 915 MHz, PA is matched into 50 Ω
FRF = 433 MHz, PA is matched into 50 Ω
FRF = 433 MHz, PA is matched into 50 Ω
FRF = 433 MHz, PA is matched into 50 Ω
PA output = −20 dBm to +13 dBm
2.3/3.6
V min/V max
8/14
10/18
14/21/32
16/24/35
1/8
190
280
0.1/1
mA typ
mA typ
mA typ
mA typ
mA min/max
µA typ
µA typ
µA typ/max
3.4/26
MHz min/max
3.4/26
1.8/2.2
CMOS Levels
MHz min/max
ms typ
Using 1 MHz loop bandwidth
Based on US FCC 15.247 specfications for ACP; higher
data rates are achievable depending on local regulations
For example, 10 MHz PFD – deviation min = ± 610 Hz
For example, 10 MHz PFD – deviation max = ± 311.7 kHz
DVDD = 3.0 V, PA is matched into 50 Ω, IVCO = min
VCO current consumption is programmable
CE to Clock Enable Valid
Refer to the LOGIC INPUTS parameter. Applied to OSC 2 –
oscillator circuit disabled.
Rev. 0 | Page 3 of 28
ADF7012
Parameter
PHASE-LOCKED LOOP PARAMETERS
VCO Gain
315MHz
433MHz
868MHz
B Version
Unit
Conditions/Comments
22
24
80
MHz/V typ
MHz/V typ
MHz/V typ
VCO divide-by-2 active
VCO divide-by-2 active
88
0.3/2.0
−65/−70
MHz/V typ
V min/max
dBc
IVCO is programmable
0.3
0.9
1.5
2.1
mA typ
mA typ
mA typ
mA typ
Refering to DB[7:6] in Function Register
Refering to DB[7:6] in Function Register
Refering to DB[7:6] in Function Register
Refering to DB[7:6] in Function Register
−85
−83
−80
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA
PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA
PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA
915MHz
Phase Noise (Out of Band)1
315MHz
433MHz
−80
dBc/Hz typ
PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA
−103
−104
dBc/Hz typ
dBc/Hz typ
PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA
PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA
868MHz
915MHz
Harmonic Content (Second)2
Harmonic Content (Third)2
−115
−114
−20
−30
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA
PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA
FRF = FVCO
Harmonic Content (Others)2
Harmonic Content (Second)2
Harmonic Content (Third)2
−27
−24
−14
dBc typ
dBc typ
dBc typ
Harmonic Content (Others)2
−19
dBc typ
LOGIC INPUTS
Input High Voltage,VINH
0.7 × DVDD
V min
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
0.2 × DVDD
±1
4.0
V max
µA max
pF max
915MHz
VCO Tuning Range
Spurious (IVCO Min/Max)
Charge Pump Current
Setting [00]
Setting [01]
Setting [10]
Setting [11]
Phase Noise (In band)1
315MHz
433MHz
868MHz
LOGIC OUTPUTS
Output High Voltage, VOH
Output High Current, IOH,
Output Low Voltage, VOL
1
2
FRF = FVCO/N (where N = 2, 4, 8)
DVDD − 0.4
V min
CMOS output chosen
500
0.4
µA max
V max
IOL = 500 µA
Measurements made with NFRAC = 2048.
Measurements made without harmonic filter.
Rev. 0 | Page 4 of 28
ADF7012
TIMING CHARACTERISTICS
DVDD = 3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
Data-to-clock setup time
Data-to-clock hold time
Clock high duration
Clock low duration
Clock –to-LE setup time
LE pulse width
t4
t5
CLOCK
t2
DATA
DB23 (MSB)
t3
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
LE
t1
04617-0-002
t6
LE
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 28
ADF7012
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
DVDD to GND
(GND = AGND = DGND = 0 V)
Digital I/O Voltage to GND
Analog I/O Voltage to GND
Operating Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +3.9 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
150°C
150.4°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of 1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
215°C
220°C
TRANSISTOR COUNT
35819 (CMOS)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 28
ADF7012
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD 1
24
CREG2
CREG1 2
23
RSET
CPOUT 3
22
AGND
21
DVDD
20
RFOUT
TxDATA 4
TxCLK 5
TSSOP
ADF7012
19 RFGND
TOP VIEW
DGND 7 (Not to Scale) 18 VCOIN
OSC1 8
17
CVCO
OSC2 9
16
L2
CLKOUT 10
15
L1
CLK 11
14
CE
DATA 12
13
LE
04617-0-003
MUXOUT 6
Figure 3.
Table 4. Pin Functional Descriptions
Pin No.
1
Mnemonic
DVDD
2
CREG1
3
CPOUT
4
5
TxDATA
TxCLK
6
MUXOUT
7
8
9
DGND
OSC1
OSC2
10
CLKOUT
11
CLK
12
DATA
13
LE
14
CE
15
L1
16
17
L2
CVCO
18
VCOIN
19
20
RFGND
RFOUT
21
DVDD
22
23
24
AGND
RSET
CREG2
Description
Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin.
A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor
improves regulator power-on time, but may cause higher spurious noise.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
Digital Data to Be Transmitted is inputted on this pin.
GFSK and GOOK only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the
ADF7012. The clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on
the falling edge of TxCLK. The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit.
Provides the Lock_Detect Signal. This determines if the PLL is locked to the correct frequency and also monitors
battery voltage. Other signals include Regulator_Ready, which indicates the status of the serial interface regulator.
Ground for Digital Section.
The reference crystal should be connected between this pin and OSC2.
The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving
this pin with CMOS levels, and powering down the crystal oscillator bit in software.
A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive
several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1uA. Register values are
lost when CE is low and the part must be reprogrammed once CE is brought high.
Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the
value of the inductor to be connected between L1 and L2.
Connected to external printed or discrete inductor.
A 220 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7012.
This capacitor is necessary to ensure stable VCO operation.
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The
higher the tuning voltage, the higher the output frequency.
Ground for Output Stage of Transmitter.
The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output
should be impedance matched using suitable components to the desired load. See the PA Matching section.
Voltage supply for VCO and PA section. This should have the same supply as DVDD Pin 1, and should be between
2.3 V and 3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin.
Ground Pin for the RF Analog Circuitry.
External Resistor to set charge pump current and some internal bias currents. Use 3.6 kV as default.
Add a 470 nF capacitor at CREG to reduce regulator noise and improve stability. A reduced capacitor improves
regulator power-on time and phase noise, but may have stability issues over the supply and temperature.
Rev. 0 | Page 7 of 28
ADF7012
TYPICAL PERFORMANCE CHARACTERISTICS
315 MHZ
–60
–70
5
0
–80
A
3
–20
–30
–100
–110
–50
–120
–60
–70
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
1 [T1]
2 [T1]
–90
–95
10.0M
CENTER 3.5MHz
Figure 4. Phase Noise Response—DVDD = 3.0 V, ICP = 0.86 mA
IVCO = 2.0 mA, FOUT = 315 MHz, PFD = 3.6864 MHZ, PA Bias = 5.5 mA
REF LVL
5dBm
5
0
1
2
5
0
–10
–10
–20
–20
1MA
–40
–50
–50
–60
–60
–70
–70
1
A
SGL
1MA
3
04617-0-005
CENTER 315MHz
50kHz/
4
–80
2 [T1]
–90
–95
SPAN 500kHz
5
0
REF LVL
5dBm
4 [T1]
–42.93dBm
939.87975952MHz
–55.48dBm
1.26252505GHz
SPAN 7GHz
700MHz/
RBW
20.33dBm VBW
26.55310621kHz SWT
5
0
A
–10
5kHz RF ATT 30dB
5kHz
dBm
500ms UNIT
A
1
–10
–20
–20
1MA
D1 –41.5dBm
–40
D2 –49dBm
–50
–60
–60
–70
–70
1 [T1]
04617-0-006
–80
0.31dBm
315.40080160MHz
CENTER 315MHz
40MHz/
2
3
–30
–80
–90
–95
SPAN 400MHz
1MA
1 [T1]
3 [T1]
2 [T1]
–3.49dBm
315.00012525MHz
–20.33dB
26.55310621kHz
–20.85dB
–27.55511022kHz
CENTER 315MHz
Figure 6. Spurious Components—Meets FCC Specs
50kHz/
04617-0-009
–30
–90
–95
3 [T1]
Figure 8. Harmonic Response, Fifth-Order Butterworth Filter
RBW 500kHz RF ATT 30dB
0.31dBm VBW 500kHz
315.40080160MHz SWT
dBm
5ms UNIT
1
0.18dBm
308.61723447MHz
–50.53dBm
631.26252505MHz
CENTER 3.5MHz
Figure 5. FSK Modulation, Power = 0 dBm, Data Rate = 1 kbps,
FDEVIATION = ±50 kHz
REF LVL
5dBm
D1 –41.5dBm
2
1 [T1]
–90
–95
SPAN 7GHz
–30
–40
–80
700MHz/
–11.48dBm
939.87975952MHz
–34.11dBm
1.26252505GHz
RBW
1MHz RF ATT 30dB
0.18dBm VBW
1MHz
308.61723447MHz SWT 17.5ms UNIT
dBm
REF LVL
5dBm
A
–30
4 [T1]
Figure 7. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
5kHz RF ATT 30dB
5kHz
dBm
500ms UNIT
RBW
0.45dBm VBW
315.05060120MHz SWT
3 [T1]
0.27dBm
308.61723447MHz
–35.43dBm
631.26252505MHz
–80
04617-0-007
–140
1.0k
D1 –41.5dBm
04617-0-008
–130
–50
1MA
4
2
–40
04617-0-004
dBc (Hz)
1
–10
–90
–40
RBW
1MHz RF ATT 30dB
0.27dBm VBW
1MHz
308.61723447MHz SWT 17.5ms UNIT
dBm
REF LVL
5dBm
= NORMAL
FREQUENCY = 9.08 kHz
LEVEL = –84.47dBc/Hz
SPAN 500kHz
Figure 9. OOK Modulation, Power = 0 dBm, Data Rate = 10 kbps
Rev. 0 | Page 8 of 28
ADF7012
433 MHZ
1 2.00V/ 2 1.00V/
1.50ms 500µs TRIG'D
1 720mv
RBW
10.01dBm VBW
433.91158317MHz SWT
REF LVL
15dBm
15
10
30kHz RF ATT 40dB
30kHz
dBm
90ms UNIT
1
A
0
–10
–20
2 CLKOUT
1MA
–30
D1 –36dBm
–40
–50
–60
04617-0-010
–70
04617-0-013
1 CE
–80
–85
CENTER 433.9500601MHz 3.2MHz/
Figure 10. Crystal Power-On Time, 4 MHz, Time = 1.6 ms
Figure 13. Spurious Components—Meets ETSI Specs
–40
15
10
–80
1
A
0
3
–10
–100
2
4
–20
1MA
–120
–30
–140
–40
–160
–50
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
1 [T1]
2 [T1]
–80
–85
10.0M
CENTER 3.5GHz
Figure 11. Phase Noise Response—ICP = 2.0 mA, IVCO = 2.0 mA,
RFOUT = 433.92 MHz, PFD = 4 MHz, PA Bias = 5.5 mA
REF LVL
15dBm
15
10
RBW 10kHz RF ATT 40dB
5.60dBm VBW 300kHz
433.91158317MHz SWT
dBm
44ms UNIT
15
10
0
0
–10
–20
–30
–30
D1 –36dBm
1
A
SGL
1MA
2
–50
–60
–60
–70
–70
04617-0-012
1 [T1]
174kHz/
2 [T1]
–80
–85
STOP 434.79kHz
D1 –30dBm
3
–40
–50
START 433.05MHz
SPAN 7GHz
–20
1MA
–80
–85
700MHz/
–5.12dBm
1.30460922GHz
–17.57dBm
1.73947896GHz
RBW
1MHz RF ATT 40dB
9.51dBm VBW
1MHz
434.86973948MHz SWT 17.5ms UNIT
dBm
REF LVL
15dBm
A
1
3 [T1]
4 [T1]
Figure 14. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
–10
–40
10.10dBm
434.86973948MHz
–15.25dBm
869.73947896MHz
–70
04617-0-014
–200
1.0k
D1 –36dBm
9.51dBm
434.86973948MHz
–33.75dBm
869.73947896MHz
CENTER 3.5GHz
Figure 12. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps, FDEVIATION
= ±19.28 kHz
Rev. 0 | Page 9 of 28
D1 –36dBm
4
3 [T1]
4 [T1]
700MHz/
–43.60dBm
1.30460922GHz
–43.44dBm
1.73947896GHz
04617-0-015
–180
D1 –30dBm
–60
04617-0-011
dBc (Hz)
RBW
1MHz RF ATT 40dB
10.10dBm VBW
1MHz
434.86973948MHz SWT 17.5ms UNIT
dBm
REF LVL
15dBm
= NORMAL
FREQUENCY = 393.38 kHz
LEVEL = –102.34dBc/Hz
–60
SPAN 32MHz
SPAN 7GHz
Figure 15. Harmonic Response, Fifth-Order Butterworth Filter
ADF7012
868 MHZ
0
15
10
–40
dBc (Hz)
–80
3
4
1MAX
1MA
–30
–100
–40
–120
–50
–160
1.0k
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
1 [T1]
–70
10.0M
15
10
12.27dBm
869.33867735MHz
–4.00dBm
1.72865731GHz
2 [T1]
–80
–85
CENTER 3.8GHz
Figure 16. Phase Noise Response–ICP = 2.5 mA, IVCO = 1.44 mA, RFOUT = 868.95
MHz, PFD = 4.9152 MHz, Power = 12.5 dBm, PA Bias = Max
REF LVL
15dBm
D1 –30dBm
–60
04617-0-016
–140
30dB
RBW 10kHz RF ATT
–40.44dBm VBW 10kHz MIXER –20dBm
869.20000000MHz SWT 15ms UNIT
dBm
2
15
10
A
LN
640MHz/
1
1 [T1]
3 [T1]
2 [T1]
–10
–20 1MAX
1MA
–20
–30
–30
D2 –36dBm
–40
1
–16.88dBm
2.59699399GHz
–15.06dBm
3.46913828GHz
SPAN 6.4GHz
30dB
RBW 1kHz RF ATT
10.39dBm VBW 1kHz MIXER –20dBm
869.33867735MHz SWT 10ms UNIT
dBm
0
–10
3 [T1]
4 [T1]
Figure 19. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
REF LVL
15dBm
0
10.39dBm
869.33867735MHz
–50.92dBm
1.72000000GHz
–50.40dBm
2.59600000GHz
1MAX
A
LN
1MA
D2 –30dBm
–40
–50
–50
–60
2
3
–60
2 [T1]
–80
–85
CENTER 868.944489MHz
–70
60kHz/
–80
–85
SPAN 600kHz
START 3.8GHz
Figure 17. FSK Modulation, Power = 12.5 dBm, Data Rate = 38.4 kbps,
FDEVIATION = ±19.2 kHz
REF LVL
15dBm
RBW
12.55dBm VBW
869.025050100MHz SWT
15
10
1
1 [T1]
0
2 [T1]
–10
3 [T1]
30dB
2kHz RF ATT
2kHz MIXER –20dBm
dBm
16s UNIT
12.55dBm
869.02505010MHz
–57.89dBm
859.16695500MHz
–81.97dBm
862.00000000MHz
–20 1MAX
A
LN
1MA
–30
D2 –36dBm
–40
2
D1 –54dBm
–60
04617-0-018
–70
3
START 856.5MHz
2.5MHz/
04617-0-020
–70
40.44dBm
869.20000000MHz
8.02dBm
868.96673347MHz
04617-0-017
1 [T1]
–80
–85
A
2
0
–20
–50
1
–10
–60
1MHz RF ATT 40dB
1MHz
dBm
16ms UNIT
04617-0-019
–20
RBW
12.27dBm VBW
869.33867735MHz SWT
REF LVL
15dBm
= NORMAL
FREQUENCY = 251.3 kHz
LEVEL = –99.39dBc/Hz
STOP 881.5MHz
Figure 18. Spurious Components—Meets ETSI Specs
Rev. 0 | Page 10 of 28
640MHz/
SPAN 6.4GHz
Figure 20. Harmonic Response, Fifth-Order Chebyshev Filter
ADF7012
915 MHZ
RBW 50MHz RF ATT 40dB
10.25dBm VBW 50MHz
907.81563126MHz SWT
dBm
6.4s UNIT
–40
REF LVL
15dBm
= NORMAL
FREQUENCY = 992.38 kHz
LEVEL = –102.34dBc/Hz
–60
15
10
–80
0
2
–10
–100
–20
3
1MAX
4
1MA
–120
–30
–140
–40
–160
D1 –41.5dBm
04617-0-021
–50
–200
1.0k
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
–60
1 [T1]
–70
10.0M
2 [T1]
–80
–85
10.25dBm
907.81563126MHz
–10.06dBm
1.83126253GHz
CENTER 3.8GHz
Figure 21. Phase Noise Response–ICP = 1.44 mA, IVCO = 3.0 mA, RFOUT = 915.2
MHz, PFD =10 MHz, Power = 10 dBm, PA Bias = 5.5 mA
REF LVL
15dBm
15
10
RBW 10kHz RF ATT 40dB
3.88dBm VBW 300kHz
915.19098196MHz SWT 15ms UNIT
dBm
15
10
0
1MA
–20
–30
–30
–40
–40
–50
–50
RBW 50MHz RF ATT 40dB
9.06dBm VBW 50MHz
907.81563126MHz SWT
dBm
6.4s UNIT
A
1
–60
–60
–70
–70
1MAX
1MA
2
04617-0-036
1 [T1]
–80
–85
CENTER 915.190982MHz
50kHz/
2 [T1]
–80
–85
REF LVL
15dBm
*
A
SGL
0
–10
1MA
–20
–30
D1 –41.5dBm
D1 –49.5dBm
–60
04617-0-037
–70
–80
–85
CENTER 915.2MHz
40MHz/
D1 –41.5dBm
4
3 [T1]
4 [T1]
640MHz/
–46.22dBm
2.74188377GHz
–46.96dBm
3.65250501GHz
SPAN 6.4GHz
Figure 25. Harmonic Response, Fifth-Order Chebyshev Filter
RBW 10kHz RF ATT 40dB
9.94dBm VBW 300kHz
915.23167977MHz SWT 100ms UNIT
dBm
1
3
9.06dBm
907.81563126MHz
–48.40dBm
1.83126253GHz
CENTER 3.8GHz
SPAN 500kHz
Figure 22. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps,
Fdeviation = ±19.2 kHz
–50
SPAN 6.4GHz
–10
–20 1MAX
–40
640MHz/
0
–10
15
10
–20.29dBm
2.74188377GHz
–17.50dBm
3.65250501GHz
Figure 24. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
REF LVL
15dBm
A
1
3 [T1]
4 [T1]
04617-0-038
–180
04617-0-039
dBc (Hz)
A
1
SPAN 400MHz
Figure 23. Spurious Components—Meets FCC Specs
Rev. 0 | Page 11 of 28
ADF7012
CIRCUIT DESCRIPTION
PLL OPERATION
CRYSTAL/R
LOOP FILTER
R
PFD
VCO
FVCO
CP2
Figure 27.
Two parallel resonant capacitors are required for oscillation at
the correct frequency—the value of these depend on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds to give the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary between 2 pF to 5 pF, depending on board layout.
Where possible, to ensure stable frequency operation over all
conditions, capacitors should be chosen so that they have a very
low temperature coefficient and/or opposite temperature
coefficients
04617-0-022
FADJUST = FSTEP × FEC
Figure 26.
FCRYSTAL × N
= FPFD × N
R
CP1
The ADF7012 features a 15-bit fixed modulus, which allows the
output frequency to be adjusted in steps of FPFD/15. This fine
resolution can be used to easily compensate for initial error and
temperature drift in the reference crystal.
VCO/N
FOUT =
OSC2
CRYSTAL COMPENSATION REGISTER
CP
N
OSC1
04617-0-023
A fractional-N PLL allows multiple output frequencies to be
generated from a single-reference oscillator (usually a crystal)
simply by changing the programmable N value found in the N
register. At the phase frequency detector (PFD), the reference is
compared to a divided-down version of the output frequency
(VCO/N). If VCO/N is too low a frequency, typically the output
frequency is lower than desired, and the PFD and charge-pump
combination sends additional current pulses to the loop filter.
This increases the voltage applied to the input of the VCO.
Because the VCO of the ADF7012 has a positive frequency vs.
voltage characteristic, any increase in the Vtune voltage applied
to the VCO input increases the output frequency at a rate of kV,
the tuning sensitivity of the VCO (MHz/V). At each interval of
1/PFD seconds, a comparison is made at the PFD until the PFD
and charge pump eventually force a state of equilibrium in the
PLL where PFD frequency = VCO/N. At this point, the PLL can
be described as locked.
(1)
(3)
where FSTEP = FPFD/215 and FEC = Bits F1 to F11 in the R
Register. Note that the notation is twos compliment, so F11
represents the sign of the FEC number.
where NFRAC can be bits M1 to M12 in the fractional N register.
Example
FPFD = 10 MHz
FADJUST = −11 kHz
FSTEP = 10 MHz/215 = 305.176 Hz
FEC = −11 kHz/305.17 Hz = −36 = −(00000100100) =
11111011100 = 0x7DC
CRYSTAL OSCILLATOR
CLOCK OUT CIRCUIT
The on-board crystal oscillator circuitry (Figure 27) allows an
inexpensive quartz crystal to be used as the PLL reference. The
oscillator circuit is enabled by setting XOEB low. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the error correction
register within the R register.
The clock out circuit takes the reference clock signal from the
oscillator section above and supplies a divided-down 50:50
mark-space signal to the CLKOUT pin. An even divide from
2 to 30 is available. This divide is set by the DB[19:22] in the R
register. On power-up, the CLKOUT defaults to divide by 16.
N
⎛
⎞
FOUT = FPFD × ⎜ N INT + FRAC
12 ⎟
2 ⎠
⎝
(2)
DVDD
CLKOUT
ENABLE BIT
A single-ended reference may be used instead of a crystal, by
applying a square wave to the OSC2 pin, with XOEB set high.
OSC1
DIVIDER
1 TO 15
÷2
Figure 28.
Rev. 0 | Page 12 of 28
CLKOUT
04617-0-024
For a Fractional N PLL
ADF7012
The output buffer to CLKOUT is enabled by setting Bit DB4 in
the function register high. On power-up, this bit is set high.
The output buffer can drive up to a 20 pF load with a 10% rise
time at 4.8 MHz. Faster edges can result in some spurious
feedthrough to the output. A small series resistor (50 Ω) can be
used to slow the clock edges to reduce these spurs at FCLK.
LOOP FILTER
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 29.
CHARGE
PUMP OUT
VCO
04617-0-025
In FSK, the loop should be designed so that the loop bandwidth
(LBW) is a minimum of two to three times the data rate.
Widening the LBW excessively reduces the time spent jumping
between frequencies, but results in reduced spurious
attenuation. See the section Tips on Designing the Loop Filter.
For OOK/ASK systems, a wider loop bandwidth than for FSK
systems is desirable. The sudden large transition between two
power levels results in VCO pulling (VCO temporarily goes to
incorrect frequency) and can cause a wider output spectrum.
By widening the loop bandwidth a minimum of 10 × data rate,
VCO pulling is minimized because the loop settles quickly back
to the correct frequency. The free design tool ADIsimPLL™ can
be used to design loop filters for the ADI family of transmitters.
VOLTAGE-CONTROLLED OSCILLATOR (VCO)
The ADF7012 features an on-chip VCO with an external tank
inductor, which is used to set the frequency range. The center
frequency of oscillation is governed by the internal varactor
capacitance and that of the external inductor combined with the
bond-wire inductance. An approximation for this is given in the
Equation 4. For a more accurate selection of the inductor, see
the section Choosing the External Inductor Value.
1
2π ( LINT + LEXT ) × (CVAR + CFIXED )
VCO Bias Current
VCO bias current may be adjusted using bits VB1 to VB4 in the
function register. Additional bias current will reduce spurious
levels, but increase overall current consumption in the part. A
bias value of 0x5 should ensure oscillation at most frequencies
and supplies. Settings 0x0, 0xE ,and 0xF are not recommended.
Setting 0x3 and Setting 0x4 are recommended under most
conditions. Improved phase noise can be achieved for lower
bias currents.
VOLTAGE REGULATORS
Figure 29.
FVCO =
Figure 32 shows the VCO gain over temperature and frequency.
VCO gain is important in determining the loop filter design—
predictable changes in VCO gain resulting in a change in the
loop filter bandwidth can be offset by changing the chargepump current in software.
(4)
The varactor capacitance can be adjusted in software to increase
the effective VCO range by writing to bits VA1 and VA2 in the
R register. Under typical conditions, setting VA1 and VA2 high
increases the center frequency by reducing the varactor
capacitance by approximately 1.3 pF.
There are two band gap voltage regulators on the ADF7012
providing a stable 2.25 V internal supply: a 2.2 µF capacitor
(X5R, NP0) to ground at CREG1 and a 470 nF capacitor at CREG2
should be used to ensure stability. The internal reference
ensures consistent performance over all supplies and reduces
the current consumption of each of the blocks.
The combination of regulators, band gap reference, and biasing
typically consume 1.045 mA at 3.0 V and can be powered down
by bringing the CE line low. The serial interface is supplied by
Regulator 1, so powering down the CE line causes the contents
of the registers to be lost. The CE line must be high and the
regulators must be fully powered on to write to the serial
interface. Regulator power-on time is typically 100 µs and
should be taken into account when writing to the ADF7012
after power-up. Alternatively, regulator status may be monitored
at the MUXOUT pin once CE has been asserted, because
MUXOUT defaults to the regulator ready signal. Once
Regulator_ready is high, the regulator is powered up and the
serial interface is active.
FSK MODULATION
FSK modulation is performed internally in the PLL loop by
switching the value of the N register based on the status of the
TxDATA line. The TxDATA line is sampled at each cycle of the
PFD block (every 1/FPFD seconds). When TxDATA makes a lowto-high transition, an N value representing the deviation
frequency is added to the N value representing the center
frequency. Immediately the loop begins to lock to the new
frequency of FCENTER + FDEVIATION. Conversely, when TxDATA
makes a high-to-low transition, the N value representing the
deviation is subtracted from the PLL N value representing the
center frequency and the loop transitions to FCENTER − FDEVIATION.
Rev. 0 | Page 13 of 28
ADF7012
PFD/
CHARGE
PUMP
PA STAGE
VCO
FSK DEVIATION
FREQUENCY
–FDEV
THIRD-ORDER
Σ-∆ MODULATOR
+FDEV
TxDATA
FRACTIONAL-N
INTEGER-N
04617-0-026
÷N
Figure 30.
The deviation from the center frequency is set using bits D1 to
D9 in the modulation register. The frequency deviation may be
set in steps of
FSTEP ( Hz) =
FPFD
214
FPFD × ModulationNumber
214
TxDATA
INT
TxCLK
ADF7012
FETCH
FETCH
FETCH
SAMPLE SAMPLE
FETCH
SAMPLE
Figure 31. TxCLK/TxDATA Synchronization.
(5)
The number of steps between symbol ‘0’ and symbol ‘1’ is
determined by the setting for the index counter.
The deviation frequency is therefore
FDEVIATION ( Hz) =
I/O
µC
04617-0-040
4R
For GFSK and GOOK, the incoming bit stream to be transmitted needs to be synchronized with an on-chip sampling
clock which provides one sample per bit to the Gaussian FIR
filter. To facilitate this, the sampling clock is routed to the
TxCLK pin where data is fetched from the host microcontroller
or microprocessor on the falling edge of TxCLK, and the data is
sampled at the midpoint of each bit on TxCLK’s rising edge.
Inserting external RC LPFs on TxDATA and TxCLK lines
creates smoother edge transitions and improves spurious
performance. As an example, suitable components would be a
1 kV resistor and 10 nF capacitor for a data rate of 5 kbps.
(6)
The GFSK deviation is set up as
GFSK DEVIATION ( Hz) =
where ModulationNumber is set by bits D1 to D9.
FPFD × 2 m
212
(7)
The maximum data rate is a function of the PLL lock time (and
the requirement on FSK spectrum). Because the PLL lock time
is reduced by increasing the loop-filter bandwidth, highest data
rates can be achieved for the wider loop filter bandwidths. The
absolute maximum limit on loop filter bandwidth to ensure
stability for a fractional-N PLL is FPFD/7. For a 20 MHz PFD
frequency, the loop bandwidth could be as high as 2.85 MHz.
FSK modulation is selected by setting bits S1 and S2 in the
modulation register low.
where DividerFactor can be bits D1 to D7, and IndexCounter
can be bits IC1 and IC2 in the modulation register.
GFSK MODULATION
POWER AMPLIFIER
Gaussian Frequency Shift Keying, or GFSK, represents a filtered
form of frequency shift keying. The data to be modulated to RF
is prefiltered digitally using an finite impulse response filter
(FIR). The filtered data is then used to modulate the sigmadelta fractional-N to generate spectrally-efficient FSK.
The output stage is based on a Class E amplifier design, with an
open drain output switched by the VCO signal. The output
control consists of six current mirrors operating as a
programmable current source.
FSK consists of a series of sharp transitions in frequency as the
data is switched from one level to an other. The sharp switching
generates higher frequency components at the output, resulting
in a wider output spectrum.
With GFSK, the sharp transitions are replaced with up to 128
smaller steps. The result is a gradual change in frequency. As a
result, the higher frequency components are reduced and the
spectrum occupied is reduced significantly. GFSK does require
some additional design work as the data is only sampled once
per bit, and so the choice of crystal is important to ensure the
correct sampling clock is generated.
where m is the mod control (Bits MC1 to MC3 in the
modulation register).
The GFSK sampling clock samples data at the data rate:
DataRate (bps) =
FPFD
DividerFactor × IndexCounter
(8)
To achieve maximum voltage swing, the RFOUT pin needs to be
biased at DVDD. A single pull-up inductor to DVDD ensures a
current supply to the output stage, PA biased to DVDD volts, and
with the correct choice of value transforms the impedance.
The output power can be adjusted by changing the value of
bits P1 to P6. Typically, this is P1 to P6 output −20dBm at 0x0,
and 13 dBm at 0x7E at 868MHz, with the optimum matching
network.
Rev. 0 | Page 14 of 28
ADF7012
The nonlinear characteristic of the output stage results in an
output spectrum containing harmonics of the fundamental,
especially the third and fifth. To meet local regulations, a lowpass filter usually is required to filter these harmonics.
As is the case with GFSK, GOOK requires the bit stream
applied at TxDATA to be synchronized with the sampling clock,
TxCLK (see the GFSK Modulation section).
10
The output stage can be powered down by setting Bit PD2 in
the function register low.
0
–10
OOK
GOOK MODULATION
–60
–70
–80
909.43
910.43
FREQUENCY (MHz)
10
0
–10
PRE-FILTER DATA
(0 TO 1 TRANSITION)
–20
–30
OOK
–40
–50
–60
–70
–80
–90
885.43
GOOK
910.43
FREQUENCY (MHz)
04617-0-041
Figure 34. GOOK vs. OOK Frequency Spectra
(Wideband Measurement)
Figure 32. Varying PA Output for GOOK (Index Counter = 16).
Rev. 0 | Page 15 of 28
04617-0-044
Figure 32 shows the step response of the Gaussian FIR filter.
An index counter of 16 is demonstrated for simplicity. While
the pre-filter data would switch the PA directly from off to on
with a low-to-high data transition, the filtered data gradually
increases the PA output in discrete steps. This has the effect of
making the output spectrum more compact.
DISCRETIZED
FILTER OUTPUT
910.93
20
Bits D1 to D6 represent the output power for the system for a
positive data bit. Divider Factor = 0x3F represents the maximum possible deviation from PA at minimum to PA at
maximum output. An index counter setting of 128 is
recommended.
PA SETTING
16 (MAX)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 (PA OFF)
GOOK
Figure 33. GOOK vs. OOK Frequency Spectra
(Narrow-Band Measurement)
(9)
POWER (dBm)
FPFD
DividerFactor × IndexCounter
–40
–50
The GOOK sampling clock samples data at the data rate:
DataRate (bps) =
–30
04617-0-043
Gaussian on-off keying (GOOK) represents a prefiltered form
of OOK modulation. The usually sharp symbol transitions are
replaced with smooth Gaussian-filtered transitions with the
result being a reduction in frequency pulling of the VCO.
Frequency pulling of the VCO in OOK mode can lead to a
wider than desired bandwidth, especially if it is not possible to
increase the loop filter bandwidth to > 300kHz.
POWER (dBm)
–20
935.93
ADF7012
OUTPUT DIVIDER
Battery Voltage Read back
An output divider is a programmable divider following the
VCO in the PLL loop. It is useful when using the ADF7012 to
generate frequencies of < 500 MHz.
By setting MUXOUT to 1010 to 1101, the battery voltage can be
estimated. The battery measuring circuit features a voltage
divider and a comparator where the divided-down supply
voltage is compared to the regulator voltage.
PFD
CP
LOOP
FILTER
VCO
OUTPUT
DIVIDER
PA
÷1/2/4/8
÷N
Table 6.
04617-0-042
REFERENCE
DIVIDER
Figure 35. Output Divider Location in PLL.
The output divider may be used to reduce feedthrough of the
VCO by amplifying only the VCO/2 component, restricting the
VCO feedthrough to leakage.
Because the divider is in loop, the N register values should be
set up according to the usual formula. However, the VCO gain
(KV) should be scaled according to the divider setting, as shown
in the following example.
Fout = 433 MHz, Fvco = 866 MHz, KV @ 868 MHz =
60 MHz/V
The divider value is set in the R register.
Table 5.
OD2
0
1
0
1
MUXOUT High
DVDD > 3.25 V
DVDD > 3.0 V
DVDD > 2.75 V
DVDD > 2.35 V
MUXOUT Low
DVDD < 3.25 V
DVDD < 3.0 V
DVDD < 2.75 V
DVDD < 2.35 V
The accuracy of the measurement is limited by the accuracy of
the regulator voltage and also the internal resistor tolerances.
Regulator Ready
The regulator has a power-up time, dependant on process and
the external capacitor. The regulator ready signal indicates that
the regulator is fully powered, and that the serial interface is
active. This is the default setting on power-up at MUXOUT.
Digital Lock Detect
Therefore, KV for loop filter design = 30 MHz/V.
OD1
0
0
1
1
MUXOUT
1010
1011
1100
1101
Divider Status
Divider off
Divide by 2
Divide by 4
Divide by 8
MUXOUT MODES
The MUXOUT pin allows the user access to various internal
signals in the transmitter, and provides information on the
PLL lock status, the regulator, and the battery voltage. The
MUXOUT is accessed by programming Bits M1 to M4 in the
function register and observing the signal at the MUXOUT pin.
Digital lock detect indicates that the status of the PLL loop.
The PLL loop takes time to settle on power-up and when the
frequency of the loop is changed by changing the N value.
When lock detect is high, the PFD has counted a number of
consecutive cycles where the phase error is < 15 ns. The lock
detect precision bit in the function register determines whether
this is 3 cycles (LDP = 0), or 5 cycles (LDP=1). It is recommended that LDP be set to 1. The lock detect is not completely
accurate and goes high before the output has settled to exactly
the correct frequency. In general, add 50% to the indicated
lock time to obtain lock time to within 1 kHz. The lock detect
signal can be used to decide when the power amplifier (PA)
should be enabled.
R Divider
MUXOUT provides the output of the R divider. This is a
narrow pulsed digital signal at frequency FPFD. This signal may
be used to check the operation of the crystal circuit and the R
divider. R divider/2 is a buffered version of this signal at FPFD/2.
Rev. 0 | Page 16 of 28
ADF7012
THEORY OF OPERATION
CHOOSING THE EXTERNAL INDUCTOR VALUE
Standard Crystal Values
The ADF7012 allows operation at many different frequencies by
choosing the external VCO inductor to give the correct output
frequency. Figure 36 shows both the minimum and maximum
frequency vs. the inductor value. These are measurements based
on 0603 CS type inductors from Coilcraft, and are intended as
guidelines in choosing the inductor because board layout and
inductor type varies between applications.
Standard crystal values are 3.6864 MHz, 4 MHz, 4.096 MHz,
4.9152 MHz, 7.3728 MHz, 9.8304 MHz, 10 MHz, 11.0592 MHz,
12 MHz, and 14.4792 MHz. Crystals with these values are
usually available in stock and cost less than crystals with
nonstandard values.
The inductor value should be chosen so it is between the
minimum and maximum value.
1200
MIN (meas)
1100
MAX (meas)
MIN (eqn)
MAX (eqn)
Reference spurious levels (spurs) occur at multiples of the PFD
frequency. The reference spur closest to the carrier is usually
highest with the spur further out being attenuated by the loop
filter. The level of reference spur is lower for lower PFD
frequencies. In designs with high output power where spurious
levels are the main concern, a lower PFD frequency (<5 MHz)
may be desirable.
Beat Note Spurs
900
500
These are spurs occurring for very small or very large values in
the fractional register. These are quickly attenuated by the loop
filter. Selection of the PFD therefore determines their location,
and ensures that they have negligible effect on the transmitter
spectrum.
400
Phase Noise
800
700
600
04617-0-031
FREQUENCY (MHz)
1000
Reference Spurious Levels
300
0
5
10
15
20
INDUCTANCE (nH)
25
30
The phase noise of a frequency synthesizer improves by 3dB for
every doubling of the PFD frequency. Because ACP is related to
the phase noise, the PFD may be increased to reduce the ACP
in the system. PFD frequencies of < 5MHz typically deliver
sufficient phase noise performance for most systems.
35
Figure 36. Output Frequency vs. External Inductor Value
Ibias = 2.0 mA.
For frequencies between 270 MHz and 550 MHz, it is
recommended to operate the VCO at twice the desired output
frequency and use the divide-by-2 option. This ensures reliable
operation over temperature and supply.
For frequencies between 130 MHz and 270 MHz, it is
recommended to operate the VCO at four times the desired
output frequency and use the divide-by-4 option.
Deviation Frequency
The deviation frequency is adjustable in steps of
FSTEP ( Hz) =
FPFD
214
(10)
To get the exact deviation frequency required, ensure FSTEP is a
factor of the desired deviation.
For frequencies below 130 MHz, it is best to use the divide-by-8
option. It is not necessary to use the VCO divider for
frequencies above 550 MHz.
ADIsimPLL is a PLL design tool which can perform the
frequency calculations for the ADF7012, and is available at
www.analog.com/pll.
CHOOSING THE CRYSTAL/PFD VALUE
The choice of crystal value is an important one. The PFD
frequency must be the same as the crystal value or an integer
division of it. The PFD determines the phase noise, spurious
levels and location, deviation frequency, and the data rate in the
case of GFSK. The following sections describe some factors that
should be considered when choosing the crystal value.
TIPS ON DESIGNING THE LOOP FILTER
The loop filter design is crucial in ensuring stable operation of
the transmitter, meeting Adjacent Channel Power (ACP)
specifications, and meeting spurious requirements for the
relevant regulations. ADIsimPLL is a free tool available to aid
the design of loop filters. The user enters the desired frequency
range, the reference crystal and PFD values, and the desired
loop bandwidth. ADIsimPLL gives a good starting point for the
filter, and the filter can be further optimized based on the
criteria below.
Rev. 0 | Page 17 of 28
ADF7012
Setting Tuning Sensitivity Value
PA MATCHING
The tuning sensitivity or kV is usually denoted in MHz/V and is
required for the loop filter design. It refers to the amount that a
change of a volt in the voltage applied to VCOIN pin, changes
the output frequency. Typical data for the ADF7012 over a
frequency range is shown.
The ADF7012 exhibits optimum performance in terms of
transmit power and current consumption only if the RF output
port is properly matched to the antenna impedance.
120
100
KV (MHz/V)
80
ZOPT_PA depends primarily on the required output power,
and the frequency range. Selecting the optimum ZOPT_PA
helps to minimize the current consumption. This data sheet
contains a number of matching networks for common
frequency bands. Under certain conditions it is recommended
to obtain a suitable ZOPT_PA value by means of a load-pull
measurement.
60
DVDD
40
400
500
600
700
800
FREQUENCY (MHz)
900
1000
LPF
ZOPT_PA
1100
Figure 37. kV vs. VCO Frequency
Figure 38. ADF7012 with Harmonic Filter
Charge-Pump Current
The charge-pump current allows the loop filter bandwidth to be
changed using the registers. The loop bandwidth reduces as the
charge pump current is reduced and vice versa.
Selecting Loop Filter Bandwidth
Data Rate
The loop filter bandwidth should usually be at two to three
times the data rate. This ensures that the PLL has ample time
to jump between the mark and space frequencies.
The impedance matching values provided in the next section
are for 50 Ω environments. An additional matching network
may be required after the harmonic filter to match to the
antenna impedance. This can be incorporated into the filter
design itself in order to reduce external components.
TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
PREAMBLE
ACP
In the case where the ACP specifications are difficult to meet,
the loop filter bandwidth can be reduced further to reduce the
phase noise at the adjacent channel. The filter rolls off at 20 dB
per decade.
Spurious Levels
In the case where the output power is quite high, a reduced loop
filter bandwidth reduces the spurious levels even further, and
provides additional margin on the specification.
SYNC
WORD
ID
FIELD
DATA FIELD
CRC
04617-0-034
300
PA
ANTENNA
04716-0-033
0
200
RFOUT
004617-0-032
20
Figure 39. Typical Format of a Transmit Protocol
A dc-free preamble pattern such as 10101010… is recommended for FSK/ASK/OOK demodulation. Preamble patterns
with longer run-length constraints such as 11001100…. can also
be used. However, this can result in a longer synchronization
time of the received bit stream in the chosen receiver.
The following sections provide examples of loop filter designs
for typical applications in specific frequencies.
Rev. 0 | Page 18 of 28
ADF7012
APPLICATION EXAMPLES
R2
C1
C2
R1
VDD
C5+
10µF
C5
2.2µF
VDD
U1
ADF7012
C5
100pF
1
C6
2.2µF
CREG1
2
3
1kΩ
TxDATA
TxDATA
TxCLK
1kΩ
TxCLK
1kΩ
MUXOUT 6
MUXOUT
Y1
C8
27pF
OSC1
C9
1kΩ
CLKOUT
9 PIN D-TYPE PLUG
J3–3
J3–5
J3–7
R3
1kΩ
CLK
R4
1kΩ
DATA
R5
1kΩ
LE
CLK
DATA
8
OSC2
9
CLKOUT
10
CREG2
CREG1
RSET
CPOUT
AGND
DVDD
TxDATA
TxCLK
RFOUT
MUXOUT
RFGND
DGND
VCOIN
OSC1
CVCO
OSC2
L2
CLKOUT
L1
CLK
CE
DATA
LE
C10
470nF
C11
0.22µF
23
R9
3.6kΩ
22
C12
100pF
C13
2.2µF
VDD
21
L1
20
C14
L2
C15
19
LF1
CF1
18
17
16
L3
11
12
15
14
VDD
13
CE
R6
1kΩ
R7
1kΩ
R8
1kΩ
TxDATA
J5–1
J5–2
TxCLK
MUXOUT
J5–3
J5–4
CLKOUT
CLK
J5–5
J5–5
DATA
LE
J5–7
J5–8
CE
VDD
J5–9
J5–10
10 PIN HEADER (5X2)
Figure 40. Applications Diagrams with Harmonic Filter
Rev. 0 | Page 19 of 28
J4
LF2
CF2
LE
J3–6
J3–8
5
7
C7
27pF
J2
4
DVDD
CREG2
24
04617-0-035
J1
C3
CF2
ADF7012
315 MHZ OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to FCC site testing.
Matching components need to be adjusted for board layout.
The FCC standard 15.231 regulates operation in the band
from 260MHz to 470MHz in the US. This is used generally in
the transmission of RF control signals, such as in a satellitedecoder remote control, or remote keyless entry system. The
band cannot be used to send any continuous signal. The
maximum output power allowed is governed by the duty cycle
of the system. A typical design example for a remote control is
shown next.
Design Criteria
315 MHz center frequency
FSK/OOK modulation
1 mW output power
House range
Meets FCC 15.231
Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used.
Additional bias current reduces any spur, but increases current
consumption.
The PA bias can be set to 5.5 mA and achieve 0 dBm.
Loop Filter Bandwidth
The loop filter is designed with ADIsimPLL Version 2.5. The
loop bandwidth design is straightforward because the 20 dB
bandwidth is generally of the order of >400 kHz (0.25% of
center frequency). A loop bandwidth of close to 100 kHz strikes
a good balance between lock time and spurious suppression. If
it is found that pulling of the VCO is more than desired in OOK
mode, the bandwidth could be increased.
Design of Harmonic Filter
The main requirements in the design of this remote are a long
battery life and sufficient range. It is possible to adjust the
output power of the ADF7012 to increase the range depending
on the antenna performance.
The center frequency is 315 MHz. Because the ADF7012
VCO is not recommended for operation in fundamental mode
for frequencies below 400 MHz, the VCO needs to operate at
630 MHz. Figure 36 (Output Frequency vs. External Inductor
Value) implies an inductor value of 7.6 nH or close to this. The
chip inductor chosen = 7.5 nH (0402CS-7N5 from Coilcraft).
Coil inductors are recommended to provide sufficient Q for
oscillation.
Crystal and PFD
Phase noise requirements are not excessive as the adjacent
channel power requirement is −20 dB. The PFD is chosen so as
to minimize spurious levels (beat note and reference), and to
ensure a quick crystal power-up time.
PFD = 3.6864 MHz − Power-Up Time 1.6ms. Figure 10 shows a
typical power-on time for a 4 MHz crystal.
N-Divider
The N Divider is determined as being:
Nint = 85
Nfrac = (1850)/4096
VCO divide-by-2 is enabled
The main requirement of the harmonic filter should ensure that
the third harmonic level is < −41.5 dBm. A fifth-order
Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 3.6864MHz
Loop Filter
ICP
0.866 mA
LBW
100 kHz
C1
680 pF
C2
12 nF
C3
220 pF
R1
1.1 kV
R2
3 kV
Matching
L1
56 nH
L2
1 nF
C14
Short
C15
Open
Harmonic Filter
L4
22 nH
L5
22 nH
CF1
3.3 pF
CF2
8.2 pF
CF3
3.3 pF
Deviation
The deviation is set to ± 50 kHz so as to accommodate a simple
receiver architecture.
The modulation steps available are in 3.6864 MHz/214 :
Modulation steps = 225 Hz
Modulation number = 50 kHz/225 Hz = 222
Rev. 0 | Page 20 of 28
ADF7012
433 MHZ OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to ETSI site testing.
Matching components need to be adjusted for board layout.
The ETSI standard EN 300-220 governs operation in the
433.050 MHz to 434.790 MHz band. For many systems, 10%
duty is sufficient for the transmitter to output 10 dBm.
Design Criteria
Loop Filter Bandwidth
The loop filter is designed with ADIsimPLL Version 2.5. The
loop bandwidth design requires that the channel power be
< −36 dBm at ±870 kHz from the center. A loop bandwidth of
close to 160 kHz strikes a good balance between lock time for
data rates, including 32 kbps and spurious suppression. If it is
found that pulling of the VCO is more than desired in OOK
mode, the bandwidth could be increased.
Design of Harmonic Filter
433.92 MHz center frequency
FSK modulation
10 mW output power
200 m range
Meets ETSI 300-220
The main requirement in the design of this remote is a long
battery life and sufficient range. It is possible to adjust the
output power of the ADF7012 to increase the range depending
on the antenna performance.
The center frequency is 433.92 MHz. It is possible to operate the
VCO at this frequency. Figure 36 shows the inductor value vs.
center frequency. The inductor chosen is 22 nH. Coilcraft
inductors such as 0603-CS-22NXJBU are recommended.
Crystal and PFD
The phase noise requirement is such to ensure the power at the
edge of the band is < −36 dBm. The PFD is chosen so as to
minimize spurious levels (beat note and reference), and to
ensure a quick crystal power-up time.
PFD = 4.9152 MHz − Power-Up Time 1.6 ms. Figure 10 shows a
typical power-up time for a 4 MHz crystal.
N-Divider
The N Divider is determined as being:
Nint = 88
Nfrac = (1152)/4096
VCO divide-by-2 is not enabled
The main requirement of the harmonic filter should ensure
that the third harmonic level is < −30 dBm. A fifth-order
Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 4.9152 MHz
Loop Filter
Icp
2.0 mA
LBW
100 kHz
C1
680 pF
C2
12 nF
C3
270 pF
R1
910 V
R2
3.3 kV
Matching
L1
22 nH
L2
10 pF
C14
Short
C15
Open
Harmonic Filter
L4
22 nH
L5
22 nH
CF1
3.3 pF
CF2
8.2 pF
CF3
3.3 pF
Deviation
The deviation is set to ± 50 kHz so as to accommodate a simple
receiver architecture.
The modulation steps available are in 4.9152 MHz/214 :
Modulation steps = 300 Hz
Modulation number = 50 kHz/300Hz = 167
Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used.
Additional bias current reduces any spurious, but increases
current consumption.
The PA bias can be set to 5.5 mA and achieve 10 dBm.
Rev. 0 | Page 21 of 28
ADF7012
868 MHZ OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to ETSI site testing.
Matching components need to be adjusted for board layout.
The modulation steps available are in 4.9152 MHz/214 :
Modulation steps = 300 Hz
Modulation number = 19.2 kHz/300 Hz = 64.
The ETSI standard EN 300-220 governs operation in the
868 MHz to 870MHz band. The band is broken down into
several subbands each having a different duty cycle and output
power requirement. Narrowband operation is possible in the
50kHz channels, but both the output power and data rate are
limited by the −36 dBm adjacent channel power specification.
There are many different applications in this band, including
remote controls for security, sensor interrogation, metering
and home control.
Bias Current
Design Criteria
868.95 MHz center frequency (band 868.7MHz − 869.2 MHz)
FSK modulation
12 dBm output power
300 m range
Meets ETSI 300-220
38.4 kbps data rate
The design challenge is to enable the part to operate in this
particular subband and meet the ACP requirement 250 kHz
away from the center.
The center frequency is 868.95 MHz. It is possible to operate the
VCO at this frequency. Figure 31 shows the inductor value vs.
center frequency. The inductor chosen is 1.9 nH. Coilcraft
inductors such as 0402-CS-1N9XJBU are recommended.
Crystal and PFD
The phase noise requirement is such to ensure the power at
the edge of the band is < −36 dBm. This requires close to
−100 dBc/Hz phase noise at the edge of the band.
The PFD is chosen so as to minimize spurious levels (beat note
and reference), and to ensure a quick crystal power-up time. A
PFD of < 6 MHz places the largest PFD spur at a frequency of
greater than 862 MHz, and so reduces the requirement on the
spur level to −36 dBm instead of −54 dBm.
PFD = 4.9152 MHz − Power Up-Time 1.6 ms. Figure 10 shows a
typical power-on time for a 4MHz crystal.
Because low current is desired, a 2.5 mA VCO bias can be used.
Additional bias current reduces any spurious, but increases
current consumption. A 2.5 mA bias current gives the best
spurious vs. phase noise trade-off.
The PA bias should be set to 7.5 mA to achieve 12 dBm.
Loop Filter Bandwidth
The loop filter is designed with ADIsimPLL Version 2.5. The
loop bandwidth design requires that the channel power be
< −36 dBm at ±250 kHz from the center. A loop bandwidth of
close to <60 kHz is required to bring the phase noise at the edge
of the band sufficiently low to meet the ACP specification. This
represents a compromise between the data rate requirement and
the phase noise requirement.
Design of Harmonic Filter
The main requirement of the harmonic filter should ensure that
the second and third harmonic levels are < −30 dBm. A fifthorder Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 4.9152 MHz
Loop Filter
Icp
1.44 mA
LBW
60 kHz
C1
1.5 nF
C2
22 nF
C3
560 pF
R1
390 V
R2
910 V
Matching
L1
27 nH
L2
6.2 nH
C14
470 pF
C15
Open
Harmonic Filter
L4
8.2 nH
L5
8.2 nH
CF1
4.7 pF
CF2
6.8 pF
CF3
4.7 pF
N-Divider
The N divider is determined as being:
Nint = 176
Nfrac = (3229)/4096
VCO divide-by-2 is not enabled.
Deviation
The deviation is set to ±19.2 kHz so as to accommodate a
simple receiver architecture and also ensure that the
modulation spectrum is narrow enough to meet the adjacent
channel power (ACP) requirements.
Rev. 0 | Page 22 of 28
ADF7012
915 MHZ OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to FCC site testing.
Matching components need to be adjusted for board layout.
FCC 15.247 and FCC 15.249 are the main regulations governing
operation in the 902 MHz to 928 MHz Band. FCC 15.247
requires some form of spectral spreading. Typically, the
ADF7012 would be used in conjunction with the frequency
hopping spread spectrum (FHSS) or it may be used in
conjunction with the digital modulation standard which
requires large deviation frequencies. Output power of < 1 W
is tolerated on certain spreading conditions.
Compliance with FCC 15.249 limits the output power to
−1.5 dBm, but does not require spreading. There are many
different applications in this band, including remote controls
for security, sensor interrogation, metering, and home control.
Deviation
The deviation is set to ±19.2 kHz so as to accommodate a
simple receiver architecture, and also to ensure the available
spectrum is used efficiently.
The modulation steps available are in 10 MHz/214 :
Modulation steps = 610 Hz
Modulation number = 19.2 kHz/610 Hz = 31.
Bias Current
Because low current is desired, a 3 mA VCO bias can be used
and still ensure oscillation at 928 MHz. Additional bias current
reduces any spurious noise, but increases current consumption.
A 3 mA bias current gives the best spurious vs. phase noise
trade-off.
The PA bias should be set to 5.5 mA to achieve 10 dBm power.
Design Criteria
Loop Filter Bandwidth
915.2MHz center frequency
FSK modulation
10 dBm output power
200 m range
Meets FCC 15.247
38.4 kbps data rate
The loop filter is designed with ADIsimPLL Version 2.5. A
data rate of 170 kHz is chosen, which allows for data rates of
> 38.4 kbps. It also attenuates the beat note spurs quickly to
ensure they have no effect on system performance.
Design of Harmonic Filter
The center frequency is 915.2 MHz. It is possible to operate
the VCO at this frequency. Figure 36 shows the inductor value
vs. center frequency. The inductor chosen is 1.6 nH. Coilcraft
inductors such as 0603-CS-1N6XJBU are recommended.
Additional hopping frequencies can easily be generated by
changing the N value.
Crystal and PFD
The phase noise requirement is such to ensure that the 20 dB
bandwidth requirements are met. These are dependant on the
channel spacing chosen. A typical channel spacing would be
400 kHz, which would allow 50 channels in 20 MHz and enable
the design to avoid the edges of the band.
The PFD is chosen so as to minimize spurious levels. There are
beat note spurious levels at 910 MHz and 920 MHz, but the
level is usually significantly less than the modulation power.
They are also attenuated quickly by the loop filter to ensure a
quick crystal power-up time.
PFD = 10 MHz − Power-Up Time 1.8 ms (approximately).
Figure 10 shows a typical power-on time for a 4 MHz crystal.
N-Divider
The N divider is determined as being:
Nint = 91
Nfrac = (2130)/4096
VCO divide-by-2 is not enabled
The main requirement of the harmonic filter should ensure
that the third harmonic level is < −41.5 dBm. A fifth-order
Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the number of inductors in the system.
Component Values—Crystal: 10 MHz
Loop Filter
Icp
1.44 mA
LBW
170 kHz
C1
470 pF
C2
12 nF
C3
120 pF
R1
470 V
R2
1.8 kV
Matching
L1
27 nH
L2
6.2 nH
C14
470 pF
C15
Open
Harmonic Filter
L4
8.2 nH
L5
8.2 nH
CF1
4.7 pF
CF2
6.8 pF
CF3
4.7 pF
Rev. 0 | Page 23 of 28
ADF7012
REGISTER DESCRIPTIONS
OD1
OUTPUT DIVIDER
0
0
1
1
0
1
0
1
DISABLED
DIVIDE BY 2
DIVIDE BY 4
DIVIDE BY 8
VA2
VA1
VCO ADJUST
0
0
1
1
0
1
0
1
NO VCO ADJUSTMENT
(FCENTER – (1 × f))
(FCENTER – (2 × f))
(FCENTER – (3 × f))
ADDRESS
BITS
.......
F3
F2
F1
F-COUNTER
OFFSET
0
0
0
0
0
.......
.......
.......
.......
.......
1
1
.
0
0
0
0
.
0
0
0
1
.
1
0
+1023
+1022
.
+1
+0
1
1
.
1
1
.......
.......
.......
.......
.......
1
1
.
0
0
1
1
.
0
0
1
0
.
1
0
–1
–0
–1
–1023
–1024
C1 (0) DB0
DB2
F1
C2 (0) DB1
DB3
F2
DB4
DB8
F7
F3
DB9
F8
DB5
DB10
F9
DB6
DB11
F4
DB12
F11
F10
F5
DB13
R1
X1 XOEB
0
XTAL OSCILLATOR ON (DEFAULT)
1
XTAL OSCILLATOR OFF
F11
e.g., F-COUNTER OFFSET = 1, FRACTIONAL
OFFSET = 1/215
CL4
0
0
0
0
.
.
.
1
1
CL3
0
0
0
1
.
.
.
1
1
CL2
0
1
1
0
.
.
.
1
1
CL1
1
0
1
0
.
.
.
0
1
CLKOUT
DIVIDE RATIO
2
4
6
8
.
16 (DEFAULT)
.
28
30
Figure 41.
Rev. 0 | Page 24 of 28
RL4
0
0
0
0
.
.
.
1
1
1
1
RL3
0
0
0
1
.
.
.
1
1
1
1
RL2
0
1
1
0
.
.
.
0
0
1
1
RL1
1
0
1
0
.
.
.
0
1
0
1
RF R COUNTER
DIVIDE RATIO
1
2
3
4
.
.
.
12
13
14
15
04617-0-027
OD2
DB7
DB14
D1 CRYSTAL DOUBLER
0
CRYSTAL DOUBLER OFF
1
CRYSTAL DOUBLER ON
F6
DB15
R3
DB19
CL1
R2
DB20
CL2
DB16
DB21
CL3
R4
XOEB
DB22
CL4
DB17
DB23
VA1
DB18
DB24
VA2
11-BIT FREQUENCY ERROR CORRECTION
X1
DB25
OD1
4-BIT R DIVIDER
D1
DB26
DB27
CLOCK OUT
DIVIDER
OD2
DB28
DB29
DB30
DB31
OUTPUT
VCO
DIVIDER ADJUST
CRYSTAL
DOUBLER
R REGISTER
ADF7012
ADDRESS
BITS
C1 (1) DB0
C2 (0) DB1
DB2
0
1
2
.
.
.
4092
4093
4094
4095
.......
.......
.......
.......
.......
.......
.......
.......
.......
.......
DB3
0
1
0
.
.
.
0
1
0
1
0
0
0
.
.
.
1
1
1
1
M1
0
0
1
.
.
.
0
0
1
1
0
0
0
.
.
.
1
1
1
1
M2
DB8
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
DB4
DB9
M7
DB11
M8
DB12
M11
M10
DB10
DB13
M9
DB14
N1
M12
DB15
N2
MODULUS
DIVIDE RATIO
M3
DB16
N3
M1
DB5
DB17
N4
M2
DB6
DB18
N5
M3
M11
M4
DB19
N6
M10 .......
M12
M5
DB20
N7
12-BIT FRACTIONAL-N
DB7
DB21
N8
8-BIT INTEGER-N
M6
DB22 PRESCALER
DB23
P1
N-COUNTER LATCH
e.g., SETTING F = 0 IN FSK MODE TURNS ON THE Σ-∆ WHILE
THE PLL IS AN INTEGER VALUE
N8
0
0
0
.
.
.
1
1
N7
0
0
0
.
.
.
1
1
N6
0
0
0
.
.
.
1
1
N5
0
0
0
.
.
.
1
1
N4
0
0
0
.
.
.
1
1
N3
0
0
0
.
.
.
1
1
N2
0
0
1
.
.
.
1
1
N1
0
1
0
.
.
.
0
1
N-COUNTER
DIVIDE RATIO
1
2
3
.
.
.
254
255
P1 PRESCALER
0
4/5
1
8/9
THE N-VALUE CHOSEN IS A MINIMUM OF
P2 + 3P + 3. FOR PRESCALER 8/9 THIS
MEANS A MINIMUM N-DIVIDE OF 91.
Figure 42.
Rev. 0 | Page 25 of 28
04617-0-028
e.g., MODULUS DIVIDE RATIO = 2048 - > 1/2
ADF7012
DB11
DB10
DB9
DB8
D1
P6
P5
P4
MOD
CONTROL
GOOK
ADDRESS
BITS
C1 (0) DB0
DB12
D2
C2 (1) DB1
DB13
D3
DB2
DB14
D4
DB3
DB15
D5
S1
DB16
D6
S2
DB17
D7
DB4
DB18
D8
G1
DB19
D9
DB5
DB20
MC1
DB6
DB21
MC2
P1
DB22
MC3
P2
DB23
MUST BE LOW
DB7
DB24
POWER AMPLIFIER
IC1
MODULATION DEVIATION
P3
GFSK MOD
CONTROL
IC2
G1 GAUSSIAN OOK
0
ON
1
OFF
IF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = 0
D6
0
.
0
0
.
.
1
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
1
D2
X
0
0
1
.
.
1
D1
X
0
1
0
.
.
1
–16.0dBm
1/31 * 14dBm
2/31 * 14dBm
.
.
14dBm
IF FREQUENCY SHIFT KEYING SELECTED
D9
0
0
0
0
.
1
.......
.......
.......
.......
.......
.......
.......
D3
0
0
0
0
.
1
D2
0
0
1
1
.
1
D1
0
1
0
1
.
.
S1
MODULATION
SCHEME
0
0
1
1
0
1
0
1
FSK
GFSK
ASK
OOK
POWER AMPLIFIER OUTPUT LEVEL
P6
0
0
0
0
.
.
1
PA OFF
S2
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
1
P2
X
0
1
1
.
.
1
P1
X
1
0
1
.
.
1
PA OFF
–16.0dBm
1/31 * 14dBm
2/31 * 14dBm
.
.
13dBm
FSTEP = FPFD /214
F DEVIATION
PLL MODE
1 × –FSTEP
2 × –FSTEP
3 × –FSTEP
.......
511 × –FSTEP
IF GAUSSIAN FREQUENCY SHIFT KEYING SELECTED
IC2
0
0
1
1
IC1
0
1
0
1
INDEX COUNTER
16
32
64
128
MC3
0
0
.
1
MC2
0
0
.
1
MC1
0
1
.
1
GFSK MOD CONTROL
0
1
.
7
D7
0
0
0
0
.
1...
.......
.......
.......
.......
.......
.......
.......
Figure 43.
Rev. 0 | Page 26 of 28
D3
0
0
0
0
.
1
D2
0
0
1
1
.
1
D1
0
1
0
1
.
1
DIVIDER FACTOR
0
1
2
3
.......
127
04617-0-029
DB25
DB26
DB27
DB28
DB29
DB30
DB31
TEST BITS
INDEX
COUNTER
MODULATION REGISTER
ADF7012
VB4
0
0
.
1
PA2
0
0
1
.
.
1
VB3
0
0
.
1
PA1
0
1
0
.
.
1
VB2
0
1
.
1
PA BIAS
5µA
6µA
7µA
.
.
12µA
VB1
1
0
.
1
VCO BIAS
CURRENT
0.5mA
M3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
M2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ADDRESS
BITS
C1 (1) DB0
DB2
PD1
BLEED DOWN
PD1
PLL ENABLE
0
1
BLEED OFF
BLEED ON
0
1
PLL OFF
PLL ON
CP3
BLEED UP
PD2
PA ENABLE
0
1
BLEED OFF
BLEED ON
0
1
PA OFF
PA ON
CP2
CP1
0
0
1
1
0
1
0
1
CHARGE PUMP
CURRENT
0.3mA
0.9mA
1.5mA
2.1mA
VD1
VCO DISABLE
PD3
CLKOUT
0
1
VCO ON
VCO OFF
0
1
CLKOUT OFF
CLKOUT ON
M1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C2 (1) DB1
DB3
DB4
PD3
PD2
DB5
I1
DATA
INVERT
CLKOUT
ENABLE
PA
ENABLE
PLL ENABLE
DB6
CP1
VCO
DISABLE
CP4
1mA
.
8mA
M4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DATA INVERT
DATA
DATA
MUXOUT
LOGIC LOW
LOGIC HIGH
INVALID MODE – DO NOT USE
REGULATOR READY (DEFAULT)
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
R DIVIDER/2 OUTPUT
N DIVIDER/2 OUTPUT
RF R DIVIDER OUTPUT
DATA RATE
BATTERY MEASURE IS > 3.25V
BATTERY MEASURE IS > 3V
BATTERY MEASURE IS > 2.75V
BATTERY MEASURE IS > 2.35V
NORMAL TEST MODES
Σ-∆ TEST MODES
Figure 44.
Rev. 0 | Page 27 of 28
04617-0-030
PA3
0
0
0
.
.
1
DB7
DB8
DB12
M2
I1
0
1
CP2
DB13
M3
CP3
DB14
M4
DB9
DB15
LD1
CP4
DB16
VB1
DB11
DB17
VB2
DB10
DB18
VB3
M1
DB19
BLEED CHARGE
CURRENT PUMP
VD1
DB20
PA1
DB24
PT2
VB4
DB25
PT3
DB21
DB26
PT4
PA2
DB27
PT5
DB22
DB28
ST1
MUXOUT
DB23
DB29
ST2
VCO BIAS
PT1
DB30
PA BIAS
PA3
DB31
ST3
PLL TEST
MODES
ST4
SD TEST
MODES
LD
PRECISION
FUNCTION REGISTER
ADF7012
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
4.50
4.40
4.30
6.40 BSC
1
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
1.20
MAX
SEATING
PLANE
0.20
0.09
0.75
0.60
0.45
8°
0°
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AD
Figure 45. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Frequency Range
ADF7012BRU
ADF7012BRU-REEL
ADF7012BRU-REEL7
EVAL-ADF7012EB1
EVAL-ADF7012EB2
EVAL-ADF7012EB3
EVAL-ADF7012EB4
EVAL-ADF7012EB5
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
TSSOP
TSSOP, 13”REEL
TSSOP, 7” REEL
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
RU-24
RU-24
RU-24
50 MHz to 1 GHz
50 MHz to 1 GHz
50 MHz to 1 GHz
902 MHz to 928 MHz
860 MHz to 880 MHz
418 MHz to 435 MHz
310 MHz to 330 MHz
50 MHz to 1 GHz
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04617–0–10/04(0)
Rev. 0 | Page 28 of 28