ELPIDA EDD51321DBH-TS

PRELIMINARY DATA SHEET
512M bits DDR Mobile RAM
WTR (Wide Temperature Range)
EDD51321DBH-TS (16M words × 32 bits)
Specifications
Features
• Density: 512M bits
• Organization: 4M words × 32 bits × 4 banks
• Package: 90-ball FBGA
 Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.7V to 1.95V
• Data rate: 400Mbps/333Mbps (max.)
• 2KB page size
 Row address: A0 to A12
 Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
 Sequential (2, 4, 8)
 Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal, 1/2, 1/4
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
 Average refresh period: 7.8µs
• Operating ambient temperature range
 TA = −25°C to +85°C
• DLL is not implemented
• Low power consumption
• Double-data-rate architecture; two data transfers per
one clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver.
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Burst termination by burst stop command and
Precharge command
• Wide temperature range
 TA = −25°C to +85°C
• Low Power Function below is not supported
 Partal Array Self-Refresh (PASR)
 Auto Temperature Compensated Self-Refresh
 Deep power-down mode
Document No. E1398E40 (Ver. 4.0)
Date Published October 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008-2009
EDD51321DBH-TS
Ordering Information
Part number
Die
revision
Organization
(words × bits)
Internal
banks
Data rate
Mbps (max.)
/CAS latency
Package
EDD51321DBH-5BTS-F
D
16M × 32
4
400
3
90-ball FBGA
333
3
EDD51321DBH-6ETS-F
Part Number
E D D 51 32 1 D BH - 5B TS - F
Elpida Memory
Environment Code
F: Lead Free (RoHS Compliant)
and Halogen Free
Type
D: Monolithic Device
Spec Detail
TS: WTR (-25°C to +85°C)
Product Family
D: DDR Mobile RAM
Speed
5B: DDR400 (3-3-3)
6E: DDR333 (3-3-3)
Density / Bank
51: 512Mb / 4-bank
Organization
32: x32
Package
BH: FBGA
Power Supply, Interface
1: 1.8V, LVCMOS, w/o Low Power Function
Die Rev.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
2
EDD51321DBH-TS
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
2
1
3
4
5
6
7
8
9
A
VSS DQ31 VSSQ
VDDQ DQ16 VDD
VDDQ DQ29 DQ30
DQ17 DQ18 VSSQ
VSSQ DQ27 DQ28
DQ19 DQ20 VDDQ
VDDQ DQ25 DQ26
DQ21 DQ22 VSSQ
VSSQ DQS3 DQ24
DQ23 DQS2 VDDQ
B
C
D
E
F
VDD
DM3
NC
NC
DM2
CKE
CK
/CK
/WE
/CAS /RAS
A9
A11
A12
/CS
BA0
A6
A7
A8
A4
DM1
A5
VSS
G
H
BA1
J
A10 (AP) A0
A1
K
A2
DM0
A3
L
VSSQ DQS1 DQ8
DQ7 DQS0 VDDQ
VDDQ DQ9 DQ10
DQ5
DQ6 VSSQ
VSSQ DQ11 DQ12
DQ3
DQ4 VDDQ
VDDQ DQ13 DQ14
DQ1
DQ2 VSSQ
M
N
P
R
VSS DQ15 VSSQ
VDDQ DQ0
VDD
(Top view)
Pin name
Function
Pin name
Function
A0 to A12
Address inputs
CK
Clock input
BA0, BA1
Bank select address
/CK
Differential clock input
DQ0 to DQ31
Data-input/output
CKE
Clock enable
DQS0 to DQS3
Input and output data strobe
VDD
Power for internal circuit
/CS
Chip select
VSS
Ground for internal circuit
/RAS
Row address strobe
VDDQ
Power for DQ circuit
/CAS
Column address strobe
VSSQ
Ground for DQ circuit
/WE
Write enable
NC
No connection
DM0 to DM3
Input mask
Preliminary Data Sheet E1398E40 (Ver. 4.0)
3
EDD51321DBH-TS
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................12
Pin Function.................................................................................................................................................13
Command Operation ...................................................................................................................................15
Simplified State Diagram .............................................................................................................................21
Operation of the DDR Mobile RAM .............................................................................................................22
Timing Waveforms.......................................................................................................................................46
Package Drawing ........................................................................................................................................55
Recommended Soldering Conditions..........................................................................................................56
Preliminary Data Sheet E1398E40 (Ver. 4.0)
4
EDD51321DBH-TS
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VT
–0.5 to +2.3
V
Supply voltage relative to VSS
VDD
–0.5 to +2.3
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
–25 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = −25°C to +85°C)
Parameter
Pins
Symbol
VDD,
VDDQ
VSS,
VSSQ
Supply voltage
min.
typ.
max.
Unit
Notes
1.7
1.8
1.95
V
1
0
0
0
V
Input high voltage
All other input VIH
0.8 × VDDQ
—
VDDQ + 0.3
V
Input low voltage
pins
VIL
–0.3
—
0.2 × VDDQ
V
DC input voltage level
CK, /CK
VIN (DC)
–0.3
—
VDDQ + 0.3
V
AC Input differential cross
point voltage
VIX
0.4 × VDDQ
0.5 × VDDQ 0.6 × VDDQ
V
6
DC input differential voltage
VID (DC)
0.4 × VDDQ
—
V
5
VID (AC)
0.6 × VDDQ
—
VDDQ + 0.6
V
5
0.7× VDDQ
—
VDDQ + 0.3
V
–0.3
—
0.3 × VDDQ
V
AC input differential voltage
DC input high voltage
DQ, DM, DQS VIHD (DC)
DC input low voltage
VILD (DC)
VDDQ + 0.6
AC input high voltage
VIHD (AC)
0.8× VDDQ
—
VDDQ + 0.3
V
AC input low voltage
VILD (AC)
–0.3
—
0.2 × VDDQ
V
Notes: 1.
2.
3.
4.
5.
VDDQ must be equal to VDD.
VIH (max.) = 2.3V (pulse width ≤ 5ns).
VIL (min.) = –0.5V (pulse width ≤ 5ns).
All voltage referred to VSS and VSSQ must be same potential.
VID (DC) and VID (AC) are the magnitude of the difference between the input level on CK and the input
level on /CK.
6. The value of VIX is expected to be 0.5 × VDDQ and must track variations in the DC level of the same.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
5
EDD51321DBH-TS
DC Characteristics 1 (TA = –25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter
Symbol
Grade max.
90
65
mA
Standby current in power-down IDD2P
3.0
mA
Standby current in power-down
IDD2PS
with clock stop
2.8
mA
Standby current in
non power-down
6.0
mA
Standby current in non powerIDD2NS
down with clock stop
4.0
mA
Active standby current in
power-down
IDD3P
5.0
mA
Active standby current in
power-down with clock stop
IDD3PS
4.0
mA
Active standby current in non
power-down
IDD3N
10
mA
Active standby current in non
power-down with clock stop
IDD3NS
7.0
mA
Burst operating current
IDD4
155
130
mA
Auto-refresh current
IDD5
106
mA
Self-refresh current
IDD6
3.0
mA
Operating current
(ACT-PRE)
IDD0
-5B
-6E
Unit
IDD2N
-5B
-6E
Preliminary Data Sheet E1398E40 (Ver. 4.0)
6
Test condition
One bank active-precharge,
CKE = H, /CS = H between valid commands,
tCK = tCK (min.), tRC = tRC (min.),
Address bus inputs are SWITCHING;
Data bus inputs are STABLE
All banks idle,
CKE = L, /CS = H, tCK = tCK (min.),
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
All banks idle,
CKE = L, /CS = H, CK = L, /CK = H,
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
All banks idle,
CKE = H, /CS = H, tCK = tCK (min.),
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
All banks idle,
CKE = H, /CS = H, CK = L, /CK = H,
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
One bank active,
CKE = L, /CS = H, tCK = tCK (min.),
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
One bank active,
CKE = L, /CS = H, CK = L, /CK = H;
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
One bank active,
CKE = H, /CS = H, tCK = tCK (min.),
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
One bank active,
CKE = H, /CS = H, CK = L, /CK = H,
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
One bank active,
Continuous burst reads or writes;
tCK = tCK (min.), CL = 3, BL = 4, IOUT = 0mA,
Address inputs are SWITCHING,
50% data change each burst transfer
CKE = H, tCK = tCK (min.), tRFC = tRFC (min.),
Address and control inputs are SWITCHING;
Data bus inputs are STABLE
CKE = L
Notes
EDD51321DBH-TS
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by Test Conditions.
3. Definitions for IDD:
L is defined as VIN ≤ 0.1 × VDDQ;
H is defined as VIN ≥ 0.9 × VDDQ;
STABLE is defined as inputs stable at an H or L level;
SWITCHING is defined as:
Address and command: inputs changing between H and L once per two clock cycles;
Data bus inputs: DQ changing between H and L once per clock cycle; DM and DQS are STABLE.
DC Characteristics 2 (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Input leakage current
ILI
–2.0
2.0
µA
0 ≤ VIN ≤ VDDQ
Output leakage current
ILO
–1.5
1.5
µA
0 ≤ VOUT ≤ VDDQ,
DQ = disable
Output high voltage
VOH
0.9 × VDDQ
—
V
IOH = − 0.1mA
Output low voltage
VOL
—
0.1 × VDDQ
V
IOL = 0.1 mA
Notes
Pin Capacitance (TA = +25°C, VDD and VDDQ = 1.7V to 1.95V)
Parameter
Symbol
Pins
min.
typ.
max.
Unit
Notes
Input capacitance
CI1
CK, /CK
2.0
—
4.5
pF
1
CI2
All other input-only pins
2.0
—
4.5
pF
1
Cdi1
CK, /CK
—
—
0.25
pF
1
Cdi2
All other input-only pins
—
—
1.0
pF
1
Data input/output capacitance
CI/O
DQ, DM, DQS
3.5
—
6.0
pF
1, 2
Delta input/output capacitance
Cdio
DQ, DM, DQS
—
—
1.0
pF
1
Delta input capacitance
Notes: 1. These parameters are measured on conditions:
TA = +25°C.
2. DOUT circuits are disabled.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
7
f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,
EDD51321DBH-TS
AC Characteristics (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
-5B
-6E
Parameter
Symbol
min.
max.
min.
max.
Unit
Clock cycle time
tCK
5.0
—
6.0
—
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min.
( tCH, tCL)
—
min.
( tCH, tCL)
—
tCK
DQ output access time from CK, /CK
tAC
2.0
5.0
2.0
5.0
ns
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
tCK
DQS output access time from CK, /CK
tDQSCK
2.0
5.0
2.0
5.0
ns
2, 8
tHZ
—
5.0
—
5.0
ns
5, 8
tLZ
1.0
—
1.0
—
ns
6, 8
DQS to DQ skew
tDQSQ
—
0.4
—
0.5
ns
3
DQ/DQS output hold time from DQS
tQH
tHP − tQHS
—
tHP − tQHS
—
ns
4
Data hold skew factor
tQHS
—
0.5
—
0.65
ns
DQ and DM input setup time
tDS
0.48
—
0.6
—
ns
3
DQ and DM input hold time
tDH
0.48
—
0.6
—
ns
3
DQ and DM input pulse width
tDIPW
1.6
—
1.6
—
ns
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Write preamble setup time
tWPRES
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
0.2
—
tCK
DQS falling edge hold time from CK
tDSH
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.40
—
0.40
—
tCK
DQS input low pulse width
tDQSL
0.40
—
0.40
—
tCK
DQ-out high-impedance time from CK,
/CK
DQ-out low-impedance time from CK,
/CK
Notes
2, 8
7
Address and control input setup time
tIS
0.9
—
1.1
—
ns
3
Address and control input hold time
tIH
0.9
—
1.1
—
ns
3
Address and control input pulse width
tIPW
2.3
—
2.7
—
ns
3
Mode register set command cycle time
tMRD
2
—
2
—
tCK
Active to Precharge command period
tRAS
40
120000
42
120000
ns
tRC
55
—
60
—
ns
tRFC
72
—
72
—
ns
Active to Read/Write delay
tRCD
15
—
18
—
ns
Precharge to active command period
tRP
15
—
18
—
ns
Column address to column address
delay
tCCD
1
—
1
—
tCK
Active to active command period
tRRD
10
—
12
—
ns
Write recovery time
tWR
15
—
15
—
ns
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Preliminary Data Sheet E1398E40 (Ver. 4.0)
8
EDD51321DBH-TS
-5B
-6E
Parameter
Symbol
min.
max.
min.
max.
Unit
Autoprecharge write recovery and
precharge time
tDAL
—
—
—
—
Self-refresh exit period
tSREX
120
—
120
—
ns
Internal Write to Read command delay
tWTR
2
—
1
—
tCK
Average periodic refresh interval
tREF
—
7.8
—
7.8
µs
Notes
9
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VDDQ/2.
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals.
The signal transition is defined to occur when the signal level crossing VDDQ/2.
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading condition.
9. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and
minimum 1 clock for tRP.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next
higher integer.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
9
EDD51321DBH-TS
Test Conditions
Parameter
Symbol
Value
Unit
Note
Input high voltage
VIH (AC)
0.8 × VDDQ
V
1
Input low voltage
VIL (AC)
0.2 × VDDQ
V
1
Input differential voltage, CK and /CK inputs
VID (AC)
1.4
V
1
Input differential cross point voltage,
CK and /CK inputs
VIX (AC)
VDDQ/2 with VDD=VDDQ
V
Input signal slew rate
SLEW
1
V/ns
Output load
CL
15
pF
1
Note: 1. VDD = VDDQ
tCK
tCH
tCL
/CK
VIH
VID
VIX
CK
VIL
tLZ
tAC
T
slew rate =
DQOUT
Q1
Q2
VDDQ/2
(DQOUT)
Test Condition (Wave form and Timing Reference)
DQ
CL
Output Load
Preliminary Data Sheet E1398E40 (Ver. 4.0)
10
(VIH − VIL)
T
EDD51321DBH-TS
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
Parameter
5.0ns
6.0ns
7.5ns
Symbol
min.
max.
min.
max.
min.
max.
Unit
tWPD
4 + BL/2

4 + BL/2

3 + BL/2

tCK
tRPD
BL/2

BL/2

BL/2

tCK
tWRD
3 + BL/2

2 + BL/2

2 + BL/2

tCK
tBSTW
3

3

3

tCK
tBSTZ
3

3

3

tCK
tRWD
3 + BL/2

3 + BL/2

3 + BL/2

tCK
tHZP
3

3

3

tCK
Write command to data in latency
tWCD
1

1

1

tCK
Write recovery
tWR
3

3

2

tCK
DM to data in latency
tDMD
0

0

0

tCK
tMRD
2

2

2

tCK
tSREX
24

20

16

tCK
Auto-refresh period
tRFC
15

12

10

tCK
Power-down entry
tPDEN
2

2

1

tCK
Power-down exit to command input
tPDEX
1

1

1

tCK
CKE minimum pulse width
tCKE
2

2

2

tCK
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write
command delay
(CL = 3)
Burst stop command to DQ high-Z
(CL = 3)
Read command to write command
delay (to output all data)
(CL = 3)
Pre-charge command to high-Z
(CL = 3)
Mode register set command cycle
time
Self-refresh exit to non-column
command
Preliminary Data Sheet E1398E40 (Ver. 4.0)
11
EDD51321DBH-TS
Clock
generator
Block Diagram
Bank 3
Bank 2
Bank 1
Address, BA0, BA1
Mode
register
Row
address
buffer
and
refresh
counter
Row decoder
CK
/CK
CKE
Memory cell array
Bank 0
Control logic
/CS
/RAS
/CAS
/WE
Command decoder
Sense amp.
Column
address
buffer
and
burst
counter
Column decoder
Data control circuit
Latch circuit
Input & Output buffer
DQ
Preliminary Data Sheet E1398E40 (Ver. 4.0)
12
DQS
DM
EDD51321DBH-TS
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the /CK falling edge. When a read operation, DQSs and DQs are referred to the
cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS
and the VDDQ/2 level. DQSs for write operation are referred to the cross point of the CK and the /CK. The other
input signals are referred at CK rising edge.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address is loaded at the cross point of the CK rising edge
and the /CK falling edge in a read or a write command cycle (See “Address Pins Table”). This column address
becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Page size
Organization
Row address
Column address
EDD51321DBH
2KB
× 32 bits
AX0 to AX12
AY0 to AY8
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write
command, auto precharge function is enabled.
BA0 and BA1 (input pins)
BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3.
(See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
13
EDD51321DBH-TS
CKE (input pin)
CKE controls power-down mode, self-refresh function with other command inputs.
The CKE level must be kept for 2 clocks at least, that is, if CKE changes at the cross point of the CK rising edge and
the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ0 to DQ31 (input/output pins)
Data are input to and output from these pins.
DQS0 to DQS3 (input and output pin): DQS provides the read data strobes (as output) and the write data strobes
(as input). Each DQS pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
DM0 to DM3 (input pin)
DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS and VDDQ/2.
When DM = high, the data input at the same timing are masked while the internal burst counter will be counting up.
Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
[DQS and DM Correspondence Table]
Part number
Organization
DQS
Data mask
DQs
EDD51321DBH
× 32 bits
DQS0
DM0
DQ0 to DQ7
DQS1
DM1
DQ8 to DQ15
DQS2
DM2
DQ16 to DQ23
DQS3
DM3
DQ24 to DQ31
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers. VDD must be equal to VDDQ.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
14
EDD51321DBH-TS
Command Operation
Command Truth Table
The DDR Mobile RAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Command
Symbol
n–1
n
/CS
/RAS /CAS /WE
BA1
BA0
AP
Address
Ignore command
DESL
H
H
H
×
×
×
×
×
×
×
No operation
NOP
H
H
L
H
H
H
×
×
×
×
Burst stop command
BST
H
H
L
H
H
L
×
×
×
×
Column address and read command
READ
H
H
L
H
L
H
V
V
L
V
Read with auto precharge
READA
H
H
L
H
L
H
V
V
H
V
Column address and write command
WRIT
H
H
L
H
L
L
V
V
L
V
Write with auto precharge
WRITA
H
H
L
H
L
L
V
V
H
V
Row address strobe and bank active
ACT
H
H
L
L
H
H
V
V
V
V
Precharge select bank
PRE
H
H
L
L
H
L
V
V
L
×
Precharge all bank
PALL
H
H
L
L
H
L
×
×
H
×
Refresh
REF
H
H
L
L
L
H
×
×
×
×
SELF
H
L
L
L
L
H
×
×
×
×
MRS
H
H
L
L
L
L
L
L
L
V
EMRS
H
H
L
L
L
L
H
L
L
V
Mode register set
Remark: H: VIH. L: VIL. ×: Don’t care V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is high at the cross point of the CK rising edge and the VDDQ/2 level, all input signals are neglected and
internal state is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VDDQ/2 level, address and data
input are neglected and internal state is held.
Burst stop command [BST]
This command stops a current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
all output buffers become high-Z.
Read with auto precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
15
EDD51321DBH-TS
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0 and BA1 (See Bank Select Signal Table) and determines
the row address (Address Pins Table in “Pin Function”).
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0 and BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR Mobile RAM has the two mode registers, the mode register and the extended mode register, to defines
how it works. The both mode registers are set through the address pins in the mode register set cycle. For details,
refer to "Mode register and extended mode register set".
Preliminary Data Sheet E1398E40 (Ver. 4.0)
16
EDD51321DBH-TS
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR Mobile RAM.
Current state
Precharging*
Idle*
1
2
Refresh
3
(auto-refresh)*
Activating*
Active*
5
4
/CS
/RAS /CAS /WE
Address
Command
Operation
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL*
11
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
×
×
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
L
L
H
H
BA, RA
ACT
Activating
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh/
12
Self-refresh*
L
L
L
L
MODE
MRS
Mode register set*
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
H
H
H
L
×
BST
ILLEGAL
L
H
L
×
×
12
ILLEGAL
L
L
×
×
×
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL*
11
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11
L
L
L
×
×
ILLEGAL
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation
L
H
L
L
BA, CA, A10
WRIT/WRITA
Starting write operation
L
L
H
H
BA, RA
ACT
ILLEGAL*
PRE, PALL
Pre-charge
L
L
H
L
BA, A10
L
L
L
×
×
ILLEGAL
Preliminary Data Sheet E1398E40 (Ver. 4.0)
17
11
EDD51321DBH-TS
Current state
Read*
6
/CS
/RAS /CAS /WE
Address
Command
Operation
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA
Interrupting burst read
operation to
start new read
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
13
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
L
L
H
L
BA, A10
PRE, PALL
Interrupting burst read
operation to start pre-charge
L
L
L
×
×
Read with auto preH
7
charge*
×
×
×
×
DESL
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
14
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11, 14
L
L
L
×
×
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
Write*
8
Write recovering*
9
ILLEGAL
NOP
ILLEGAL
Burst Stop
Interrupting burst write
operation to
start read operation.
Interrupting burst write
operation to
start new write
operation.
L
H
L
H
BA, CA, A10
READ/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
L
L
H
L
BA, A10
PRE, PALL
Interrupting write operation to
start pre-charge.
L
L
L
×
×
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
11
ILLEGAL
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation.
L
H
L
L
BA, CA, A10
WRIT/WRITA
Starting new write operation.
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL*
11
L
L
L
×
×
ILLEGAL
Preliminary Data Sheet E1398E40 (Ver. 4.0)
18
EDD51321DBH-TS
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Write with auto preH
1
charge*
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL*
14
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11, 14
L
L
L
×
×
ILLEGAL
H: VIH. L: VIL. ×: Don’t care.
The DDR Mobile RAM is in "Precharging" state for tRP after precharge command is issued.
The DDR Mobile RAM reaches "IDLE" state tRP after precharge command is issued.
The DDR Mobile RAM is in "Refresh" state for tRFC after auto-refresh command is issued.
The DDR Mobile RAM is in "Activating" state for tRCD after ACT command is issued.
The DDR Mobile RAM is in "Active" state after "Activating" is completed.
The DDR Mobile RAM is in "READ" state until burst data have been output and DQ output circuits are
turned off.
7. The DDR Mobile RAM is in "READ with auto precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8. The DDR Mobile RAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR Mobile RAM is in "Write recovering" for tWR after the last data are input.
10. The DDR Mobile RAM is in "Write with auto precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
issued.
14. The DDR Mobile RAM supports the concurrent auto precharge feature, a read with auto precharge or a
write with auto precharge, can be followed by any command to the other banks, as long as that command
does not interrupt the read or write data transfer, and all other related limitations apply (e.g. contention
between READ data and WRITE data must be avoided.)
Remark:
Notes: 1.
2.
3.
4.
5.
6.
The minimum delay from a read or write command with auto precharge, to a command to a different bank,
is summarized below.
From command
To command (different bank, noninterrupting command)
Minimum delay
(Concurrent AP supported)
Units
Read w/AP
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
CL (rounded up)+ (BL/2)
tCK
Precharge or Activate
1
tCK
Read or Read w/AP
1 + (BL/2) + tWTR
tCK
Write w/AP
Write or Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
Preliminary Data Sheet E1398E40 (Ver. 4.0)
19
EDD51321DBH-TS
CKE Truth Table
CKE
Current state
Command
n–1
n
/CS
/RAS
/CAS
/WE
Address
Notes
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
2
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
2
Active/Idle
Power-down entry (PDEN)
Self-refresh
Self-refresh exit (SELFX)
Power-down
Power-down exit (PDEX)
H
L
L
H
H
H
×
H
L
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Notes: 1. H: VIH . L: VIL × : Don’t care.
2. All the banks must be in IDLE before executing this command.
3. The CKE level must be kept for 1 clock cycle at least.
Auto-refresh command [REF]
This command executes auto-refresh. The bank and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The output buffer becomes high-Z after auto-refresh start. Precharge has been
completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last autorefresh command.
The average refresh cycle is 7.8µs. To allow for improved efficiency in scheduling, some flexibility in the absolute
refresh interval (64ms) is provided. A maximum of eight auto-refresh commands can be posted to the DDR Mobile
RAM or the maximum absolute interval between any auto-refresh command and the next auto-refresh command is
8 × tREF.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the selfrefresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power-down mode entry [PDEN]
tPDEN after the cycle when [PDEN] is issued, the DDR Mobile RAM enters into power-down mode. In power-down
mode, power consumption is suppressed by deactivating the input initial circuit. Power-down mode continues while
CKE is held low. No internal refresh operation occurs during the power-down mode.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. tSREX after [SELFX], the device will be into idle state.
Power-down exit [PDEX]
The DDR Mobile RAM can exit from power-down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
20
EDD51321DBH-TS
Simplified State Diagram
SELF
REFRESH
EXTENDED
MODE
REGISTER
SET
SR ENTRY
EM
RS
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
POWER
DOWN
ACTIVE
CKE_
CKE
ROW
ACTIVE
BST
BST
READ
WRITE
WRITE
WRITE
WITH
AP
WRITE
READ
WITH
AP
READ
READ
READ
WITH AP
WRITE
WITH AP
READ
READ
WITH AP
PRECHARGE
WRITEA
READA
PRECHARGE
POWER
APPLIED
POWER
ON
PRECHARGE
PRECHARGE
PRECHARGE
Automatic sequence
Manual input
Preliminary Data Sheet E1398E40 (Ver. 4.0)
21
EDD51321DBH-TS
Operation of the DDR Mobile RAM
Initialization
The DDR Mobile RAM is initialized in the power-on sequence according to the following.
1. Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up
simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are
from the same power source. Also assert and hold Clock Enable (CKE) to a LV-CMOS logic high level.
2. Once the system has established consistent device power and CKE is driven high, it is safe to apply stable clock.
3. There must be at least 200µs of valid clocks before any command may be given to the DRAM. During this time
NOP or deselect (DESL) commands must be issued on the command bus.
4. Issue a precharge all command.
5. Provide NOPs or DESL commands for at least tRP time.
6. Issue an auto-refresh command followed by NOPs or DESL command for at least tRFC time. Issue the second
auto-refresh command followed by NOPs or DESL command for at least tRFC time. Note as part of the
initialization sequence there must be two auto-refresh commands issued. The typical flow is to issue them at
Step 6, but they may also be issued between steps 10 and 11.
7. Using the MRS command, load the base mode register. Set the desired operating modes.
8. Provide NOPs or DESL commands for at least tMRD time.
9. Using the MRS command, program the extended mode register for the desired operating modes.
10. Provide NOP or DESL commands for at least tMRD time.
11. The DRAM has been properly initialized and is ready for any valid command.
Preliminary Data Sheet E1398E40 (Ver. 4.0)
22
EDD51321DBH-TS
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0 and BA1 pins by the mode register set
command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode
register are set by inputting signal via the A0 to the A12 and BA0 and BA1 pins during mode register set cycles.
BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a
write operation, the mode register must be set.
Mode Register
The mode register has four fields;
Reserved
/CAS latency
Burst type
Burst length
: A12 through A7
: A6 through A4
: A3
: A2 through A0
Following mode register programming, no command can be issued before at least 2 clocks have elapsed.
/CAS Latency
/CAS latency must be set to 3.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become high-Z. The burst length is programmable as 2, 4 and 8.
Burst Type (Burst Sequence)
The burst type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. “Burst Operation” shows the addressing sequence for each burst length for each burst
type.
BA0
BA1
0
0
A12 A11 A10 A9
0
0
0
0
A8
A7
0
0
A6
A5
A4
LMODE
A3
BT
A2
A1
BL
MRS
A6 A5 A4 CAS Latency
A3 Burst Type
0
0
0
Reserved
0 Sequential
0
0
0
1
1
0
Reserved
Reserved
1 Interleave
0
1
1
0
1
0
1
0
1
1
1
1
1
Burst Length
A2 A1 A0
0
0
0
BT = 0
Reserved
0
0
1
2
2
3
Reserved
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
Mode Register Set
Preliminary Data Sheet E1398E40 (Ver. 4.0)
23
BT = 1
Reserved
A0
EDD51321DBH-TS
Extended Mode Register
The extended mode register is as follows;
Reserved
Driver Strength
: A12 through A7, A4 through A0
: A6 through A5
Following extended mode register programming, no command can be issued before at least 2 clocks have elapsed.
Driver Strength
BA1 BA0
1
0
A12 A11 A10
0
0
0
A9
A8
A7
0
0
0
A6
A5
DS
A4
A3
A2
A1
A0
0
0
0
0
0
A6 A5 Driver Strength
0
0
1
1
0
1
0
1
Normal
1/2 strength
1/4 strength
Reserved
Extended Mode Register Set
Preliminary Data Sheet E1398E40 (Ver. 4.0)
24
EDD51321DBH-TS
Power-Down Mode and CKE Control
DDR Mobile RAM will be into power-down mode at the second CK rising edge after CKE to be low level with NOP or
DESL command at first CK rising edge after CKE signal to be low.
CK
/CK
CKE
Command
Valid*1
Address
Valid*1
NOP
Valid*2
NOP
NOP
Valid*2
Power-down mode
Notes: 1. Valid*1 can be either Activate command or Precharge command, When Valid*1 is Activate command,
power-down mode will be active power-down mode, while it will be precharge power down mode,
if Valid*1 will be Precharge command.
2. Valid*2 can be any command as long as all of specified AC parameters are satisfied.
Power-Down Entry and Exit
However, if the CKE has one clock cycle high and on clock cycle low just as below, even DDR Mobile RAM will not
enter power-down mode, this command flow does not hurt any data and can be done.
CK
/CK
CKE
Command
PRE
NOP
NOP
ACT
Note: Assume PRE and ACT command is closing and activating same bank.
CKE Control
Preliminary Data Sheet E1398E40 (Ver. 4.0)
25
EDD51321DBH-TS
Burst Operation
The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequence
Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequence
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
A0 Sequence
Interleave
0
0
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
Preliminary Data Sheet E1398E40 (Ver. 4.0)
26
EDD51321DBH-TS
Read/Write Operations
Bank Active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read Operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4 or 8. The starting address of the burst read is defined by the column address, the bank select
address (See “Pin Function”) in the cycle when the read command is issued. The data output timing is characterized
by CL and tAC. The read burst start (CL-1) × tCK + tAC (ns) after the clock rising edge where the read command is
latched. The DDR Mobile RAM outputs the data strobe through DQS pins simultaneously with data. tRPRE prior to
the first rising edge of the data strobe, the DQS pins are driven low from high-Z state. This low period of DQS is
referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data
strobe. The DQ pins become high-Z in the next cycle after the burst read operation completed. tRPST from the last
falling edge of the data strobe, the DQS pins become high-Z. This low period of DQS is referred as read postamble.
CK
/CK
Command
Address
tRCD
NOP
ACT
NOP
Row
READ
NOP
Column
tRPRE
out0 out1
BL = 2
tRPST
DQS
DQ
out0 out1 out2 out3
BL = 4
out0 out1 out2 out3 out4 out5 out6 out7
BL = 8
CL = 3
BL: Burst length
Read Operation (Burst Length)
Preliminary Data Sheet E1398E40 (Ver. 4.0)
27
EDD51321DBH-TS
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
Command
READ
NOP
tRPRE
tRPST
VTT
DQS
tAC,tDQSCK
out0
DQ
out1
out2
VTT
out3
Read Operation (/CAS Latency)
Write Operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst write is defined
by the column address, the bank select address (See “Pin Function”) in the cycle when the write command is issued.
DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first
rising edge of DQS, DQS must be set to low. tWPST after the last falling edge of DQS, the DQS pins can be
changed to high-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is
referred as write postamble.
CK
/CK
Command
Address
tRCD
NOP
ACT
NOP
Row
WRIT
NOP
Column
tWPRE
tWPRES
BL = 2
in0
in1
tWPST
DQS
DQ
BL = 4
BL = 8
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
BL: Burst length
Write Operation
Preliminary Data Sheet E1398E40 (Ver. 4.0)
28
EDD51321DBH-TS
Burst Stop
Burst Stop Command during Burst Operation
The burst stop (BST) command stops the burst read and sets all output buffers to high-Z. tBSTZ (= CL) cycles after
a BST command issued, all DQ and DQS pins become high-Z.
The BST command is also supported for the burst write operation. No data will be written in subsequent cycles.
Note that bank address is not referred when this command is executed.
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
Command
READ
BST
NOP
tBSTZ
DQS
out0
DQ
out1
CL: /CAS latency
Burst Stop during a Read Operation
Preliminary Data Sheet E1398E40 (Ver. 4.0)
29
EDD51321DBH-TS
Auto Precharge
Read with Auto Precharge
The precharge is automatically performed after completing a read operation. The precharge starts BL/2 (= tRPD)
clocks after READA command input. tRAS lock out mechanism for READA allows a read command with auto
precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min)
specification. A column command to the other active bank can be issued the next cycle after the last data output.
Read with auto precharge command does not limit row commands execution for other bank.
CK
/CK
tRP (min)
tRAS (min)
tRCD (min)
Command
ACT
BL/2 (= tRPD)
READA
NOP
ACT
DQS
tAC,tDQSCK
DQ
out0
Note: Internal auto-precharge starts at the timing indicated by "
out1
out2
out3
".
Read with auto precharge
Write with Auto Precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started Write latency (WL) + BL/2 + tWR (= tWPD) clocks after WRITA command issued.
A column command to the other banks can be issued the next cycle after the internal precharge command issued.
Write with auto precharge command does not limit row commands execution for other bank.
CK
/CK
tRAS (min)
tRP
tRCD (min)
Command
ACT
NOP
WRITA
NOP
ACT
WL + BL/2 + tWR (= tWPD)
DM
DQS
DQ
in1
in2
in3
Note: Internal auto-precharge starts at the timing indicated by "
in4
".
Burst Write (BL = 4)
Preliminary Data Sheet E1398E40 (Ver. 4.0)
30
BL = 4
;;;;;;
EDD51321DBH-TS
Command Intervals
A Read Command to the Consecutive Read Command Interval
Destination row of the
consecutive read command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
IDLE
t0
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
tn
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
ACT
Address
Row
NOP
READ
NOP
READ
Column A Column B
BA
out
A0
DQ
Column = A Column = B
Read
Read
out
A1
Column = A
Dout
out
B0
out out
B1 B2
out
B3
Column = B
Dout
DQS
Bank0
Active
CL = 3
BL = 4
Bank0
READ to READ Command Interval (same ROW address in the same bank)*
Note: n ≥ 4
Preliminary Data Sheet E1398E40 (Ver. 4.0)
31
;
;;; ;
EDD51321DBH-TS
t0
t1
t2
ACT
NOP
ACT
tn
tn+1
READ
READ
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
Address
Row0
Row1
NOP
NOP
Column A Column B
BA
out out
A0 A1
DQ
Column = A Column = B
Read
Read
Bank0
Dout
out out out out
B0 B1 B2 B3
Bank3
Dout
DQS
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
READ to READ Command Interval (different bank)*
Note: n ≥ 4
Preliminary Data Sheet E1398E40 (Ver. 4.0)
32
CL = 3
BL = 4
;;;;;
EDD51321DBH-TS
A Write Command to the Consecutive Write Command Interval
Destination row of the consecutive write
command
Bank
address
1.
Same
2.
Same
3.
Different
Row address State
Operation
Same
ACTIVE
Different
—
Any
ACTIVE
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank to interrupt the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A write command to the
consecutive precharge interval’ section.
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank without interrupting the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive write command can be issued.
IDLE
t0
CK
/CK
Command
Address
BA
DQ
ACT
Row
tn
NOP
WRIT
tn+1
tn+2
tn+4
tn+5
tn+6
NOP
WRIT
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Column = A
Write
DQS
tn+3
Column = B
Write
Bank0
Active
BL = 4
Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
Preliminary Data Sheet E1398E40 (Ver. 4.0)
33
;;; ;;;
EDD51321DBH-TS
CK
/CK
Command
Address
BA
DQ
t0
t1
t2
ACT
NOP
ACT
Row0
Row1
tn
NOP
WRIT
tn+1
tn+3
tn+4
tn+5
NOP
WRIT
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Bank0
Write
DQS
tn+2
Bank0
Active
Bank3
Write
Bank3
Active
BL = 4
Bank0, 3
WRITE to WRITE Command Interval (different bank)
Preliminary Data Sheet E1398E40 (Ver. 4.0)
34
EDD51321DBH-TS
A Read Command to the Consecutive Write Command Interval with the BST Command
Destination row of the consecutive write
command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
IDLE
t0
t1
READ
BST
Operation
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
WRIT
NOP
tBSTW (≥ tBSTZ)
DM
tBSTZ (= CL)
DQ
out0 out1
in0
in1
in2
in3
High-Z
DQS
OUTPUT
INPUT
READ to WRITE Command Interval
Preliminary Data Sheet E1398E40 (Ver. 4.0)
35
BL = 4
CL = 3
EDD51321DBH-TS
A Write Command to the Consecutive Read Command Interval: To Complete the Burst Operation
Destination row of the consecutive read
command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
IDLE
t0
t1
t2
t3
tn
tn + 1
tn + 2
tn + 3
tn + 4
CK
/CK
Command
WRIT
NOP
READ
NOP
tWRD (min)
tWTR*
DM
DQ
in0
in1
in2
out0
in3
out1
out2
DQS
INPUT
OUTPUT
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval
Preliminary Data Sheet E1398E40 (Ver. 4.0)
36
BL = 4
CL = 3
EDD51321DBH-TS
A Write Command to the Consecutive Read Command Interval: To Interrupt the Write Operation
Destination row of the consecutive read
command
Bank
address
Row address State
Operation
1.
Same
Same
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
2.
Same
Different
—
—*
3.
Different
Any
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
IDLE
—*
1
1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
t0
t1
WRIT
READ
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
DM
DQ
in0
in1
in2
out0 out1 out2 out3
High-Z
High-Z
DQS
BL = 4
CL = 3
Data masked
[WRITE to READ delay = 1 clock cycle]
Preliminary Data Sheet E1398E40 (Ver. 4.0)
37
EDD51321DBH-TS
t0
t1
t2
WRIT
NOP
READ
t3
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
DM
DQ
in0
in1
in2
in3
High-Z
out0 out1 out2 out3
High-Z
DQS
Data masked
BL = 4
CL = 3
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
CK
/CK
Command
WRIT
NOP
READ
NOP
tWTR*
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
DQS
BL = 4
CL = 3
Data masked
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 4 clock cycle]
Preliminary Data Sheet E1398E40 (Ver. 4.0)
38
;;;;;;;;
EDD51321DBH-TS
A Write Command to the Bust Stop Command Interval: To Interrupt the Write Operation
WRITE to BST Command Interval (Same bank, same ROW address)
t0
t1
WRIT
BST
t2
t3
t4
t5
t6
t7
CK
/CK
Command
NOP
DM
DQ
in0
in1
DQS
BL = 4 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 1 clock cycle]
t0
t1
t2
WRIT
NOP
BST
t3
t4
t5
t6
t7
CK
/CK
Command
NOP
DM
DQ
in0
in1
in2
in3
DQS
Data will be written
Following data will not be written.
[WRITE to BST delay = 2 clock cycle]
Preliminary Data Sheet E1398E40 (Ver. 4.0)
39
BL = 8 or longer
;; ;;
EDD51321DBH-TS
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
WRIT
NOP
BST
NOP
DM
DQ
in0
in1
in2
in3
in4
in5
DQS
BL = 8 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 3 clock cycle]
Preliminary Data Sheet E1398E40 (Ver. 4.0)
40
EDD51321DBH-TS
A READ Command to the Consecutive Precharge Command Interval
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
1.
Same
2.
Different
Operation
The PRE and PALL command can interrupt a read operation.
To complete a burst read operation, tRPD is required between the read and the precharge
command. Please refer to the following timing chart.
The PRE command does not interrupt a read command.
No interval timing is required between the read and the precharge command.
READ to PRECHARGE Command Interval (same bank) : To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0
t1
t2
t3
NOP
READ
NOP
PRE/
PALL
t4
t5
t6
t7
t8
CK
/CK
Command
DQ
NOP
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become high-Z tHZP
(= CL) after the precharge command.
t0
t1
t2
t3
READ
PRE/PALL
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
NOP
High-Z
DQ
out0 out1
High-Z
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 4, 8)
Preliminary Data Sheet E1398E40 (Ver. 4.0)
41
EDD51321DBH-TS
A Write Command to the Consecutive Precharge Command Interval (same bank)
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
1.
Same
2.
Different
Operation
The PRE and PALL command can interrupt a write operation.
To complete a burst write operation, tWPD is required between the write and the precharge
command. Please refer to the following timing chart.
The PRE command does not interrupt a write command.
No interval timing is required between the write and the precharge command.
WRITE to PRECHARGE Command Interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
t0
t1
t2
t3
t4
tn
tn + 1
tn + 2
CK
/CK
Command
WRIT
PRE/PALL
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Preliminary Data Sheet E1398E40 (Ver. 4.0)
42
NOP
EDD51321DBH-TS
t0
t1
t2
t3
tn
tn + 1
tn + 2
tn + 3
CK
/CK
Command
WRIT
PRE/PALL
NOP
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
Last data
input
in2
in3
Data
masked
BL = 4
WRITE to PRECHARGE Command Interval (same bank) (BL = 4, DM to mask data)
Preliminary Data Sheet E1398E40 (Ver. 4.0)
43
EDD51321DBH-TS
Bank Active Command Interval
Destination row of the consecutive ACT
command
Bank
address
Row address
State
1.
Same
Any
ACTIVE
2.
Different
Any
ACTIVE
IDLE
Operation
Two successive ACT commands can be issued at tRC interval. In between two
successive ACT operations, precharge command should be executed.
Precharge the bank. tRP after the precharge command, the consecutive ACT
command can be issued.
tRRD after an ACT command, the next ACT command can be issued.
CK
/CK
Command
Address
ACTV
ACT
ACT
ROW: 0
ROW: 1
Bank0
Active
Bank3
Active
PRE
NOP
NOP
ACT
NOP
ROW: 0
BA
tRRD
Bank0
Precharge
Bank0
Active
tRC
Bank Active to Bank Active
Mode Register Set to Bank-Active Command Interval
The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK
/CK
Command
MRS
Address
CODE
NOP
ACT
BS and ROW
Mode Register Set
tMRD
Bank3
Active
Mode Register Set to Bank Active
Preliminary Data Sheet E1398E40 (Ver. 4.0)
44
NOP
EDD51321DBH-TS
DM Control
DM can mask input data. By setting DM to low, data can be written. When DM is set to high, the corresponding
data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask
function is 0.
t1
t2
t3
t4
DQS
DQ
Mask
Mask
DM
Write mask latency = 0
DM Control
Preliminary Data Sheet E1398E40 (Ver. 4.0)
45
t5
t6
EDD51321DBH-TS
Timing Waveforms
Command and Addresses Input Timing Definition
CK
/CK
Command
(/RAS, /CAS,
/WE, /CS)
tIS
tIH
tIS
tIH
Address
= Don't care
Read Timing Definition (1)
CK
/CK
Command
READ
tLZ (min.)
DQ
(Output)
tHZ (max.)
High-Z
High-Z
tLZ (min.)
DQS
High-Z
High-Z
CL = 3
BL = 2
Preliminary Data Sheet E1398E40 (Ver. 4.0)
46
EDD51321DBH-TS
Read Timing Definition (2)
/CK
CK
tDQSCK
tAC (min.)
DQS
tAC (min.)
tDSC
Fastest DQ
(Output)
tQH
tDQSQ
Slowest DQ
(Output)
Data valid
window
tDQSCK
tAC (max.)
DQS
tDQSQ
Fastest DQ
(Output)
tQH
tAC (max.)
tQHS
Slowest DQ
(Output)
Data valid
window
BL = 4
= Invalid
Write Timing Definition
tCK
/CK
CK
tDQSS
tDSH
tDSS
tDSS
tDSC
tWPRES
DQS
tDQSL
tWPRE
tDQSH
tWPST
DQ
(Din)
tDS
tDH
tDIPW
tDS
tDH
tDIPW
DM
tDIPW
BL = 4
= Don't care
Preliminary Data Sheet E1398E40 (Ver. 4.0)
47
EDD51321DBH-TS
Initialize Sequence
VDD
VDDQ
/CK
CK
Clock cycle is necessary
CKE
VIH
2 refresh cycles are necessary
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
Address key
Address key
Address
DM
High-Z
DQ, DQS
200µs
VDD/VDDQ
powered up
clock stable
tCK
Precharge
All Banks
Command
is necessary
tRP
tRFC
Auto-Refresh
Command
is necessary
tRFC
Auto-Refresh
Command
is necessary
tMRD
Mode
Register Set
Command
is necessary
tMRD
Extended
Mode
Register Set
Command
is necessary
Activate
Command
= Don't care
Preliminary Data Sheet E1398E40 (Ver. 4.0)
48
EDD51321DBH-TS
Read Cycle
tCK
tCH tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRCD
tRP
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
BA
A10
tIS tIH
Address
DM
DQS (output)
DQ (output)
tRPRE
High-Z
tDSC
tRPST
High-Z
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
Preliminary Data Sheet E1398E40 (Ver. 4.0)
49
CL = 3
BL = 4
Bank0 Access
= Don't care
EDD51321DBH-TS
Write Cycle
tCK
tCH tCL
CK
/CK
tRC
VIH
CKE
tRP
tRAS
tRCD
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
BA
A10
tIS tIH
Address
tDQSS
tDQSL
tWPST
DQS
(input)
tDQSH
tDS
tDS
tDH
DM
tDS
tDH
DQ (input)
tDH
Bank 0
Active
tWR
Bank 0
Write
Bank 0
Precharge
Preliminary Data Sheet E1398E40 (Ver. 4.0)
50
CL = 2
BL = 4
Bank0 Access
= Don't care
EDD51321DBH-TS
Mode Register Set Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
code
Address
C: b
R: b
code
valid
DM
High-Z
DQS
High-Z
b
DQ
tMRD
tRP
Mode
register
set
Precharge
If needed
Bank 3
Read
Bank 3
Active
Bank 3
Precharge
CL = 3
BL = 4
= Don't care
Read/Write Cycle
T0
/CK
CK
CKE
T1
T2
T3
T4
C:a
R:b
T5
T6
T7
T8
T9
T10
T11 Tn
Tn+1 Tn+2 Tn+3 Tn+4
VIH
/CS
/RAS
/CAS
/WE
BA
Address
R:a
C:b''
C:b
DM
DQS
b
a
DQ
Read
tRWD
Bank 0
Active
b’’
Write
Read
tWRD
Bank 0 Bank 3
Read Active
Bank 3
Write
Preliminary Data Sheet E1398E40 (Ver. 4.0)
51
Bank 3
Read
Read cycle
CL = 3
BL = 4
= Don't care
EDD51321DBH-TS
Auto-Refresh Cycle
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
High-Z
DQS
High-Z
DQ
tRP
Precharge
If needed
b
tRFC
Auto
Refresh
Bank 0
Active
Bank 0
Read
CL = 3
BL = 4
= Don't care
Preliminary Data Sheet E1398E40 (Ver. 4.0)
52
EDD51321DBH-TS
Self-Refresh Cycle
/CK
CK
tIS
CKE
tIH
CKE = low
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
Bank 0
Active
Bank 0
Read
DM
DQS
DQ
tRP
Precharge
If needed
tSREX
Self
refresh
entry
Self refresh
exit
BL = 4
= Don't care
Preliminary Data Sheet E1398E40 (Ver. 4.0)
53
EDD51321DBH-TS
Power-Down Entry and Exit
/CK
CK
tIS
tIH
CKE = low
CKE
tCKE
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
R: c
DM
DQS
DQ
tRP
tPDEX
tPDEN
Precharge
If needed
Power down
entry
Power
down
exit
Bank 0
Active
Bank 0
Read
BL = 4
= Don't care
Preliminary Data Sheet E1398E40 (Ver. 4.0)
54
EDD51321DBH-TS
Package Drawing
90-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
8.0 ± 0.1
0.2 S A
13.0 ± 0.1
INDEX MARK
0.2 S B
0.2 S
1.0 max.
S
0.1 S
0.35 ± 0.05
90-φ0.45 ± 0.05
φ0.08 M S A B
0.8
A
11.2
B
INDEX MARK
1.6 0.8
6.4
ECA-TS2-0238-01
Preliminary Data Sheet E1398E40 (Ver. 4.0)
55
EDD51321DBH-TS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD51321DBH.
Type of Surface Mount Device
EDD51321DBH: 90-ball FBGA < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E1398E40 (Ver. 4.0)
56
EDD51321DBH-TS
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E1398E40 (Ver. 4.0)
57
EDD51321DBH-TS
Mobile RAM is a trademark of Elpida Memory, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 ,
SO 2 , and NO x .
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0706
Preliminary Data Sheet E1398E40 (Ver. 4.0)
58