FUJITSU SEMICONDUCTOR DATA SHEET DS07-16303-3E 32-bit RISC Microcontroller CMOS FR30 Series MB91121 MB91121 ■ DESCRIPTION The MB91121 is a microcontroller with a 32-bit RISC CPU (FR family *) as the core, incorporating a variety of I/O resources, a bus control facility, and a multiplier-accumulator (simplified DSP) with internal program RAM for built-in control applications which require advanced, high-speed CPU processing. While being based on external bus access for supporting a vast address space accessed by the 32-bit CPU, it contains 1 K bytes of instruction cache memory and 4 K bytes of RAM (8 K bytes when the DSP is not used) for speeding up the execution of instructions by the CPU. In this way, the device is designed for built-in applications which require high performance and processing power of the CPU, such as digital camera, navigation system, and high-performance FAX, and printer controls. * : FR Family stands for FUJITSU RISC controller. ■ FEATURES 1. FR CPU • • • • • 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) General purpose registers : 32 bits × 16 16-bit fixed length instructions (basic instructions) , 1 instruction/1 cycle Memory to memory transfer, bit processing, barrel shifter processing : Optimized for embedded applications (Continued) ■ PACKAGE 120-pin plastic LQFP (FPT-120P-M21) MB91121 (Continued) • Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages • Register interlock functions, efficient assembly language coding • Branch instructions with delay slots : Reduced overhead time in branch executions • Internal multiplier/supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles • Interrupt (push PC and PS) : 6 cycles, 16 priority levels 2. Bus interface • • • • • • Clock doubler : Internal 50 MHz, external bus 25 MHz operation 25-bit address bus (32 Mbytes memory space) 8/16-bit data bus Basic external bus cycle : 2 clock cycles Chip select outputs for setting down to a minimum memory block size of 64 Kbytes : 6 Interface supported for various memory technologies DRAM interface (area 4 and 5) • Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area • Unused data/address pins can be configured as input/output ports. • Little endian mode supported (Select 1 area from area 1 to 5) 3. DRAM interface • • • • • 2 banks independent control (area 4 and 5) Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM Basic bus cycle : Normally 5 cycles, 2-cycle access possible in high-speed page mode Programmable waveform : Automatic 1-cycle wait insertion to RAS and CAS cycles DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode • Supports 8/9/10/12-bit column address width • 2CAS/1WE, 2WE/1CAS selective 4. DSP Macros (Simplified DSP) • • • • • • • • • • • High-speed multiply-accumulate operation (1 machine cycle) Data format : 16-bit fixed-point (16 × 16 + 40 bits) Instruction area : 256 words × 16 bits Data area : 64 words × 16 bits × 1 set, 1024 words × 16 bits × 2 sets (banks) Capable of rounding and saturation processing Number of terms in addition : Up to 32 terms Instructions : MAC, STR, and JMP instructions Delay processing : Capable of free transfer within 32 words Fixed-point system : Capable of selection from among Q12 to Q15 Program execution control : Capable of externally selecting eight calculation programs Variable monitoring : Capable of monitoring calculation results of up to 4 words without stopping the program • Efficient data variable areas : Two banks of data variable areas provided, enabling the CPU to execute a DSP calculation program using one bank while accessing a data variable in the other. 5. Cache memory • 1 K-byte instruction cache • 2-way set-associative configuration • 32 blocks/way, 4 entries (4 words) /block 2 MB91121 (Continued) • Lock feature: Keeping a specific program code resident in the cache 6. DMAC (DMA Controller) • • • • • 8 channels Transfer incident/external pins/UART interrupt requests/DSP Macros/Software start Transfer sequence : Step transfer/block transfer/burst transfer/continuous transfer Transfer data length : 8 bits/16 bits/32 bits selective Interrupt request enables temporary stop operation 7. UART • • • • • • • • 3 independent channels Full-duplex double buffer Data length : 7 bits to 9 bits (non-parity) , 6 bits to 8 bits (parity) Asynchronous (start-stop system) , CLK-synchronized communication selective Multi-processor mode Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator : Generates any given baud rate Use external clock can be used as a transfer clock Error detection : Parity, frame, overrun 8. A/D converter (successive approximation conversion type) • • • • • 9. 10-bit resolution, 8 channels Successive approximation type : Conversion time of 5.6 µs at 25 MHz Internal sample and hold circuit Conversion mode : Single conversion/scanning conversion/repeated conversion selective Start : Software/external trigger/internal timer selective Reload timer • 16-bit timer : 3 channels • Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective 10. Other interval timers • 16-bit timer : 3 channels (U-TIMER) • PWM timer : 4 channels • Watchdog timer : 1 channel 11. Bit search module • First bit transition “1” or “0” from MSB can be detected in 1 cycle 12. Interrupt controller • External interrupt input : Non-maskable interrupt (NMI) , normal interrupt × 8 (INT0 to INT7) • Internal interrupt incident : UART, DMA controller (DMAC) , A/D converter, U-TIMER, delayed interrupt module and DSP Macros • Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) . Others 1. Reset cause • Power-on reset/watchdog timer/software reset/external reset 2. Low-power consumption mode • Sleep mode/stop mode 3. Clock control • Gear function : Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) However, operating frequency for peripherals is less than 25 MHz. 3 MB91121 (Continued) 4. Packages : LQFP-120 5. CMOS technology (0.35 µm) 6. Power supply voltage 3.3 V ± 0.3 V 4 MB91121 ■ PIN ASSIGNMENT 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 RAS1/PB4 DW0/PB3 CSOH/PB2 CSOL/PB1 RAS0/PB0 VCC X0 X1 VSS PI1/EOP2/ATG PI0/DACK2 PE7/DREQ2 PE6/EOP1 PE5/DACK1 PE4/DREQ1 PE3/EOP0 PE2/DACK0 PE1/DREQ0 PE0/SC2 PF7/SO2 PF6/SI2 PF5/SC1 PF4/SO1 PF3/SI1 PF2/SC0 PF1/SO0 VSS PF0/SI0 PG7/INT7/TRG3 PG6/INT6/TRG2 (TOP VIEW) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PG5/INT5/TRG1 PG4/INT4/TRG0 PG3/INT3 PG2/INT2 PG1/INT1 PG0/INT0 VCC PH7/OCPA3 PH6/OCPA2 PH5/OCPA1 PH4/OCPA0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 P26/D22 P27/D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS A00 A01 A02 A03 A04 A05 A06 A07 VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60/A16 PB5/CS1L PB6/CS1H PB7/DW1 VCC CS0 PA1/CS1 PA2/CS2 PA3/CS3 PA4/CS4 PA5/CS5 PA6/CLK NMI MD3 RST VSS MD0 MD1 MD2 P80/RDY P81/BGRNT P82/BRQ RD WR0 P85/WR1 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 (FPT-120P-M21) 5 MB91121 ■ PIN DESCRIPTION Pin no. Pin name Circuit type Function 1 2 3 4 5 6 7 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 F Bits 16 to 23 for the external address bus. When not used for the address bus, these pins serve as ports (P60 to P67) . 8 A24 M Bit 24 for the external address bus 9 AVCC A/D converter VCC power supply 10 AVRH A/D converter reference voltage (high potential side) The VCC pin must be applied with voltage equal to or higher than the voltage at this pin (AVRH) when the AVRH pin is turned on or off. 11 AVSS/AVRL A/D converter VSS power supply or reference voltage (low potential side) 12 to 19 AN0 to AN7 N [AN0 to AN7] A/D converter analog input. This function is enabled with the AIC register set for the analog input. 20 to 23 OCPA0/PH4 OCPA1/PH5 OCPA2/PH6 OCPA3/PH7 25 to 32 33 INT0/PG0 INT1/PG1 INT2/PG2 INT3/PG3 INT4/PG4/TRG0 INT5/PG5/TRG1 INT6/PG6/TRG2 INT7/PG7/TRG3 SI0/PF0 F [OCPA0 to OCPA3] PWM timer output. This function is enabled with the PWM timer output flag set to “Enabled”. [PH4 to PH7] General-purpose I/O port [INT0 to INT7] External interrupt request input F [TRG0 to TRG3] PWM timer external trigger input Since these inputs are used during their respective input operations, the output by the other function must remain off unless used intentionally. [PG0 to PG7] General-purpose I/O port F [SI0] UART0 data input. Since this input is used whenever UART0 is in input operation, the output by the other function must remain off unless used intentionally. [PF0] General-purpose I/O port 35 36 SO0/PF1 SC0/PF2 F F [SO0] UART0 data output. This function is enabled with the UART0 data output flag set to “Enabled”. [PF1] General-purpose I/O port. This function is enabled with the UART0 data output flag set to “Disabled”. [SC0] UART0 clock input/output. The clock output is enabled with the UART0 clock output flag set to “Enabled”. [PF2] General-purpose I/O port. This function is enabled with the UART0 clock output flag set to “Disabled”. (Continued) 6 MB91121 (Continued) Pin no. 37 Pin name SI1/PF3 Circuit type Function F [SI1] UART1 data input. Since this input is used whenever UART1 is in input operation, the output by the other function must remain off unless used intentionally. [PF3] General-purpose I/O port 38 39 40 SO1/PF4 SC1/PF5 SI2/PF6 F F F [SO1] UART1 data output. This function is enabled with the UART1 data output flag set to “Enabled”. [PF4] General-purpose I/O port. This function is enabled with the UART1 data output flag set to “Disabled”. [SC1] UART1 clock input/output. The clock output is enabled with the UART1 clock output flag set to “Enabled”. [PF5] General-purpose I/O port. This function is enabled with the UART1 clock output flag set to “Disabled”. [SI2] UART2 data input. Since this input is used whenever UART2 is in input operation, the output by the other function must remain off unless used intentionally. [PF6] General-purpose I/O port 41 42 43 SO2/PF7 SC2/PE0 DREQ0/PE1 F F F [SO2] UART2 data output. This function is enabled with the UART2 data output flag set to “Enabled”. [PF7] General-purpose I/O port. This function is enabled with the UART2 data output flag set to “Disabled”. [SC2] UART2 clock input/output. The clock output is enabled with the UART2 clock output flag set to “Enabled”. [PE0] General-purpose I/O port. This function is enabled with the UART2 clock output flag set to “Disabled”. [DREQ0] DMA external transfer request input (ch0) . Since this input is used whenever the DMA external transfer request has been selected as a DMA transfer trigger event, the output by the other function must remain off unless used intentionally. [PE1] General-purpose I/O port 44 DACK0/PE2 F 45 EOP0/PE3 F [DACK0] DMAC external transfer request acknowledge output (ch0) . This function is enabled with the DMAC transfer request acknowledge output flag set to “Enabled”. [PE2] General-purpose I/O port. This function is enabled with the DMAC transfer request acknowledge output flag or DACK0 output flag set to “Disabled”. [EOP0] DMAC EOP output (ch0) . This function is enabled with the EOP output flag set to “Enabled”. [PE3] General-purpose I/O port 46 DREQ1/PE4 F [DREQ1] DMA external transfer request input (ch1) . Since this input is used whenever the DMA external transfer request has been selected as a DMA transfer trigger event, the output by the other function must remain off unless used intentionally. [PE4] General-purpose I/O port (Continued) 7 MB91121 (Continued) Pin no. 47 48 Pin name DACK1/PE5 EOP1/PE6 Circuit type F F Function [DACK1] DMAC external transfer request acknowledge output (ch1) . This function is enabled with the DMAC transfer request acknowledge output flag set to “Enabled”. [PE5] General-purpose I/O port. This function is enabled with the DMAC transfer request acknowledge output flag or DACK0 output flag set to “Disabled”. [EOP1] DMAC EOP output (ch1) . This function is enabled with the EOP output flag set to “Enabled”. [PE6] General-purpose I/O port 49 DREQ2/PE7 F [DREQ2] DMA external transfer request input (ch2) . Since this input is used whenever the DMA external transfer request has been selected as a DMA transfer trigger event, the output by the other function must remain off unless used intentionally. [PE7] General-purpose I/O port 50 DACK2/PI0 F [DACK2] DMAC external transfer request acknowledge output (ch2) . This function is enabled with the DMAC transfer request acknowledge output flag set to “Enabled”. [PI0] General-purpose I/O port. This function is enabled with the DMAC transfer request acknowledge output flag or DACK0 output flag set to "Disabled". [EOP2] DMAC EOP output (ch2) . This function is enabled with the EOP output flag set to “Enabled”. 51 EOP2/ATG/PI1 F [ATG] A/D converter external trigger input. Since this input is used whenever the A/D converter external trigger signal has been selected as an A/D trigger event, the output by the other function must remain off unless used intentionally. [PI1] General-purpose I/O port. This function is enabled with the DMAC transfer termination signal output flag set to “Disabled”. 53 54 X1 X0 56 57 58 59 60 RAS0/PB0 CSOL/PB1 CSOH/PB2 DW0/PB3 RAS1/PB4 61 62 63 CS1L/PB5 CS1H/PB6 DW1/PB7 F 65 CS0 M A F Clock (oscillation) output. Clock (oscillation) input. RAS output of DRAM bank 0 CASL output of DRAM bank 0 CASH output of DRAM bank 0 WE output of DRAM bank 0 (Low active) RAS output of DRAM bank 1 [PB0 to PB3] Can serve as a port when not used for signal output. CASL output of DRAM bank 1 CASH output of DRAM bank 1 WE output of DRAM bank 1 (Low active) [PB5 to PB7] Can serve as a port when not used for signal output. Chip select 0 output (Low active) . (Continued) 8 MB91121 (Continued) Pin no. 66 67 68 69 70 71 Pin name CS1/PA1 CS2/PA2 CS3/PA3 CS4/PA4 CS5/PA5 CLK/PA6 Circuit type F Function Chip select 1 output (Low active) . Chip select 2 output (Low active) . Chip select 3 output (Low active) . Chip select 4 output (Low active) . Chip select 5 output (Low active) . [PA1 to PA5] Can serve as a port when not used for signal output. F System clock output. This pin outputs the same clock frequency as the external bus operating frequency. [PA6] Can serve as a port when not used for signal output. 72 NMI H NMI (Non Maskable Interrupt) input (Low active) . 73 MD3 G Mode pin 3. Connect this pin directly to the VCC or VSS pin. 74 RST B External reset input. 76 77 78 MD0 MD1 MD2 G Mode pins 0 to 2. These pins are set to MCU basic operation modes. Connect this pin directly to the VCC or VSS pin. 79 RDY/P80 C External ready signal input. This pin inputs 0 when the bus cycle being executed is not completed. It can serve as a port when not used for that input. 80 BGRNT/P81 F External bus release request acknowledge output. This pin outputs the L signal when the eternal bus has been released. The pin can serve as a port when not used for that output. 81 BRQ/P82 C External bus release request input. Input 1 to this pin to release the external bus. The pin can serve as a port when not used for that input. 82 RD M External bus read strobe. 83 WR0 M External bus write strobe. The control signals and data bus byte locations have the following relationships. 84 WR1/P85 F 16-bit bus width 8-bit bus width D31 to D24 WR0 WR0 D23 to D16 WR1 (Usable as port) Note : WR1 remains in the Hi-Z state during a reset. For use with a 16-bit bus width, add an external pull-up resistor. 85 86 87 88 89 90 91 92 D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 C External data bus bits 16 to 23. These pins can be used as ports (P20 to P27) when the external bus width has been set to 8 bits. (Continued) 9 MB91121 (Continued) Pin no. Pin name Circuit type Function 93 94 95 96 97 98 99 100 D24 D25 D26 D27 D28 D29 D30 D31 C External data bus bits 24 to 31. 102 103 104 105 106 107 108 109 111 112 113 114 115 116 117 118 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 F External address bus bits 00 to 15. 120 A16/P60 24 55 64 110 VCC Power supply pin for digital circuit. 34 52 75 101 119 VSS Earth level for digital circuit. External address bus bit 16. This pin can serve as a port (P60) when not used as the address bus. Note : In most of the above pins, I/O port and resource I/O are multiplexed xxxx/Pxx. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O. 10 MB91121 ■ DRAM CONTROL PIN Pin name Data bus 16-bit mode 2CAS/1WR mode 1CAS/2WR mode Data bus 8-bit mode RAS0 Area 4 RAS Area 4 RAS Area 4 RAS RAS1 Area 5 RAS Area 5 RAS Area 5 RAS CS0L Area 4 CASL Area 4 CAS Area 4 CAS CS0H Area 4 CASH Area 4 WEL Area 4 CAS CS1L Area 5 CASL Area 5 CAS Area 5 CAS CS1H Area 5 CASH Area 5 WEL Area 5 CAS DW0 Area 4 WE Area 4 WEH Area 4 WE DW1 Area 5 WE Area 5 WEH Area 5 WE Remarks Correspondence of “L” “H” to lower address 1 bit (A0) in data bus 16-bit mode “L” : “0” “H” : “1” CASL : CAS which A0 corresponds to “0” area CASH : CAS which A0 corresponds to “1” area WEL : WE which A0 corresponds to “0” area WEH : WE which A0 corresponds to “1” area 11 MB91121 ■ I/O CIRCUIT TYPE Circuit Type Circuit Remarks X1 Clock input A • Oscillation feedback resistance 1 MΩ approx. X0 Standby control signal VCC P-channel type Tr B Diffuse resistor N-channel type Tr • CMOS level Hysteresis input Without standby control With pull-up resistance VSS Digital input Digital output Digital output C • CMOS level I/O With standby control Digital input STANDBY CONTROL • Analog input N Analog input (Continued) 12 MB91121 (Continued) Circuit Type Circuit Remarks Digital output Digital output F Digital input • CMOS level output • CMOS level Hysteresis input With standby control STANDBY CONTROL • CMOS level input Without standby control G Digital input • CMOS level Hysteresis input Without standby control H Digital input Digital output • CMOS level output M Digital output 13 MB91121 ■ HANDLING DEVICES • Preventing Latchup In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. Take care that the analog power supply (AVCC AVR) and the analog input do not exceed the digital power supply (VCC) when the analog power supply turned on or off. • Treatment of Unused Pins Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors. • External Reset Input It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly. • Remarks for External Clock Operation When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at “H” output in stop mode) . And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than. • Using an external clock X0 X1 MB91121 Using an external clock (normal) Note: Can not be used stop mode (oscillation stop mode). X0 OPEN X1 MB91121 Using an external clock (can be used at 12.5 MHz and less than.) • Power Supply Pins When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND. It is preferred to connect VCC and VSS of MB91121 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC and VSS at a position as close as possible to MB91121. 14 MB91121 • Crystal Oscillator Circuit Noises around X0 and X1 pins may cause malfunctions of MB91121. In designing the PC board, layout X0, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for stable operation. • Treatment of N.C. Pins Make sure to leave N.C. pins open. • Mode Setting Pins (MD0 to MD3) Connect mode setting pins (MD0 to MD3) directly to VCC or VSS. Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. • Turning on the Power Supply When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to “H” level. • Pin Condition at Turning on the Power Supply The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation becomes stable. • Source Oscillation Input at Turning on the Power Supply At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. • The device contains registers which are initialized only at a power-on reset. When it is expected to initialize them, recycle the power to execute a power-on reset. • Even when the A/D converter is not used, make the connections : AVCC = VCC, AVSS = VSS. • Caution on operations during PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 15 MB91121 ■ BLOCK DIAGRAM FR CPU 3 3 3 DREQ0 to DREQ2 DACK0 to DACK2 EOP0 to EOP2 DMAC (8 ch) D -bus (32 bit) Bit Search Module I -bus (16 bit) RAM (4 KB) Instruction Cache (1 KB) Bus Converter (Harvard↔Princeton) 16 25 DSP macro (Embedded RAM 4 ) 2 Bus Converter (32 bit ↔16 bit) Bus Controller 6 X0 X1 RST 8 Interrupt Control Unit C-bus (32 bit) AN0 to AN7 AVCC AVRH AVSS /AVRL Clock Control Unit (Watct Dog Timer) 8 RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1 DRAM Controller 10 bit A/D Converter (8 ch) Reload Timer (3 ch) R -bus (16 bit) INT0 to INT7 NMI D16 to D31 A00 to A24 RDY WR0 to WR1 RDY CLK CS0 to CS5 BRQ BGRNT Port 0 to Port B STRG Soft DMA Start Circuit Port 3 UART (3 ch) with Baud Rate Timer PWM Timer (4 ch) 3 3 4 4 SI0 to SI2 SO0 to SO2 SC0 to SC2 OCPA0 to OCPA3 TRG0 to TRG3 Note : Pins are display for functions (Actually some pins are multiplexer) . When using REALOS, time control should be done by using external interrupt or inner timer. 16 MB91121 ■ CPU CORE 1. Memory Space The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory space. • Memory space External ROM/external bus mode 0000 0000H I/O 0000 0400H I/O Direct addressing area See “■ I/O MAP” 0000 0800H Access inhibited 0000 1000H Embedded RAM 4 KB 0000 2000H Y-RAM1 ←Usable as RAM in the DSP Macros YBANK unused mode. Y-RAM1 ←Usable as RAM when DSP Macros is not used. 0000 2800H 0000 3000H Access inhibited 0000 F000H DSP Macros 0000 F300H Access inhibited 0001 0000H External area FFFF FFFFH • Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consist of the following areas dependent on accessible data sizes. Byte data access : 000H to 0FFH Half word data access : 000H to 1FFH Word data access : 000H to 3FFH 17 MB91121 2. Registers The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. • Dedicated registers Program counter (PC) Program status (PS) Table base register (TBR) : 32-bit length, indicates the location of the instruction to be executed. : 32-bit length, register for storing register pointer or condition codes : Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) processing. Return pointer (RP) : Holds address to resume operation after returning from a subroutine. System stack pointer (SSP) : Indicates system stack space. User’s stack pointer (USP) : Indicates user’s stack space. Multiplication/division result register (MDH/MDL) : 32-bit length, register for multiplication/division Initial value 32 bit PC Program counter PS Program status TBR XXXX XXXXH Indeterminate Table base register 0 0 0 F FC0 0H Return pointer XXXX XXXXH Indeterminate SSP System stack pointer 0 0 0 0 0 0 0 0H USP User’s stack pointer XXXX XXXXH Indeterminate RP XXXX XXXXH Indeterminate MDH Multiplication/division result register MDL XXXX XXXXH Indeterminate • Program status (PS) The PS register is for holding program status and consists of a condition code register (CCR) , a system condition code register (SCR) and a interrupt level mask register (ILM) . 31 PS 20 19 18 16 ILM4 ILM3 ILM2 ILM1 ILM0 ILM 18 17 10 9 8 7 6 5 4 3 2 1 0 D1 D0 T S I N Z V C SCR CCR MB91121 • Condition code register (CCR) S-flag : Specifies a stack pointer used as R15. I-flag : Controls user interrupt request enable/disable. N-flag : Indicates sign bit when division result is assumed to be in the 2’s complement format. Z-flag : Indicates whether or not the result of division was “0”. V-flag : Assumes the operand used in calculation in the 2’s complement format and indicates whether or not overflow has occurred. C-flag : Indicates if a carry or borrow from the MSB has occurred. • System condition code register (SCR) T-flag : Specifies whether or not to enable step trace trap. • Interrupt level mask register (ILM) ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 ILM3 ILM2 ILM1 ILM0 Interrupt level High-low 0 0 0 0 0 : : 0 1 0 1 1 High : : 0 0 : : 1 0 15 : : 1 1 31 Low 19 MB91121 ■ GENERAL-PURPOSE REGISTERS R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address) . • Register bank structure 32 bits R0 R1 R12 R13 R14 R15 AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer) Initial value XXXX XXXXH XXXX XXXXH 0 0 0 0 0 0 0 0H Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP) Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value) . 20 MB91121 ■ SETTING MODE 1. Pin • Mode setting pins and modes Mode setting pins Mode name MD3 MD2 MD1 MD0 Reset vector access area External data bus width Bus mode 1 0 0 0 External vector mode 0 External 8 bits 1 0 0 1 External vector mode 1 External 16 bits 1 0 1 0 1 0 1 1 Internal vector mode Internal (Mode register) 1 1 Inhibited 0 Inhibited External ROM/external bus mode Inhibited Single-chip mode* * : MB91121 does not support single-chip mode. 2. Registers • Mode setting registers (MODR) and modes Address 0000 07FFH M1 M0 * * * * * * Initial value Access XXXX XXXXB W Bus mode setting bit W : Write only X : Indeterminate * : Always write “0” except for M1 and M0. • Bus mode setting bits and functions M1 M0 Functions 0 0 Single-chip mode 0 1 Internal ROM/external bus mode 1 0 External ROM/external bus mode 1 1 Note Inhibited Note : Because of without internal ROM, MB91121 allows “10B” setting value only. 21 MB91121 ■ I/O MAP Address Register name (abbreviated) Register name 0000H 0001H Initial value R/W XXXXXXXXB R/W XXXXXXXXB (Vacancy) PDR2 Port 2 data register 0002H to 0004H 0005H Read/write (Vacancy) PDR6 Port 6 data register 0006H (Vacancy) 0007H 0008H PDRB Port B data register R/W XXXXXXXXB 0009H PDRA Port A data register R/W −XXXXXX −B R/W − −X − −XXXB 000AH 000BH (Vacancy) PDR8 Port 8 data register 000CH to 0011H (Vacancy) 0012H PDRE Port E data register R/W XXXXXXXXB 0013H PDRF Port F data register R/W XXXXXXXXB 0014H PDRG Port G data register R/W XXXXXXXXB 0015H PDRH Port H data register R/W XXXX − − − −B 0016H PDRI Port I data register R/W − − − − − − XXB 0017H to 001BH (Vacancy) 001CH SSR0 Serial status register 0 R/W 0 0 0 0 1 − 0 0B 001DH SIDR0/SODR0 Serial input register 0/serial output register 0 R/W XXXXXXXXB 001EH SCR0 Serial control register 0 R/W 0 0 0 0 0 1 0 0B 001FH SMR0 Serial mode register 0 R/W 0 0 − − 0 − 0 0B 0020H SSR1 Serial status register 1 R/W 0 0 0 0 1 − 0 0B 0021H SIDR1/SODR1 Serial input register 1/serial output register 1 R/W XXXXXXXXB 0022H SCR1 Serial control register 1 R/W 0 0 0 0 0 1 0 0B 0023H SMR1 Serial mode register 1 R/W 0 0 − − 0 − 0 0B 0024H SSR2 Serial status register 2 R/W 0 0 0 0 1 − 0 0B 0025H SIDR2/SODR2 Serial input register 2/serial output register 2 R/W XXXXXXXXB 0026H SCR2 Serial control register 2 R/W 0 0 0 0 0 1 0 0B 0027H SMR2 Serial mode register 2 R/W 0 0 − − 0 − 0 0B (Continued) 22 MB91121 Address 0028H 0029H 002AH 002BH Register name (abbreviated) Register name TMRLR0 16-bit reload register ch. 0 W TMR0 16-bit timer register ch. 0 R 002CH 002FH 0030H 0031H 0032H 0033H TMCSR0 16-bit reload timer control status register ch. 0 TMRLR1 16-bit reload register ch. 1 W TMR1 16-bit timer register ch. 1 R 0034H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 16-bit reload timer control status register ch. 1 ADCR A/D converter data register ADCS A/D converter control status register TMRLR2 16-bit reload register ch. 2 W TMR2 16-bit timer register ch. 2 R TMCSR2 16-bit reload timer control status register ch. 2 0044H to 004FH 0050H 0051H to 0077H XXXXXXXXB XXXXXXXXB XXXXXXXXB − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W R R/W − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B − − − − − − XXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Vacancy) 0041H 0043H R/W TMCSR1 0040H 0042H XXXXXXXXB (Vacancy) 0035H 0036H Initial value (Vacancy) 002DH 002EH Read/write R/W − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B (Vacancy) STRG Soft DMA Start R/W − − − − − − 0 0B (Vacancy) (Continued) 23 MB91121 Address 0078H 0079H Register name (abbreviated) UTIM0/UTIMR0 Register name U-TIMER register ch. 0/reload register ch. 0 007AH 007BH 007CH 007DH 0080H 0081H UTIMC0 U-TIMER control register ch. 0 R/W UTIM1/UTIMR1 U-TIMER register ch. 1/reload register ch. 1 R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 − − 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Vacancy) UTIMC1 U-TIMER control register ch. 1 R/W UTIM2/UTIMR2 U-TIMER register ch. 2/reload register ch. 2 R/W 0082H 0083H R/W Initial value (Vacancy) 007EH 007FH Read/write 0 − − 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Vacancy) UTIMC2 U-TIMER control register ch. 2 0084H to 0093H R/W 0 − − 0 0 0 0 1B (Vacancy) 0094H EIRR External interrupt cause register R/W 0 0 0 0 0 0 0 0B 0095H ENIR Interrupt enable register R/W 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B 0096H to 0097H 0098H 0099H (Vacancy) ELVR 009AH to 00D1H External interrupt request level setting register (Vacancy) 00D2H DDRE Port E data direction register W 0 0 0 0 0 0 0 0B 00D3H DDRF Port F data direction register W 0 0 0 0 0 0 0 0B 00D4H DDRG Port G data direction register W 0 0 0 0 0 0 0 0B 00D5H DDRH Port H data direction register W 0 0 0 0 − − − −B 00D6H DDRI Port I data direction register W − − − − − − 0 0B 00D7H to 00DBH 00DCH 00DDH (Vacancy) GCN1 00DEH 00DFH General control register 1 R/W 0 0 1 1 0 0 1 0B 0 0 0 1 0 0 0 0B (Vacancy) GCN2 General control register 2 R/W 0 0 0 0 0 0 0 0B (Continued) 24 MB91121 Address 00E0H Register name (abbreviated) Register name Read/write Initial value 1 1 1 1 1 1 1 1B PTMR0 PWM timer register R PCSR0 PWM cycle setting register W PDUT0 PWM duty setting register W 00E6H PCNH0 PWM control status register H R/W 0 0 0 0 0 0 0 −B 00E7H PCNL0 PWM control status register L R/W 0 0 0 0 0 0 0 0B PTMR1 PWM timer register R PCSR1 PWM cycle setting register W PDUT1 PWM duty setting register W 00EEH PCNH1 PWM control status register H R/W 0 0 0 0 0 0 0 −B 00EFH PCNL1 PWM control status register L R/W 0 0 0 0 0 0 0 0B PTMR2 PWM timer register R PCSR2 PWM cycle setting register W PDUT2 PWM duty setting register W 00F6H PCNH2 PWM control status register H R/W 0 0 0 0 0 0 0 −B 00F7H PCNL2 PWM control status register L R/W 0 0 0 0 0 0 0 0B PTMR3 PWM timer register R PCSR3 PWM cycle setting register W PDUT3 PWM duty setting register W 00FEH PCNH3 PWM control status register H R/W 0 0 0 0 0 0 0 −B 00FFH PCNL3 PWM control status register L R/W 0 0 0 0 0 0 0 0B 00E1H 00E2H 00E3H 00E4H 00E5H 00E8H 00E9H 00EAH 00EBH 00ECH 00EDH 00F0H 00F1H 00F2H 00F3H 00F4H 00F5H 00F8H 00F9H 00FAH 00FBH 00FCH 00FDH 0100H to 01FFH 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Vacancy) (Continued) 25 MB91121 Address Register name (abbreviated) Register name Read/write XXXXXXXXB 0200H 0201H 0202H Initial value DPDP DMAC parameter descriptor pointer R/W XXXXXXXXB XXXXXXXXB 0203H X0 0 0 0 0 0 0B 0204H 0 0 0 0 0 0 0 0B 0205H 0206H DACSR DMAC control status register R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0207H 0 0 0 0 0 0 0 0B 0208H XXXXXXXXB 0209H 020AH DATCR DMAC pin control register R/W 020BH 0211H 0212H 0213H 0214H XXXX0 0 0 0B XXXX0 0 0 0B 020CH to 020FH 0210H XXXX0 0 0 0B (Vacancy) − − − − 0 0 0 0B OFAS STRS 0 0 0 0 0 0 0 0B DSP macro register R/W − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 − − − 0B OFSC 0215H (Vacancy) 0216H OFSS R/W 0 0 0 0 0 0 0 0B 0217H Y-BANKC R/W 0 − − 0 0 0 0 0B OFSD R/W 021AH DSP-PC R/W XXXXXXXXB 021BH DSP-CSR R/W 0 0 0 0 0 0 0 0B 0218H 0219H 021CH 021DH 021EH 021FH 0220H 0221H 0222H 0223H DSP-LY DSP macro register R/W DSP-OT0 R DSP-OT1 R DSP-OT2 R 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 26 MB91121 Address 0224H 0225H Register name (abbreviated) DSP-OT3 0226H to 03E3H Register name DSP macro register Read/write R 03E6H ICHCR Instruction cache control register R/W − − − − − − − −B − − − − − − − −B − − 0 0 0 0 0 0B 03E8H to 03EFH (Vacancy) XXXXXXXXB 03F0H 03F2H XXXXXXXXB − − − − − − − −B 03E7H 03F1H XXXXXXXXB (Vacancy) 03E4H 03E5H Initial value BSD0 Bit search module 0-detection data register W XXXXXXXXB XXXXXXXXB 03F3H XXXXXXXXB 03F4H XXXXXXXXB 03F5H 03F6H BSD1 Bit search module 1-detection data register R/W XXXXXXXXB XXXXXXXXB 03F7H XXXXXXXXB 03F8H XXXXXXXXB 03F9H 03FAH BSDC Bit search module transition-detection data register W XXXXXXXXB XXXXXXXXB 03FBH XXXXXXXXB 03FCH XXXXXXXXB 03FDH 03FEH BSRR Bit search module detection result register R 03FFH XXXXXXXXB XXXXXXXXB XXXXXXXXB 0400H ICR00 Interrupt control register 0 R/W − − − 1 1 1 1 1B 0401H ICR01 Interrupt control register 1 R/W − − − 1 1 1 1 1B 0402H ICR02 Interrupt control register 2 R/W − − − 1 1 1 1 1B 0403H ICR03 Interrupt control register 3 R/W − − − 1 1 1 1 1B 0404H ICR04 Interrupt control register 4 R/W − − − 1 1 1 1 1B 0405H ICR05 Interrupt control register 5 R/W − − − 1 1 1 1 1B 0406H ICR06 Interrupt control register 6 R/W − − − 1 1 1 1 1B 0407H ICR07 Interrupt control register 7 R/W − − − 1 1 1 1 1B (Continued) 27 MB91121 Address Register name (abbreviated) Register name Read/write Initial value 0408H ICR08 Interrupt control register 8 R/W − − − 1 1 1 1 1B 0409H ICR09 Interrupt control register 9 R/W − − − 1 1 1 1 1B 040AH ICR10 Interrupt control register 10 R/W − − − 1 1 1 1 1B 040BH ICR11 Interrupt control register 11 R/W − − − 1 1 1 1 1B 040CH ICR12 Interrupt control register 12 R/W − − − 1 1 1 1 1B 040DH ICR13 Interrupt control register 13 R/W − − − 1 1 1 1 1B 040EH ICR14 Interrupt control register 14 R/W − − − 1 1 1 1 1B 040FH ICR15 Interrupt control register 15 R/W − − − 1 1 1 1 1B 0410H ICR16 Interrupt control register 16 R/W − − − 1 1 1 1 1B 0411H ICR17 Interrupt control register 17 R/W − − − 1 1 1 1 1B 0412H ICR18 Interrupt control register 18 R/W − − − 1 1 1 1 1B 0413H ICR19 Interrupt control register 19 R/W − − − 1 1 1 1 1B 0414H ICR20 Interrupt control register 20 R/W − − − 1 1 1 1 1B 0415H ICR21 Interrupt control register 21 R/W − − − 1 1 1 1 1B 0416H ICR22 Interrupt control register 22 R/W − − − 1 1 1 1 1B 0417H ICR23 Interrupt control register 23 R/W − − − 1 1 1 1 1B 0418H ICR24 Interrupt control register 24 R/W − − − 1 1 1 1 1B 0419H ICR25 Interrupt control register 25 R/W − − − 1 1 1 1 1B 041AH ICR26 Interrupt control register 26 R/W − − − 1 1 1 1 1B 041BH ICR27 Interrupt control register 27 R/W − − − 1 1 1 1 1B 041CH ICR28 Interrupt control register 28 R/W − − − 1 1 1 1 1B 041DH ICR29 Interrupt control register 29 R/W − − − 1 1 1 1 1B 041EH ICR30 Interrupt control register 30 R/W − − − 1 1 1 1 1B 041FH ICR31 Interrupt control register 31 R/W − − − 1 1 1 1 1B 0420H to 042EH ICR32 to ICR46 Interrupt control register 32 to 46 R/W − − − 1 1 1 1 1B 042FH ICR47 Interrupt control register 47 R/W − − − 1 1 1 1 1B 0430H DICR Delayed interrupt control register R/W − − − − − − − 0B 0431H HRCL Hold request cancel request level setting register R/W − − − 1 1 1 1 1B 0432H to 047FH (Vacancy) 0480H RSRR/WTCR Reset cause register/ watchdog peripheral control register R/W 1XXXX − 0 0B 0481H STCR Standby control register R/W 0 0 0 1 1 1 − −B 0482H PDRR DMA controller request squelch register R/W − − − − 0 0 0 0B (Continued) 28 MB91121 Address Register name (abbreviated) Register name 0483H CTBR Timebase timer clear register 0484H GCR Gear control register 0485H WPR Watchdog reset occurrence postpone register 0486H PCTR PLL control register 0489H to 0600H 0601H W XXXXXXXXB R/W 1 1 0 0 1 1 − 1B W XXXXXXXXB R/W 0 0 − − 0 − − −B W 0 0 0 0 0 0 0 0B W 0 0 0 0 0 0 0 0B (Vacancy) DDR2 Port 2 data direction register 0602H to 0604H 0605H Initial value (Vacancy) 0487H 0488H Read/write (Vacancy) DDR6 Port 6 data direction register 0606H (Vacancy) 0607H 0608H DDRB Port B data direction register W 0 0 0 0 0 0 0 0B 0609H DDRA Port A data direction register W − 0 0 0 0 0 0 −B − − 0 − − 0 0 0B 060AH 060BH 060CH 060DH 060EH 060FH 0610H 0611H 0612H 0613H 0614H 0615H 0616H 0617H 0618H 0619H 061AH 061BH (Vacancy) DDR8 Port 8 data direction register W ASR1 Area select register 1 W AMR1 Area mask register 1 W ASR2 Area select register 2 W AMR2 Area mask register 2 W ASR3 Area select register 3 W AMR3 Area mask register 3 W ASR4 Area select register 4 W AMR4 Area mask register 4 W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued) 29 MB91121 (Continued) Address 061CH Register name (abbreviated) Register name Initial value 0 0 0 0 0 0 0 0B ASR5 Area select register 5 W AMR5 Area mask register 5 W 0620H AMD0 Area mode register 0 R/W − − − 0 0 1 1 1B 0621H AMD1 Area mode register 1 R/W 0 − − 0 0 0 0 0B 0622H AMD32 Area mode register 32 R/W 0 0 0 0 0 0 0 0B 0623H AMD4 Area mode register 4 R/W 0 − − 0 0 0 0 0B 0624H AMD5 Area mode register 5 R/W 0 − − 0 0 0 0 0B 0625H DSCR DRAM signal control register W 0 0 0 0 0 0 0 0B RFCR Refresh control register EPCR0 External pin control register 0 061DH 061EH 061FH 0626H 0627H 0628H 0629H 062AH 062BH 062CH 062DH 062EH 062FH R/W W 0 0 0 0 0 1 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B − −XXXXXXB 0 0 − − − 0 0 0B − − − − 1 1 0 0B − 1 1 1 1 1 1 1B (Vacancy) EPCR1 External pin control register 1 DMCR4 DRAM control register 4 R/W DMCR5 DRAM control register 5 R/W 0630H to 07FDH W 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B (Vacancy) 07FEH LER Little endian register W − − − − − 0 0 0B 07FFH MODR Mode register W XXXXXXXXB 002000H to 002FFFH Y-RAM (Variable RAM) 4096 byte (Max.) 00F000H to 00F07FH X-RAM (Coefficient RAM) DSP macro RAM 128 byte 00F100H to 00F2FFH I-RAM (Instruction RAM) 512 byte Note : Do not use (vacancy) . 30 Read/write MB91121 ■ INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS Interrupt number Interrupt level Decimal Hexadecimal Register Offset TBR default address Reset 0 00 3F4H 000FFFFCH Reserved for system 1 01 3F8H 000FFFF8H Reserved for system 2 02 3F4H 000FFFF4H Reserved for system 3 03 3F0H 000FFFF0H Reserved for system 4 04 3ECH 000FFFECH Reserved for system 5 05 3E8H 000FFFE8H Reserved for system 6 06 3E4H 000FFFE4H Reserved for system 7 07 3E0H 000FFFE0H Reserved for system 8 08 3DCH 000FFFDCH Reserved for system 9 09 3D8H 000FFFD8H Reserved for system 10 0A 3D4H 000FFFD4H Reserved for system 11 0B 3D0H 000FFFD0H Reserved for system 12 0C 3CCH 000FFFCCH Reserved for system 13 0D 3C8H 000FFFC8H Exception for undefined instruction 14 0E 3C4H 000FFFC4H NMI request 15 0F FH fixed 3C0H 000FFFC0H External interrupt 0 16 10 ICR00 3BCH 000FFFBCH External interrupt 1 17 11 ICR01 3B8H 000FFFB8H External interrupt 2 18 12 ICR02 3B4H 000FFFB4H External interrupt 3 19 13 ICR03 3B0H 000FFFB0H UART0 receive complete 20 14 ICR04 3ACH 000FFFACH UART1 receive complete 21 15 ICR05 3A8H 000FFFA8H UART2 receive complete 22 16 ICR06 3A4H 000FFFA4H UART0 transmit complete 23 17 ICR07 3A0H 000FFFA0H UART1 transmit complete 24 18 ICR08 39CH 000FFF9CH UART2 transmit complete 25 19 ICR09 398H 000FFF98H DMAC0 (complete, error) 26 1A ICR10 394H 000FFF94H DMAC1 (complete, error) 27 1B ICR11 390H 000FFF90H DMAC2 (complete, error) 28 1C ICR12 38CH 000FFF8CH DMAC3 (complete, error) 29 1D ICR13 388H 000FFF88H DMAC4 (complete, error) 30 1E ICR14 384H 000FFF84H DMAC5 (complete, error) 31 1F ICR15 380H 000FFF80H DMAC6 (complete, error) 32 20 ICR16 37CH 000FFF7CH Interrupt causes (Continued) 31 MB91121 Interrupt number Interrupt level Decimal Hexadecimal Register Offset TBR default address DMAC7 (complete, error) 33 21 ICR17 378H 000FFF78H A/D converter (successive approximation conversion type) 34 22 ICR18 374H 000FFF74H 16-bit reload timer 0 35 23 ICR19 370H 000FFF70H 16-bit reload timer 1 36 24 ICR20 36CH 000FFF6CH 16-bit reload timer 2 37 25 ICR21 368H 000FFF68H PWM 0 38 26 ICR22 364H 000FFF64H PWM 1 39 27 ICR23 360H 000FFF60H PWM 2 40 28 ICR24 35CH 000FFF5CH PWM 3 41 29 ICR25 358H 000FFF58H U-TIMER 0 42 2A ICR26 354H 000FFF54H U-TIMER 1 43 2B ICR27 350H 000FFF50H U-TIMER 2 44 2C ICR28 34CH 000FFF4CH External interrupt 4 45 2D ICR29 348H 000FFF48H External interrupt 5 46 2E ICR30 344H 000FFF44H External interrupt 6 47 2F ICR31 340H 000FFF40H External interrupt 7 48 30 ICR32 33CH 000FFF3CH DSP Macros soft interrupt 49 31 ICR33 338H 000FFF38H DSP Macros offset interrupt 50 32 ICR34 334H 000FFF34H Reserved for system 51 33 ICR35 330H 000FFF30H Reserved for system 52 34 ICR36 32CH 000FFF2CH Reserved for system 53 35 ICR37 328H 000FFF28H Reserved for system 54 36 ICR38 324H 000FFF24H Reserved for system 55 37 ICR39 320H 000FFF20H Reserved for system 56 38 ICR40 31CH 000FFF1CH Reserved for system 57 39 ICR41 318H 000FFF18H Reserved for system 58 3A ICR42 314H 000FFF14H Reserved for system 59 3B ICR43 310H 000FFF10H Reserved for system 60 3C ICR44 30CH 000FFF0CH Reserved for system 61 3D ICR45 308H 000FFF08H Reserved for system 62 3E ICR46 304H 000FFF04H Delayed interrupt cause bit 63 3F ICR47 300H 000FFF00H Reserved for system (used in REALOS*) 64 40 2FCH 000FFEFCH Reserved for system (used in REALOS*) 65 41 2F8H 000FFEF8H Interrupt causes (Continued) 32 MB91121 (Continued) Interrupt causes Used in INT instructions Interrupt number Interrupt level Decimal Hexadecimal Register Offset TBR default address 66 to 255 42 to FF 2F4H to 000H 000FFEF4H to 000FFC00H * : When using in REALOS/FR, interrupt 0x40, 0x41 for system code. 33 MB91121 ■ PERIPHERAL RESOURCES 1. I/O Ports There are 2 types of I/O port register structure; port data register (PDR2, 6, 8, A, B, E to I) and data direction register (DDR2, 6, 8, A, B, E to I) , where bits PDR2, 6, 8, A, B, E to I and bits DDR2, 6, 8, A, B, E to I corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit “0” specifies input and “1” specifies output. • For input (DDR = “0”) setting; PDR reading operation : reads level of corresponding external pin. PDR writing operation : writes set value to PDR. • For output (DDR = “1”) setting; PDR reading operation : reads PDR value. PDR writing operation : outputs PDR value to corresponding external pin. • Block diagram Resource input 0 1 Data bus PDR read 0 PDR (Port data register) Resource output 1 Resource output enable DDR (Data direction register) 34 Pin MB91121 • Register explanation • Port Data Register (PDR) PDR2 Address : 000001H PDR6 Address : 000005H PDR8 Address : 00000BH PDRA Address : 000009H PDRB Address : 000008H PDRE Address : 000012H PDRF Address : 000013H PDRG Address : 000014H PDRH Address : 000015H PDRI Address : 000016H 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 7 6 5 4 3 2 1 0 P85 P82 P81 P80 7 6 5 4 3 2 1 0 PA6 PA5 PA4 PA3 PA2 PA1 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 7 6 5 4 3 2 1 0 PH7 PH6 PH5 PH4 7 6 5 4 3 2 1 0 PI1 PI0 Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value − − X − − X X XB Access R/W Initial value − X X X X X X −B Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X X X X XB Access R/W Initial value X X X X − − − −B Access R/W Initial value − − − − − − X XB Access R/W PDR2 to PDRI is the I/O port input/output data register. The associated register, DDR2 to DDRI, controls the input/output. 35 MB91121 • Data Direction Register (DDR) DDR2 Address : 000601H DDR6 Address : 000605H DDR8 Address : 00060BH DDRA Address : 000609H DDRB Address : 000608H DDRE Address : 0000D2H DDRF Address : 0000D3H DDRG Address : 0000D4H DDRH Address : 0000D5H DDRI Address : 0000D6H 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 7 6 5 4 3 2 1 0 P85 P82 P81 P80 7 6 5 4 3 2 1 0 PA6 PA5 PA4 PA3 PA2 PA1 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 7 6 5 4 3 2 1 0 PH7 PH6 PH5 PH4 7 6 5 4 3 2 1 0 PI1 PI0 DDR2 to DDRI controls the I/O port input/output direction bit by bit. 0 : Input 1 : Output 36 Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value − − 0 − − 0 0 0B Access W Initial value − 0 0 0 0 0 0 −B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 0 0 0 0B Access W Initial value 0 0 0 0 − − − −B Access W Initial value − − − − − − 0 0B Access W MB91121 2. DMA Controller (DMAC) The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. • • • • • • • 8 channels Mode : single/block transfer, burst transfer and continuous transfer : 3 kinds of transfer Transfer all through the area Max. 65536 of transfer cycles Interrupt function right after the transfer Selectable for address transfer increase/decrease by the software External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each • Block diagram DREQ0 to DREQ2 3 Edge/level detection circuit 3 3 DACK0 to DACK2 3 Sequencer EOP0 to EOP2 8 Interrupt request 5 Inner resource transfer request Data buffer Switcher DACSR DATCR Data bus DPDP Mode BLK DEC BLK DMACT INC / DEC SADR DADR 37 MB91121 • Registers (DMAC internal registers) Address Initial value bit 31 bit 16 bit 0 00000200H 00000201H 00000202H 00000203H DPDP X X X X X X X XB X X X X X X X XB X X X X X X X XB X 0 0 0 0 0 0 0B (R/W) 00000204H 00000205H 00000206H 00000207H DACSR 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 00000208H 00000209H 0000020AH 0000020BH DATCR X X X X X X X XB X X X X 0 0 0 0B X X X X 0 0 0 0B X X X X 0 0 0 0B (R/W) ( ) : Access R/W : Readable and writable X : Indeterminate • Registers (DMA descriptor) Address DPDP + 0H DPDP + 0CH DPDP + 54H 38 bit 31 bit 0 DMA ch.0 Descriptor DMA ch.1 Descriptor DMA ch.7 Descriptor MB91121 3. UART The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features. The MB91121 consists of 3 channels of UART. • • • • • • • • Full double double buffer Both a synchronous (start-stop system) communication and CLK synchronous communication are available. Supporting multi-processor mode Perfect programmable baud rate Any baud rate can be set by internal timer (refer to section “4. U-TIMER”) . Any baud rate can be set by external clock. Error checking function (parity, framing and overrun) Transfer signal : NRZ code Enable DMA transfer start by interrupt. 39 MB91121 • Block diagram Control signals Receive interrupt (to CPU) SC (clock) Transmit interrupt (to CPU) Transmit clock From U-TIMER Clock select circuit Receive clock From external clock SC SI (receive data) Receive control circuit Transmit control circuit Start bit detect circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter SO (transmit data) Receive status judge circuit Receive shifter Receive error generate signal for DMA (to DMAC) Transmit shifter Receive complete Transmit start SODR SIDR R-bus MD1 MD0 SMR register CS0 SCKE SOE SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE RIE TIE Control signals 40 MB91121 • Register configuration Address Initial value bit 15 bit 8 bit 0 0000001EH SCR0 0 0 0 0 0 1 0 0B (R/W) 00000022H SCR1 0 0 0 0 0 1 0 0B (R/W) 00000026H SCR2 0 0 0 0 0 1 0 0B (R/W) 0000001FH SMR0 0 0 − − 0 − 0 0B (R/W) 00000023H SMR1 0 0 − − 0 − 0 0B (R/W) 00000027H SMR2 0 0 − − 0 − 0 0B (R/W) 0000001CH SSR0 0 0 0 0 1 − 0 0B (R/W) 00000020H SSR1 0 0 0 0 1 − 0 0B (R/W) 00000024H SSR2 0 0 0 0 1 − 0 0B (R/W) 0000001DH SIDR0/SODR0 X X X X X X X XB (R/W) 00000021H SIDR1/SIDR1 X X X X X X X XB (R/W) 00000002H SIDR2/SIDR2 X X X X X X X XB (R/W) ( ) R/W X : Access : Readable and writable : Unused : Indeterminate 41 MB91121 4. U-TIMER (16-bit Timer for UART Baud Rate Generation) The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91121 has 3 channel U-TIMER embedded on the chip. An interval of up to 216 × φ can be counted. • Block diagram bit 15 bit 0 UTIMR (reload register) Load bit 15 bit 0 UTIM ( U-TIMER register) Underflow Clock φ (Peripheral clock) Control To UART f.f. • Register configuration Address Initial value bit 15 00000078H 00000079H UTIM0/UTIMR0 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 0000007CH 0000007DH UTIM1/UTIMR1 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 00000080H 00000081H UTIM2/UTIMR2 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 0000007BH UTIMC0 0 − − 0 0 0 0 1B (R/W) 0000007FH UTIMC1 0 − − 0 0 0 0 1B (R/W) 00000083H UTIMC2 0 − − 0 0 0 0 1B (R/W) ( ) : Access R/W : Readable and writable : Unused 42 bit 0 MB91121 5. PWM Timer The PWM timer can output high accurate PWM waves efficiently. MB91121 has inner 4-channel PWM timers, and has the following features. • Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit compare resister with a buffer for duty setting, and a pin controller. • The count clock of a 16-bit down counter can be selected from the following four inner clocks. Inner clock φ, φ/4, φ/16, φ/64 • The counter value can be initialized “FFFFH” by the resetting or the counter borrow. • PWM output (each channel) • Resister description • Block diagram (general construction) 16-bit reload timer ch.0 16-bit reload timer ch.1 General control register 2 General control register 1 (cause selection) 4 4 External TRG0 to TRG3 TRG input PWM timer ch.0 PWM0 TRG input PWM timer ch.1 PWM1 TRG input PWM timer ch.2 PWM2 TRG input PWM timer ch.3 PWM3 43 MB91121 • Block diagram (for one channel) PDUT PCSR Prescaler 1/1 1/4 1 / 16 1 / 64 cmp Load ck 16-bit down counter Start Borrow PPG mask S Peripheral clock Q PWM output R Enable TRG input Edge detect Soft trigger 44 Interrupt selection Reverse bit IRQ MB91121 • Register configuration Address Initial value bit 15 bit 8 000000DCH 000000DDH bit 0 GCN1 000000DFH GCN2 0 0 1 1 0 0 1 0B 0 0 0 1 0 0 1 0B (R/W) 0 0 0 0 0 0 0 0B (R/W) 000000E0H 000000E1H PTMR0 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B (R) 000000E2H 000000E3H PCSR0 X X X X X X X XB X X X X X X X XB (W) 000000E4H 000000E5H PDUT0 X X X X X X X XB X X X X X X X XB (W) 0 0 0 0 0 0 0 −B (R/W) 0 0 0 0 0 0 0 0B (R/W) 000000E6H PCNH0 000000E7H PCNL0 000000E8H 000000E9H PTMR1 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B (R) 000000EAH 000000EBH PCSR1 X X X X X X X XB X X X X X X X XB (W) 000000ECH 000000EDH PDUT1 X X X X X X X XB X X X X X X X XB (W) 0 0 0 0 0 0 0 −B (R/W) 0 0 0 0 0 0 0 0B (R/W) 000000EEH PCNH1 000000EFH PCNL1 000000F0H 000000F1H PTMR2 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B (R) 000000F2H 000000F3H PCSR2 X X X X X X X XB X X X X X X X XB (W) 000000F4H 000000F5H PDUT2 X X X X X X X XB X X X X X X X XB (W) 0 0 0 0 0 0 0 −B (R/W) 0 0 0 0 0 0 0 0B (R/W) 000000F6H PCNH2 000000F7H PCNL2 000000F8H 000000F9H PTMR3 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B (R) 000000FAH 000000FBH PCSR3 X X X X X X X XB X X X X X X X XB (W) 000000FCH 000000FDH PDUT3 X X X X X X X XB X X X X X X X XB (W) 0 0 0 0 0 0 0 −B (R/W) 0 0 0 0 0 0 0 0B (R/W) 000000FEH PCNH3 000000FFH ( ) R/W R W X PCNL3 : Access : Readable and writable : Read only : Write only : Unused : Indeterminate 45 MB91121 6. 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock) . The DMA transfer can be started by the interruption. The MB91121 consists of 3 channels of the 16-bit reload timer. • Block diagram 16 16-bit reload register 8 Reload RELD 16 16-bit down counter UF OUTE OUTL 2 OUT CTL. GATE INTE R-bus 2 IRQ UF CSL1 Clock selector CNTE CSL0 2 TRG Retrigger IN CTL. EXCK φ φ φ 21 23 25 3 Prescaler clear MOD2 MOD1 Internal clock MOD0 3 46 PWM (ch0, ch1) A/D (ch2) MB91121 • Register configuration Address Initial value bit 15 bit 0 0000002EH 0000002FH TMCSR0 − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 00000036H 00000037H TMCSR1 − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 00000042H 00000043H TMCSR2 − − − − 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 0000002AH 0000002BH TMR0 X X X X X X X XB X X X X X X X XB (R) 00000032H 00000033H TMR1 X X X X X X X XB X X X X X X X XB (R) 0000003EH 0000003FH TMR2 X X X X X X X XB X X X X X X X XB (R) 00000028H 00000029H TMRLR0 X X X X X X X XB X X X X X X X XB (W) 00000030H 00000031H TMRLR1 X X X X X X X XB X X X X X X X XB (W) 0000003CH 0000003DH TMRLR2 X X X X X X X XB X X X X X X X XB (W) ( ) R/W R W X : Access : Readable and writable : Read only : Write only : Unused : Indeterminate 47 MB91121 7. Bit Search Module The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. • Block diagram Input latch Address decoder Detection mode D-bus Single-detection data recovery Bit search circuit Search result • Register configuration Address Initial value bit 31 bit 0 000003F0H 000003F1H 000003F2H 000003F3H BSD0 X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB (W) 000003F4H 000003F5H 000003F6H 000003F7H BSD1 X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB (W) 000003F8H 000003F9H 000003FAH 000003FBH BSDC X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB (W) 000003FCH 000003FEH 000003FDH 000003FFH BSRR X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB (W) ( ) R/W R W X 48 bit 16 : Access : Readable and writable : Read only : Write only : Indeterminate MB91121 8. 10-bit A/D Converter (Successive Approximation Conversion Type) The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. Minimum converting time : 5.6 µs/ch. (system clock : 25 MHz) Inner sample and hold circuit Resolution : 10 bits Analog input can be selected from 4 channels by program. Single convert mode : 1 channel is selected and converted. Scan convert mode : Converting continuous channels. Maximum 4 channels are programmable. Continuous convert mode : Converting the specified channel repeatedly. Stop convert mode : After converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. • DMA transfer operation is available by interruption. • Operating factor can be selected from the software, the external trigger (falling edge) , and 16-bit reroad timer (rising edge) . • • • • 49 MB91121 • Block diagram AVCC AVR AVSS Internal voltage generator MPX Successive approximation register Input circuit AN0 AN1 AN2 AN3 Comparator R-bus Sample & hold circuit Decoder Data register (ADCR) A/D control register (ADCS) Trigger start ATG TIM0 (internal connection) (16-bit reload timer ch.2) Timer start Operating clock φ (Peripheral clock) Prescaler • Register configuration Address Initial value bit 15 0000003AH 0000003BH ADCS 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (R/W) 00000038H 00000039H ADCR − − − − − − X XB X X X X X X X XB (R) ( ) R/W R X 50 bit 0 : Access : Readable and writable : Read only : Unused : Indeterminate MB91121 9. Interrupt Controller The interrupt controller processes interrupt acknowledgments and arbitration between interrupts. • Block diagram INT0 2 IM Priority judgment OR 5 5 NMI processing NMI 4 Level judgment ICR00 RI00 • • • 6 • • • • • Vector judgment 6 HLDCAN 3 VCT5 to VCT0 5 ICR47 RI47 (DLYIRQ) Level vector generation HLDREQ cancel request LEVEL4 to LEVEL0 4 DLYI 1 R-bus *1 : DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11. Delayed Interrupt Module” for detail) . *2 : INT0 is a wake-up signal to clock control block in the sleep or stop status. *3 : HLDCAN is a bus release request signal for bus masters other than CPU. *4 : LEVEL5 to LEVEL0 are interrupt level outputs. *5 : VCT5 to VCT0 are interrupt vector outputs. 51 MB91121 • Register configuration Address Initial value bit 7 Initial value bit 7 bit 0 00000400H ICR00 − − − 1 1 1 1 1B (R/W) 00000411H ICR17 − − − 1 1 1 1 1B (R/W) 00000401H ICR01 − − − 1 1 1 1 1B (R/W) 00000412H ICR18 − − − 1 1 1 1 1B (R/W) 00000402H ICR02 − − − 1 1 1 1 1B (R/W) 00000413H ICR19 − − − 1 1 1 1 1B (R/W) 00000403H ICR03 − − − 1 1 1 1 1B (R/W) 00000414H ICR20 − − − 1 1 1 1 1B (R/W) 00000404H ICR04 − − − 1 1 1 1 1B (R/W) 00000415H ICR21 − − − 1 1 1 1 1B (R/W) 00000405H ICR05 − − − 1 1 1 1 1B (R/W) 00000416H ICR22 − − − 1 1 1 1 1B (R/W) 00000406H ICR06 − − − 1 1 1 1 1B (R/W) 00000417H ICR23 − − − 1 1 1 1 1B (R/W) 00000407H ICR07 − − − 1 1 1 1 1B (R/W) 00000418H ICR24 − − − 1 1 1 1 1B (R/W) 00000408H ICR08 − − − 1 1 1 1 1B (R/W) 00000419H ICR25 − − − 1 1 1 1 1B (R/W) 00000409H ICR09 − − − 1 1 1 1 1B (R/W) 0000041AH ICR26 − − − 1 1 1 1 1B (R/W) 0000040AH ICR10 − − − 1 1 1 1 1B (R/W) 0000041BH ICR27 − − − 1 1 1 1 1B (R/W) 0000040BH ICR11 − − − 1 1 1 1 1B (R/W) 0000041CH ICR28 − − − 1 1 1 1 1B (R/W) 0000040CH ICR12 − − − 1 1 1 1 1B (R/W) 0000041DH ICR29 − − − 1 1 1 1 1B (R/W) 0000040DH ICR13 − − − 1 1 1 1 1B (R/W) 0000041EH ICR30 − − − 1 1 1 1 1B (R/W) 0000040EH ICR14 − − − 1 1 1 1 1B (R/W) 0000041FH ICR31 − − − 1 1 1 1 1B (R/W) 0000040FH ICR15 − − − 1 1 1 1 1B (R/W) 0000042FH ICR47 − − − 1 1 1 1 1B (R/W) 00000410H ICR16 − − − 1 1 1 1 1B (R/W) 00000431H HRCL − − − 1 1 1 1 1B (R/W) 00000430H DICR − − − − − − − 0B (R/W) ( ) : Access R/W : Readable and writable : Unused 52 Address bit 0 MB91121 10. External Interrupt/NMI Control Block The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to INT3 pins. Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin) . • Block diagram 8 9 R-bus Interrupt request Interrupt enable register Gate 8 Cause F/F Edge detection circuit 5 INT0 to INT7 NMI Interrupt cause register 8 Request level setting register • Register configuration Address Initial value bit 15 bit 8 ENIR 00000095H 00000094H bit 0 EIRR 00000099H ELVR 0 0 0 0 0 0 0 0B (R/W) 0 0 0 0 0 0 0 0B (R/W) 0 0 0 0 0 0 0 0B (R/W) ( ) : Access R/W : Readable and writable 53 MB91121 11. Delayed Interrupt Module Delayed interrupt module is a module which generates an interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram. • Register configuration Address Initial value bit 7 00000430H ( ) : Access R/W : Readable and writable : Unused 54 bit 0 DICR − − − − − − − 0B (R/W) MB91121 12. Clock Generation (Low-power consumption mechanism) The clock control block is a module which undertakes the following functions. • • • • • • CPU clock generation (including gear function) Peripheral clock generation (including gear function) Reset generation and cause hold Standby function (including hardware standby) DMA request prohibit PLL (multiplier circuit) embedded 55 MB91121 • Block diagram [Gear control block] Gear control register (GCR) CPU gear X0 X1 Oscillator circuit PCTR register PLL 1/2 Selection circuit R-bus Peripheral gear CPU clock Internal bus clock External bus clock Internal clock generation circuit Peripheral DMA clock DSP Macros clock Internal peripheral clock [Stop/sleep control block] Internal interrupt request Internal reset Standby control register (STCR) STOP state SLEEP state Status transition control circuit CPU hold enable HST pin CPU hold request Reset generation F/F [DMA prohibit circuit] DMA request DMA request prohibit register (PDRR) [Reset cause circuit] Power on sel RST pin Reset cause register (RSRR) [Watchdog control block] Watchdog reset generation postpone register (WPR) Watchdog reset postpone register Timebase timer clear register (CTBR) Timebase timer 56 Count clock Internal reset MB91121 • Register configuration Address Initial value bit 15 00000480H bit 8 RSRR/WTCR 00000481H 00000482H STCR PDRR 00000483H 00000484H CDBR GCR 00000485H ( ) R/W R X bit 0 WPR 1 X X X X − 0 0B (R/W) 0 0 0 1 1 1 − −B (R/W) − − − − 0 0 0 0B (R/W) X X X X X X X XB (W) 1 1 0 0 1 1 − 1B (R/W) X X X X X X X XB (W) : Access : Readable and writable : Read only : Unused : Indeterminate 57 MB91121 13. External Bus Interface The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. • 25-bit (32 Mbytes) address output • 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin. • 8/16-bit bus width setting are available for every chip select area. • Programmable automatic memory wait (Max. for 7 cycles) can be inserted. • DRAM interface support Three kinds of DRAM interface : Double CAS DRAM (normally DRAM I/F) Single CAS DRAM Hyper DRAM 2 banks independent control (RAS, CAS, etc. control signals) DRAM select is available from 2CAS/1WE and 1CAS/2WE. Hi-speed page mode supported CBR/self refresh supported Programmable wave form • Unused address/data pin can be used for I/O port. • Little endian mode supported • Clock doublure : Internal bus 50 MHz, external bus 25 MHz 58 MB91121 • Block diagram Address bus 32 A-OUT Data bus 32 External data bus Write buffer Switch Read buffer Switch MUX DATA BLOCK ADDRESS BLOCK +1 or +2 External address bus Inpage Shifter Address buffer 6 ASR AMR CS0 to CS5 Comparator 8 DRAM control RAS0, RAS1 CS0L, CS1L CS0H, CS1H DW0, DW1 Underflow DMCR Refresh counter To TBT 3 External pin control block All blocks control 4 Registers & control RD WR0, WR1 BRQ BGRNT CLK RDY 59 MB91121 • Register configuration Address Initial value bit 31 0000060CH 0000060DH bit 16 bit 0 ASR1 0000060EH 0000060FH AMR1 00000610H 00000611H ASR2 00000612H 00000613H AMR2 00000614H 00000615H ASR3 00000616H 00000617H AMR3 00000618H 00000619H ASR4 0000061AH 0000061BH AMR4 0000061CH 0000061DH ASR5 0000061EH 0000061FH 00000620H AMR5 AMD0 00000621H AMD1 00000622H AMD32 00000623H 00000624H AMD4 AMD5 00000625H DSCR 00000626H 00000627H 00000628H 00000629H RFCR EPCR0 0000062BH 0000062CH 0000062DH 0000062EH 0000062FH 000007FEH 000007FFH ( ) : Access W : Write only X : Indeterminate 60 EPCR1 DMCR4 DMCR5 LER MODR 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 0B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 1B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (W) − − − 0 0 1 1 1B (R/W) 0 − − 0 0 0 0 0B (R/W) 0 0 0 0 0 0 0 0B (R/W) 0 − − 0 0 0 0 0B (R/W) 0 − − 0 0 0 0 0B (R/W) 0 0 0 0 0 0 0 0B (W) − − X X X X X XB 0 0 − − − 0 0 0B (R/W) − − − 1 1 0 0 0B − 1 1 1 1 1 1 1B (W) 1 1 1 1 1 1 1 1B (W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B (R/W) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B (R/W) − − − − − 0 0 0B (W) X X X X X X X XB (W) R/W : Readable and writable : Unused MB91121 ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter (VSS = AVSS = 0.0 V) Symbol Value Min. Max. Unit Remarks Power supply voltage VCC VSS − 0.3 VSS + 3.6 V Analog supply voltage AVCC VSS − 0.3 VSS + 3.6 V *1 Analog reference voltage AVRH VSS − 0.3 VSS + 3.6 V *1 Input voltage VI VSS − 0.3 VCC + 0.3 V Analog pin input voltage VIA VSS − 0.3 AVCC + 0.3 V Output voltage VO VSS − 0.3 VCC + 0.3 V “L” level maximum output current IOL 10 mA *2 “L” level average output current IOLAV 4 mA *3 “L” level maximum total output current ΣIOL 100 mA ΣIOLAV 50 mA *4 IOH −10 mA *2 “H” level average output current IOHAV −4 mA *3 “H” level maximum total output current ΣIOH −50 mA ΣIOHAV −20 mA Power consumption PD 600 mW Operating temperature TA 0 +70 °C Tstg −55 +150 °C “L” level average total output current “H” level maximum output current “H” level average total output current Storage temperature *4 *1 : Care must be taken that AVCC and AVRH do not exceed VCC + 0.3 V, such as when turning on the device. Also, care must be taken that AVRH does not exceed AVCC. *2 : Maximum output current is a peak current value measured at a corresponding pin. *3 : Average output current is an average current for a 100 ms period at a corresponding pin. *4 : Average total output current is an average current for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 61 MB91121 2. Recommended Operating Conditions Parameter Symbol (VSS = AVSS = 0.0 V) Value Min. Max. Unit Power supply voltage VCC 3.0 3.6 V Analog supply voltage AVCC VSS + 0.3 VSS + 3.6 V Analog reference voltage AVRH AVSS AVCC V TA 0 +70 °C Operating temperature Remarks WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 62 MB91121 3. DC Characteristics Parameter (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol Pin name Condition Value Min. Typ. Max. Unit Remarks VIH Input pin except for hysteresis input 0.65 × VCC VCC + 0.3 V *2 VIHS *1 0.8 × VCC VCC + 0.3 V Hysteresis input*2 VIL Input pin except for hysteresis input VSS − 0.3 0.25 × VCC V *2 VILS *1 VSS − 0.3 0.2 × VCC V Hysteresis input*2 “H” level output voltage VOH D16 to D31 VCC = 3.0 V A00 to A24 IOH = −4.0 mA P6 to PF VCC − 0.5 V “L” level output voltage VOL D16 to D31 VCC = 3.0 V A00 to A24 IOL = 4.0 mA P6 to PF 0.4 V D00 to D31 VCC = 3.6 V A00 to A23 0.45 V< VI < VCC P8 to PF −5 +5 µA 25 50 100 kΩ “H” level input voltage “L” level input voltage Input leakage current (Hi-Z output leakage current) Pull-up resistance ILI RPULL RST FC = 12.5 MHz VCC = 3.3 V 130 180 (4 multiplication) mA Operation at 50 MHz ICCS FC = 12.5 MHz VCC = 3.3 V 85 120 mA Sleep mode ICCH TA = +25 °C VCC = 3.3 V 15 150 µA Stop mode 10 ICC Power supply current Input capacitance VCC = 3.6 V VI = 0.45 V VCC CIN Except for VCC, AVCC, AVSS, VSS pF *1 : Hysteresis input pin : NMI, RST, P60 to P67, PA1 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7, PG0 to PG7, PI0, PI1 *2 : VCC3 = 3.3 ± 0.2 V (internal regulator output voltage) when using 5 V power supply, VCC3 = power supply voltage when using 3V power supply (internal regulator unused) 63 MB91121 4. AC Characteristics (1) Measurement Conditions The following conditions apply to AC characteristics unless otherwise specified. • Measurement conditions for AC standards VCC : 3.0 V to 3.6 V Input Output VCC 0V HIH VOH VIL VOL VIH VOH 1/2 ∗ VCC VIL 1/2 ∗ VCC VOL 1/2 ∗ VCC (The input rise/fall time is 10 ns or less.) • Load condition Output pin C = 50 pF (VCC : 3.0 V to 3.6 V) 64 1/2 ∗ VCC MB91121 (2) Clock Timing Rating (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 .0V, TA = 0 °C to + 70 °C) Parameter Value Symbol Pin name Condition Unit Min. Max. 10 12.5 MHz 80 100 ns 5 % Remarks Clock frequency (1) FC X0, X1 Clock cycle time tC X0, X1 Frequency shift ratio*1 (when locked) ∆f Clock frequency (2) FC X0, X1 10 25 MHz Self-oscillation (divide-by-2 input) Clock frequency (3) FC X0, X1 10 25 MHz External clock (divide-by-2 input) Clock cycle time tC X0, X1 40 100 ns PWH, PWL X0, X1 25 ns Input to X0 only 10 ns Input to X0, X1 tCR, tCF X0, X1 8 ns (tCR + tCF) fCP 0.625*2 50 MHz CPU system fCPB 0.625*2 25*3 MHz Bus system fCPP 2 MHz Peripheral system Input clock pulse width Input clock rising/falling time Internal operating clock frequency 0.625* 25 When using PLL 20 1600* 2 ns CPU system tCPB 40*3 1600*2 ns Bus system tCPP 40 1600*2 ns Peripheral system tCP Internal operating clock cycle time *1 : Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system. + ∆f = |α| × 100 (%) f0 +α Center frequency f0 −α − *2 : These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and a 1/8 gear. *3 : Values when using the doublure and CPU operation at 50 MHz. 65 MB91121 • Clock timing rating measurement conditions tC 0.8 VCC 0.2 VCC PWH PWL tCR tCF • Guaranteed operating range Guaranteed operating range (T A = 0 °C to +70 °C) f CPP falls within the shaded range. Power supply VCC (V) 3.6 3.0 3.3 V ± 0.3 V 0 0.625 25 50 fCP / fCPP [MHz] Internal clock Internal clock setting upper limit • External/internal clock setting range fCP fCPP 50 40 CPU 25 20 Peripheral PLL system (4 multiplication) Divide-by-2 system 12.5 5 0 0 10 12.5 25 50 FC [MHz] External clock Internal oscillation Oscillation input clock Note : 1.If the PLL is used, the external clock input should be 10.0 MHz to 12.5 MHz. 2.The PLL oscillation settling time must be longer than 300 µs. 3.The internal clock gear setting must fall within the above range. 66 MB91121 (3) Clock Output Timing Parameter Symbol (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Pin name Value Condition Min. Max. tCP — tCPB — Cycle time tCYC CLK CLK ↑ → CLK ↓ tCHCL CLK 1 / 2 × tCYC − 10 CLK ↓ → CLK ↑ tCLCH CLK 1 / 2 × tCYC − 10 Unit Remarks *1 ns Using the doublure 1 / 2 × tCYC + 10 ns *2 1 / 2 × tCYC + 10 ns *3 tCYC tCHCL CLK tCLCH VOH VOH VOL *1 : tCYC is a frequency for 1 clock cycle including a gear cycle. Use the doublure when CPU frequency is above 25 MHz. *2 : Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8, respectively. Min. : (1 − n / 2) × tCYC − 10 Max. : (1 − n / 2) × tCYC + 10 Select a gear cycle of × 1 when using the doublure. *3 : Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8, respectively. Min. : n / 2 × tCYC − 10 Max. : n / 2 × tCYC + 10 Select a gear cycle of × 1 when using the doublure. 67 MB91121 The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows: However, in this chart source oscillation input means X0 input clock. Source oscillation input (when using the doublure) (1) PLL system (CHC bit of GCR set to “0”) (a) Gear × 1 CLK pin CCK1/0: “00” tCYC tCYC Source oscillation input (2) 2 dividing system (CHC bit of GCR set to “1”) (a) Gear × 1 CLK pin CCK1/0: “00” (b) Gear × 1/2 CLK pin CCK1/0: “01” (c) Gear × 1/4 CLK pin CCK1/0: “10” (d) Gear × 1/8 CLK pin CCK1/0: “11” 68 tCYC tCYC tCYC tCYC MB91121 • Ceramc oscillator applications Recommended circuit (2 contacts) X0 Recommended circuit (3 contacts) X0 X1 X1 * * C1 C1 C2 C2 C1, C2 internally connected. * : Murata Mfg. Co., Ltd. • Discrete type Oscillation frequency [MHz] 10.00 to 13.00 13.01 to 15.99 16.00 to 19.99 20.00 to 25.00 Model name Circuit constants C1[pF] C1[pF] Rf[Ω]*1 Rd[Ω]*2 Pin type CSA MTZ 30 30 0 Two-pin CST MTW (30) (30) 0 Three-pin CSA MXZ040 15 15 0 Two-pin CST MXW0C3 (15) (15) 0 Three-pin CSA MXZ040 (10) (10) 0 Two-pin ∗∗∗∗∗∗∗∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ Three-pin CSA None None 0 Two-pin ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ Three-pin MXZ004 ∗∗∗∗∗∗∗∗∗∗∗ *1 : Feedback resistor Rf is built in the LSI. *2 : No dumping resistor is required. ( ) : C1 and C2 integrated 69 MB91121 • SMD type Oscillation frequency [MHz] 10.00 to 13.00 13.01 to 15.99 16.00 to 19.99 20.00 to 25.00 Model name C1[pF] C1[pF] Rf[Ω]*1 Rd[Ω]*2 Pin type CSACS MT 30 30 0 Two-pin CSTCS MT (30) (30) 0 Three-pin CSACS MX040 15 15 0 Two-pin CSTCS MX0C3 (15) (15) 0 Three-pin CSACS MX040 10 10 0 Two-pin CSTCS MX0C2 (10) (10) 0 Three-pin CSACS MX040 None None 0 Two-pin ∗∗∗∗∗∗∗∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ Three-pin *1 : Feedback resistor Rf is built in the LSI. *2 : No dumping resistor is required. ( ) : C1 and C2 integrated 70 Circuit constants MB91121 (4) Reset input ratings Parameter Reset input time (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol Pin name Condition tRSTL RST Value Min. Max. tCP × 5 Unit Remarks ns tRSTL, tHSTL RST 0.2 VCC 71 MB91121 (5) Power-on Reset Parameter Power supply rising time Power supply shut off time (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol Pin name Condition Value Min. Max. Unit Remarks tR VCC VCC = 3.3 V 50 µs 18 ms VCC < 0.2 V before the power supply rising tOFF VCC 1 ms Repeated operations tR VCC 0.9 × VCC 0.2 V tOFF Note: Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. VCC A voltage rising rate of 50 mV/ms or less is recommended. VSS Note: Set RST pin to ÒLÓ level when turning on the device, at least the described above duration after the supply voltage reaches Vcc is necessary before turning the RST to ÒHÓ level. VCC RST tRSTL 72 MB91121 (6) Normal Bus Access Read/write Operation Parameter CS0 to CS5 delay time Symbol tCHCSL tCHCSH Pin name (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Condition CLK CS0 to CS5 Value Unit Remarks Min. Max. 15 ns 15 ns Address delay time tCHAV CLK A24 to A00 15 ns Data delay time tCHDV CLK D31 to D16 15 ns 10 ns 10 ns 10 ns 10 ns 3 / 2 × tCYC − 40 ns *1 *2 tCYC − 25 ns *1 25 ns 0 ns RD delay time WR0, WR1 delay time tCLRL tCLRH tCLWL tCLWH Valid address → valid data input time tAVDV RD ↓→ valid data input time tRLDV Data set up → RD ↑ time tDSRH RD ↑→ data hold time tRHDX CLK RD CLK WR0, WR1 A24 to A00 D31 to D16 RD D31 to D16 *1 : When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC × extended cycle number for delay) to this rating. *2 : Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. Equation : (2 − n / 2) × tCYC − 40 73 MB91121 tCYC BA2 BA1 CLK VOH VOH VOL VOH VOL tCHCSH tCHCSL CS0 to CS5 VOL A24 to A00 VOH VOL VOH tCHAV VOH VOL tCLRL tCLRH RD VOH VOL tRLDV tRHDX tAVDV VIH VIL D31 to D16 VIH VIL Read tDSRH tCLWL tCLWH WR0 , WR1 VOH VOL tCHDV D31 to D16 74 VOH VOL Write VOH VOL MB91121 (7) Ready Input Timing Parameter RDY set up time → CLK ↓ CLK ↓ → RDY hold time (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol Pin name tRDYS RDY CLK tRDYH CLK RDY Condition Value Unit Min. Max. 20 ns 0 ns Remarks tCYC CLK VOH VOH VOL VOL tRDYH tRDYH tRDYS RDY When wait(s) is inserted. RDY When no wait is inserted. VIL VIH tRDYS VIH VIL 75 MB91121 (8) Hold Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Parameter Symbol tCHBGL BGRNT delay time tCHBGH Pin floating → BGRNT ↓ time tXHAL BGRNT ↑→ pin valid time tHAHV Pin name Condition CLK BGRNT BGRNT Value Max. 10 ns 10 ns tCYC − 10 tCYC + 10 ns tCYC − 10 tCYC + 10 ns Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change. tCYC CLK VOH VOH VOH VOH BRQ tCHBGH tCHBGL BGRNT VOH VOL tXHAL tHAHV Each pin High impedance 76 Unit Min. Remarks MB91121 (9) Normal DRAM Mode Read/Write Cycle Parameter RAS delay time CAS delay time Symbol tCLRAH tCHRAL tCLCASL tCLCASH ROW address delay time tCHRAV COLUMN address delay time tCHCAV DW delay time tCHDWL tCHDWH (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Pin name Condition CLK RAS CLK CAS CLK A24 to A00 CLK DW Value Unit Min. Max. 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 15 ns 15 ns Remarks Output data delay time tCHDV1 CLK D31 to D16 15 ns RAS ↓ → valid data input time tRLDV RAS D31 to D16 5 / 2 × tCYC − 20 ns *1 *2 CAS ↓ → valid data input time tCLDV tCYC − 17 ns *1 CAS ↑ → data hold time tCADH 0 ns CAS D31 to D16 *1 : When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating. *2 : Rating at a gear cycle of × 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. Equation : (3 − n / 2) × tCYC − 20 77 MB91121 tCYC Q1 CLK Q2 Q3 Q4 VOH Q5 VOH VOH VOL VOL VOH RAS VOL VOL tCHRAL tCLRAH tCLCASH tCLCASL CAS VOH VOL tCHCAV tCHRAV VOH VOL A24 to A00 ROW address VOH VOL VOH VOL COLUMN address VOH VOL tRLDV tCLDV VIH VIL D31 to D16 tCADH VIH VIL Read VOH DW VOL tCHDWH tCHDWL D31 to D16 VOH VOL tCHDV1 78 Write VOH VOL MB91121 (10) Normal DRAM Mode Fast Page Read/Write Cycle (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Parameter RAS delay time CAS delay time Symbol Pin name tCLRAH CLK, RAS tCLCASL CLK CAS tCLCASH COLUMN address delay time tCHCAV CLK A24 to A00 DW delay time tCHDWH CLK, DW Output data delay time tCHDV1 CLK D31 to D16 CAS ↓→ valid data input time tCLDV CAS ↑→ data hold time tCADH Condition CAS D31 to D16 Value Unit Min. Max. 10 ns 10 ns 10 ns 15 ns 15 ns 15 ns tCYC − 17 ns 0 ns Remarks * * : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating. 79 MB91121 Q5 Q4 VOH CLK Q5 VOL Q4 Q5 VOH VOL VOL tCLRAH VOH RAS tCLCASL tCLCASH VOH CAS VOL tCHCAV A24 to A00 COLUMN address VOH VOL VOH VOL COLUMN address tCADH tCLDV D31 to D16 VIH VIL Read COLUMN address Read VIH VIL Read tCHDWH VOH DW tCHDV1 D31 to D16 80 VOH VOL Write VOH VOL VOH VOL Write MB91121 (11) Single DRAM Timing Parameter (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol Pin name Condition Value Unit Min. Max. 10 ns 10 ns tCHCASL2 CLK CAS tCHCASH2 n / 2 × tCYC +8 ns 10 ns ROW address delay time tCHRAV2 15 ns COLUMN address delay time tCHCAV2 15 ns 15 ns 15 ns 15 ns (1 − n / 2) × tCYC − 17 ns 0 — ns RAS delay time CAS delay time DW delay time tCLRAH2 tCHRAL2 tCHDWL2 tCHDWH2 Output data delay time tCHDV2 CAS ↓ → Valid data input time tCLDV2 CAS ↑ → data hold time tCADH2 CLK RAS CLK A24 to A00 CLK DW CLK D31 to D16 CAS D31 to D16 Remarks 81 MB91121 tCYC Q1 VOH CLK Q2 VOH VOL VOH RAS *1 Q4S Q3 Q4S VOH Q4S VOH VOH VOL tCHRAL2 tCLRAH2 tCHCASL2 tCHCASH2 VOH CAS VOH VOL VOH VOL A24 to A00 ROW address tCHRAV2 VOH VOL VOL VOHCOLUMN-0 VOL COLUMN-1 COLUMN-2 tCHCAV2 tCADH2 tCLDV2 D31 to D16 Read-0 DW VIH VIL Read-1 D31 to D16 VOH VOL Write-0 tCHDV2 VOH *2 VOH VOL tCHDWH2 VOH VOL Write-1 VOH VOH VOL VOL tCHDV2 *1 : Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. 82 Read-2 VOL tCHDWL2 *2 : VIH VIL indicates the timing when the bus cycle begins from the high speed page mode. Write-2 MB91121 (12) Hyper DRAM Timing Parameter RAS delay time (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol tCLRAH3 tCHRAL3 Pin name Condition CLK RAS Value Unit Remarks Min. Max. 10 ns 10 ns CAS delay time tCHCASL3 CLK tCHCASH3 CAS n / 2 × tCYC + 8 ns 10 ns ROW address delay time tCHRAV3 15 ns COLUMN address delay time tCHCAV3 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns tCYC − 20 ns 0 ns CLK A24 to A00 tCHRL3 RD delay time tCHRH3 CLK RD tCLRL3 DW delay time tCHDWL3 tCHDWH3 Output data delay time tCHDV3 CAS ↓→ valid data input time tCLDV3 CAS ↓→ data hold time tCADH3 CLK DW CLK D31 to D16 CAS D31 to D16 83 MB91121 tCYC Q1 Q2 VOH CLK VOH VOL VOH RAS *1 Q4H Q3 Q4H VOH Q4H VOH VOL VOH VOL tCHRAL3 tCLRAH3 tCHCASL3 tCHCASH3 VOH CAS VOL VOH VOL A24 to A00 ROW address tCHRAV3 VOH VOL VOHCOLUMN-0 VOL VOL VOL COLUMN-1 COLUMN-2 tCHCAV3 *2 VOL RD VOH VOL tCHRL3 tCHRH3 tCLRL3 tCLDV3 D31 to D16 tCADH3 Read-0 DW VIH VIL VOH VOL tCHDWL3 tCHDWH3 *2 D31 to D16 VOH VOL Write-0 tCHDV3 VOH VOL VOH VOL Write-1 VOH VOH VOL VOL tCHDV3 *1 : Q4H indicates Q4HR (Read) of Hyper DRAM cycle or Q4HW (Write) cycle. *2 : 84 VIH Read-1 VIL indicates the timing when the bus cycle begins from the high speed page mode. Write-2 MB91121 (13) CBR Refresh Parameter RAS delay time CAS delay time (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol Pin name tCLRAH CLK RAS tCHRAL tCLCASL CLK CAS tCLCASH tCYC R1 CLK RAS R2 Unit Min. Max. 10 ns 10 ns 10 ns 10 ns R3 VOH Remarks R4 VOH VOL VOL VOL VOH VOL tCLRAH CAS Value Condition tCHRAL VOH VOL tCLCASL tCLCASH DW 85 MB91121 (14) Self Refresh (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Parameter Symbol tCLRAH RAS delay time tCHRAL tCLCASL CAS delay time tCLCASH tCYC SR1 CLK VOH Pin name Condition CLK RAS CLK CAS SR2 SR3 VOH VOL Max. 10 ns 10 ns 10 ns 10 ns Remarks SR3 VOL RAS VOL tCLRAH VOH VOH VOL tCHCASL 86 Unit Min. VOH tCHRAL CAS Value tCLCASH MB91121 (15) UART Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCLK ↓ → SOUT delay time tSLOV Valid SIN → SCLK ↑ tIVSH SCLK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width Value Condition Unit Min. Max. SC0 to SC2 8tCYCP ns SC0 to SC2 SO0 to SO2 −80 80 ns 100 ns SC0 to SC2 SI0 to SI2 60 ns tSHSL SC0 to SC2 4tCYCP ns Serial clock “L” pulse width tSLSH SC0 to SC2 4tCYCP ns SCLK ↓ → SOUT delay time tSLOV SC0 to SC2 SO0 to SO2 150 ns Valid SIN → SCLK ↑ tIVSH 60 ns SCLK ↑ → valid SIN hold time tSHIX 60 ns Internal SC0 to SC2 shift clock mode SI0 to SI2 External shift clock SC0 to SC2 mode SI0 to SI2 SC0 to SC2 SI0 to SI2 Remarks Note : This rating is for AC characteristics in CLK synchronous mode. tCYCP is a cycle time of peripheral system clock • Internal shift clock mode tSCYC VOH SCLK VOL VOL tSLOV VOH VOL SOUT tSHIX tIVSH VIH VIL SIN VIH VIL • External shift clock mode tSLSH tSHSL VIH VIH SCLK VIL VIL tSLOV SOUT VOH VOL tIVSH SIN VIH VIL tSHIX VIH VIL 87 MB91121 (16) Trigger System Input Timing Parameter A/D start trigger input time External interrupt input time (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Symbol tTRGH tTRGL Pin name Condition ATG TRG0 to TRG3 Value Min. Max. 5tCYCP Unit ns Note : tCYCP is a cycle time of peripheral system clock tTRGH ATG TRG0 to TRG3 88 VIH tTRGL VIH VIL VIL Remarks MB91121 (17) DMA Controller Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C) Parameter Symbol Pin name DREQ input pulse width tDRWH DREQ0 to DREQ2 DACK delay time (Normal bus) (Normal DRAM) tCLDL EOP delay time (Normal bus) (Normal DRAM) DACK delay time (Single DRAM) (Hyper DRAM) EOP delay time (Single DRAM) (Hyper DRAM) tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH Condition CLK DACK0 to DACK2 CLK EOP0 to EOP2 CLK DACK0 to DACK2 CLK EOP0 to EOP2 Value Unit Min. Max. 2tCYC ns 6 ns 6 ns 6 ns 6 ns n / 2 × tCYC ns 6 ns n / 2 × tCYC ns 6 ns Remarks tCYC CLK VOH VOH VOL VOL tCLDL tCLEL DACK0 to DACK2 EOP0 to EOP2 (Normal bus) (Normal DRAM) tCLDH tCLEH VOH VOL DACK0 to DACK2 EOP0 to EOP2 (Single DRAM) (Hyper DRAM) VOH VOL tCHDL tCHEL tCHDH tDRWH DREQ0 to DREQ2 VIH VIH 89 MB91121 5. A/D Converter Block Electrical Characteristics (VCC = AVCC = AVRH = 3.3 V, AVSS = 0.0 V, TA = 0 °C to + 70 °C) Parameter Symbol Pin name Resolution Total error Value Unit Min. Typ. Max. 10 10 BIT ±5.0 LSB Linearity error ±3.5 LSB Differentiation linearity error ±2.0 LSB Zero transition voltage VOT AN0 to AN7 −1.5 +0.5 +2.5 LSB Full-scale transition voltage VFST AN0 to AN7 AVRH − 4.5 AVRH − 1.5 AVRH + 0.5 LSB Conversion time 5.6*1 µs Analog port input current IAIN AN0 to AN7 0.1 10 µA Analog input voltage VAIN AN0 to AN7 AVSS AVRH V AVRH AVSS AVCC V 4 mA 2 5* µA 200 µA 5*2 µA 5 LSB Reference voltage IA Power supply current IAH IR Reference voltage supply current IRH Conversion variance between channels AVCC AVRH AN0 to AN7 *1 : Machine clock = 25 MHz *2 : Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.3 V) Note : • As the absolute value of AVRH decreases, relative error increases. • Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 5 kΩ If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling. Analog input circuit example Sample-and-hold circuit Analog input C0 Comparator RON1 RON2 RON3 RON4 C1 RON1 : 0. 2 kΩ RON2 : 1. 4 kΩ RON3 : 1. 4 kΩ RON4 : 0. 2 kΩ C0 : 16.6 pF C1 : 4.0 pF Note : These values are given for reference purposes. 90 MB91121 6. A/D Converter Glossary • Resolution The smallest change in analog voltage detected by A/D converter. • Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000 0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”) . • Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage. Linearity error 3FF Differential linearity error Ideal characteristic Actual conversion characteristic N+1 3FE {1 LSB × (N − 1) + VOT} Actual conversion characteristic Digital output Digital output 3FD VFST (measured value) 004 VNT (measured value) 003 N N−1 Actual conversion characteristic V(N + 1)T VNT (measured value) (measured value) 002 Ideal characteristic N−2 001 VOT (measured value) AVRL Actual conversion characteristic Linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = AVRL AVRH Analog input VNT − {1 LSB × (N − 1) + VOT} 1 LSB V(N + 1)T − VNT 1 LSB VFST − VOT 1022 −1 Analog input AVRH [LSB] [LSB] [V] VOT: A voltage for causing transition of digital output from (000)H to (001)H VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H VNT: A voltage for causing transition of digital output from (N − 1)H to N 91 MB91121 • Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error. Total error 3FF 1.5 LSB 3FE Actual conversion characteristic Digital output 3FD {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (measured value) 003 Actual conversion characteristic 002 Ideal characteristic 001 0.5 LSB AVRL Total error of digital output N = 1 LSB (ideal value) = AVRH Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} AVRH − AVRL 1024 1 LSB [V] VOT (ideal value) = AVRL + 0.5 LSB [V] VFST (ideal value) = AVRL − 1.5 LSB [V] VNT: A voltage for causing transition of digital output from (N − 1) to N 92 [LSB] MB91121 ■ EXAMPLE CHARACTERISTICS (1) Power Supply Current Power supply current-Power supply voltage Power supply current (sleeping) -Power supply voltage 120 160 140 100 120 ICC (mA) 25 MHz 50 MHz 80 60 ICCS (mA) 80 100 25 MHz 50 MHz 60 40 40 20 20 0 2.7 3 3.3 3.6 0 2.7 3.9 3 100 100 90 90 80 80 70 70 60 60 50 50 MHz 40 3.9 50 30 30 20 10 10 0 0 -10 2.7 -10 2.7 3.6 3.9 50 MHz 40 20 3.3 VCC (V) 3.6 A/D power supply current-Power supply voltage IA (mA) ICCH (mA) Power supply current (stopping) -Power supply voltage 3 3.3 VCC (V) VCC (V) 3 3.3 VCC (V) 3.6 3.9 A/D reference power supply current -Power supply voltage 180 160 140 IR (mA) 120 100 50 MHz 80 60 40 20 0 2.7 3 3.3 3.6 3.9 VCC (V) 93 MB91121 (2) Output Voltage “H” output voltage-Power supply voltage “L” output voltage-Power supply voltage 100 4 3.8 3.6 90 3.2 VOL (mV) VOH (V) 3.4 3 2.8 2.6 80 70 2.4 2.2 2 2.7 3 3.3 3.6 3.9 (3) Pull-up Resistance Pull-up resistance-Power supply voltage R (kΩ) 100 10 3 3.3 VCC (V) 94 3 3.3 VCC (V) VCC (V) 2.7 60 2.7 3.6 3.9 3.6 3.9 MB91121 ■ ORDERING INFORMATION Part number MB91121PFV Package Remarks 120-pin Plastic LQFP (FPT-120P-M21) 95 MB91121 ■ PACKAGE DIMENSION 120-pin plastic LQFP (FPT-120P-M21) 18.00±0.20(.709±.008)SQ 16.00±0.10(.630±.004)SQ 90 61 91 60 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 0~8° 120 LEAD No. 1 30 0.50(.020) C 96 "A" 31 2001 FUJITSU LIMITED F120033S-c-3-3 0.22±0.05 (.009±.002) +0.05 0.08(.003) M 0.145 –0.03 +.002 .006 –.001 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) Dimensions in mm (inches) MB91121 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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