FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16312-1E
32-bit Proprietary Microcontrollers
CMOS
FR30 Family
MB91151A Series
MB91151A
■ DESCRIPTION
The MB91151A is a single-chip microcontroller using a 32-bit RISC-CPU (FR30 family) as its core.
■ FEATURES
CPU
• 32-bit RISC (FR30) , load/store architecture, 5-stage pipeline
• General-purpose registers : 32 bits × 16
• 16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle
• Memory-to-memory transfer, bit processing, barrel shift processing : Optimized for embedded applications
• Function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language description
• Branch instructions with delay slots : Reduced overhead time in branching executions
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC and PS saving) : 6 cycles, 16 priority levels
(Continued)
■ PACKAGE
144-pin plastic LQFP
(FPT-144P-M08)
MB91151A
(Continued)
Bus Interface
• 16-bit address output, 8/16-bit data input and output
• Basic bus cycle : 2-clock cycle
• Support for interface for various types of memory
• Unused data/address pins can be configured as input/output ports
• Support for little endian mode
Internal RAM
Instruction RAM : 2 Kbytes
Data RAM
: 32 Kbytes
DMAC
DMAC in descriptor format for placing transfer parameters on to the main memory.
Capable of transferring a maximum of eight internal and external factors combined.
Three channels for external factors
Bit Search Module
Searches in one cycle for the position of the bit that changes from the MSB in one word to the initial 1/0.
Timers
• 16-bit OCU × 8 channels, ICU × 4 channels, Free-run timer × 1 channel
• 8/16-bit up/down timer/counter (8-bit × 2 channels or 16-bit × 1 channel)
• 16-bit PPG timer × 6 channels. The output pulse cycle and duty can be varied as desired.
• 16-bit reload timer × 4 channels
D/A Converter
• 8-bit × 3 channels
A/D Converter (Sequential Comparison Type)
• 10-bit × 8 channels
• Sequential conversion method (conversion time : 5.0 µs@33 MHz)
• Single conversion or scan conversion can be selected, and one-shot or continuous or stop conversion mode
can be set respectively.
• Conversion starting function by hardware/software.
Serial I/O
• UART × 4 channels. Any of them is capable of serial transfer in sync with clock attached with the LSB/MSB
switching function.
• Serial data output and serial clock output are selectable by push-pull/open drain software.
• A 16-bit timer (U-timer) is contained as a dedicated baud rate generator allowing any baud rate to be generated.
Clock Switching Function
• Gear function : Operating clock ratios to the basic clock can be set independently for the CPU and peripherals
from four types, 1 : 1, 1 : 2, 1 : 4 or 1 : 8.
Interrupt Controller
External interrupt input (16 channels in total)
• Allows the rising edge/falling edge/H level/L level to be set.
Internal interrupt factors
• Interrupt by resources and delay interrupt
Others
• Reset cause : Power on reset/watchdog timer/software reset/external reset
• Low power consumption mode : Sleep/stop
• Package : 144-pin LQFP
• CMOS technology (0.35 µm)
• Power supply voltage : 3.15 V to 3.6 V
2
MB91151A
■ PIN ASSIGNMENT
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PH5/SCK1/TO1
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
PI5/SCK3/TO3
VSS
PJ0
PJ1
VSS
VCC
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
VCC
PD7/ATG/INT15
PD6/DEOP2/INT14
PD5/ZIN1/INT13/TRG5
PD4/ZIN0/INT12/TRG4
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P61/A17
P62/A18
P63/A19
P64/A20
P65/A21
P66/A22
P67/A23
VSS
P80/RDY
P81/BGRNT
P82/BRQ
P83/RD
P84/WR0
P85/WR1
P86/CLK
MD2
MD1
MD0
RST
VCC
X1
X0
VSS
PC0/INT0
PC1/INT1
PC2/INT2
PC3/INT3
PC4/INT4/CS0
PC5/INT5/CS1
PC6/INT6/CS2
PC7/INT7/CS3
VCC
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
VSS
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
VSS
VCC
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSS
OPEN
OPEN
OPEN
VCC
PK7/AN7
PK6/AN6
PK5/AN5
PK4/AN4
PK3/AN3
PK2/AN2
PK1/AN1
PK0/AN0
AVSS
AVRL
AVRH
AVCC
DAVC
DAVS
DA0
DA1
DA2
VCC
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0
PL1/DACK0
PL0/DREQ0
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
(TOP VIEW)
(FPT-144P-M08)
3
MB91151A
■ PIN DESCRIPTION
Circuit
type
Pin No.
Pin name
1
2
3
4
5
6
7
8
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
C
Bit 16 to bit 23 of external data bus
These pins are activated only in 16-bit external bus mode.
These pins are available as ports in single-chip and 8-bit external bus
modes.
10
11
12
13
14
15
16
17
D24/P30
D25/P31
D26/P32
D27/P33
D28P34
D29/P35
D30/P36
D31/P37
C
Bit 24 to bit 31 of external data bus
These pins are available as ports in single-chip mode.
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57
F
Bit 0 to bit 15 of external address bus
These pins are activated in external bus mode.
These pins are available as ports in single-chip mode.
36
37
38
39
40
41
42
43
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
O
Bit 16 to bit 23 of external address bus
These pins are available as ports when the address bus is not in use.
C
External RDY input
This function is activated when external RDY input is allowed.
Input “0” when the bus cycle being executed does not end.
This pin is available as a port when external RDY input is not in use.
45
RDY/P80
Function
(Continued)
4
MB91151A
Pin No.
46
47
Pin name
BGRNT/P81
BRQ/P82
Circuit
type
Function
F
External bus release acceptance output
This function is activated when external bus release acceptance output is
allowed.
Output “L” upon releasing of the external bus.
This pin is available as a port when external bus release acceptance output is not allowed.
C
External bus release request input
This function is activated when external bus release request input is allowed.
Input “1” when the release of the external bus is desired.
This pin is available as a port when external bus release request input is
not in use.
48
RD/P83
F
External bus read strobe output
This function is activated when external bus read strobe output is allowed.
This pin is available as a port when external bus read strobe output is not
allowed.
49
WR0/P84
F
External bus write strobe output
This function is activated in external bus mode.
This pin is available as a port in single chip mode.
50
WR1/P85
F
External bus write strobe output
This function is activated in external bus mode when the bus width is 16
bits.
This pin is available as a port in single chip mode or when the external bus
width is 8 bits.
51
CLK/P86
F
System clock output
The pin outputs the same clock as the external bus operating frequency.
The pin is available as a port when it is not used to output the clock.
52
53
54
MD2
MD1
MD0
G
Mode pins
To use these pins, connect them directly to either VCC or VSS.
Use these pins to set the basic MCU operating mode.
55
RST
B
External reset input
57
58
X1
X0
A
High-speed clock oscillation pins
H
External interrupt request input 0-3
Since this input is used more or less continuously when the corresponding
external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately.
Since this port is allowed to input also in standby mode, it can be used to
reset the standby state.
These pins are available as ports when external interrupt request input is
not in use.
60
61
62
63
INT0/PC0
INT1/PC1
INT2/PC2
INT3/PC3
(Continued)
5
MB91151A
Pin No.
64
65
66
67
69
70
71
72
73
74
75
76
Pin name
INT4/PC4/CS0
INT5/PC5/CS1
INT6/PC6/CS2
INT7/PC7/CS3
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3
PD4/ZIN0/INT12/TRG4
PD5/ZIN1/INT13/TRG5
PD6/DEOP2/INT14
PD7/ATG/INT15
Circuit
type
Function
H
These pins also serve as the chip select output and external interrupt request input 4 to 7.
When the chip select output is not allowed, these pins are available
as external interrupt requests or ports.
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
Since this port is also allowed to input in standby mode, the port can
be used to reset the standby state.
These pins are available as ports when external interrupt request
input and chip select output are not in use.
H
External interrupt request input 8 to 13
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[AIN, BIN] Up/down timer input.
[TRG] PPG external trigger input.
Since this input is used more or less continuously while input is allowed, output by the port needs to be stopped except when it is performed deliberately.
These pins are available as ports when the external interrupt request input, up timer counter input, and PPG external trigger input
are not in use.
H
External interrupt request input 14
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[DEOP2] DMA external transfer end output.
This function is activated when DMAC external transfer end output
is allowed.
This pin is available as a port when it is not in use as the external
interrupt request input or DMA external transfer end output.
H
External interrupt request input 15
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[ATG] A/D converter external trigger input.
Since this input is used more or less continuously when selected as
an A/D activation factor, output by the port needs to be stopped except when it is performed deliberately.
This pin is available as a port when it is not in use as the external
interrupt request input or A/D converter external trigger input.
(Continued)
6
MB91151A
Pin No.
Pin name
Circuit
type
Function
78
79
80
81
82
83
84
85
PE0/OC0
PE1/OC1
PE2/OC2
PE3/OC3
PE4/OC4
PE5/OC5
PE6/OC6
PE7/OC7
F
Output compare output
These pins are available as ports when output compare output is not allowed.
86
87
88
89
PF0/IN0
PF1/IN1
PF2/IN2
PF3/IN3
F
Input capture input
This function is activated when the input capture operation is input.
These pins are available as ports when input capture input is not in use.
90
PF4
F
General I/O port
91
92
93
94
95
96
PG0/PPG0
PG1/PPG1
PG2/PPG2
PG3/PPG3
PG4/PPG4
PG5/PPG5
F
PPG timer output
This function is activated when PPG timer output is allowed.
These pins are available as ports when PPG timer output is not allowed.
99
100
PJ1
PJ0
Q
General I/O port
102
PI5/SCK3/TO3
P
UART3 clock I/O, Reload timer 3 output
When UART3 clock output is not allowed, reload timer 3 can be output by
allowing it.
This pin is available as a port when neither UART3 clock output nor reload
timer output is allowed.
103
PI4/SOT3
P
UART3 data output
This function is activated when UART3 data output is allowed.
This pin is available as a port when UART3 clock output is not allowed.
P
UART3 data input
Since this input is used more or less continuously while UART3 is engaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART3 output data input is not in use.
104
PI3/SIN3
(Continued)
7
MB91151A
Pin No.
Pin name
Circuit
type
Function
105
PI2/SCK2/TO2
P
UART2 clock I/O, Reload timer 2 output
When UART2 clock output is not allowed, reload timer 2 can be output by
allowing it.
This pin is available as a port when neither UART2 clock output nor reload
timer output is allowed.
106
PI1/SOT2
P
UART2 data output
This function is activated when UART2 data output is allowed.
This pin is available as a port when UART2 clock output is not allowed.
P
UART2 data input
Since this input is used more or less continuously while UART2 is engaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART2 data input is not in use.
107
PI0/SIN2
108
PH5/SCK1/TO1
P
UART1 clock I/O, Reload timer 1 output
When UART1 clock output is not allowed, reload timer 1 can be output by
allowing it.
This pin is available as a port when neither UART1 clock output nor reload
timer output is allowed.
109
PH4/SOT1
P
UART1 data output
This function is activated when UART1 data output is allowed.
This pin is available as a port when UART1 clock output is not allowed.
P
UART1 data input
Since this input is used more or less continuously while UART1 is engaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART1 data input is not in use.
110
PH3/SIN1
111
PH2/SCK0/TO0
P
UART0 clock I/O, Reload timer 0 output
When UART0 clock output is not allowed, reload timer 0 can be output by
allowing it.
This pin is available as a port when neither UART0 clock output nor reload
timer output is allowed.
112
PH1/SOT0
P
UART0 data output
This function is activated when UART0 data output is allowed.
This pin is available as a port when UART0 clock output is not allowed.
P
UART0 data input
Since this input is used more or less continuously while UART0 is engaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART0 data input is not in use.
F
DMA external transfer request input
Since this input is used more or less continuously when selected as a
DMAC transfer factor, output by the port needs to be stopped except when
it is performed deliberately.
This pin is available as a port when DMA external transfer request input is
not in use.
113
114
PH0/SIN0
DREQ0/PL0
(Continued)
8
MB91151A
Pin No.
Pin name
Circuit
type
Function
115
DACK0/PL1
F
DMA external transfer request acceptance output
This function is activated when the DMAC external transfer request acceptance is allowed to be output.
This pin is available as a port when the DMAC transfer request acceptance is not allowed to be output.
116
DEOP0/PL2
F
DMA external transfer end output
This function is activated when the end of DMAC external transfer is allowed to be output.
F
DMA external transfer request input
Since this input is used more or less continuously when selected as a
DMAC transfer factor, output by the port needs to be stopped except when
it is performed deliberately.
This pin is available as a port when DMA external transfer request input is
not in use.
117
DREQ1/PL3
118
DACK1/PL4
F
DMA external transfer request acceptance output
This function is activated when the DMAC external transfer request acceptance is allowed to be output.
This pin is available as a port when DMAC transfer request acceptance
output is not allowed.
119
DEOP1/PL5
F
DMA external transfer end output
This function is activated when the end of DMAC external transfer is allowed to be output.
F
DMA external transfer request input
Since this input is used more or less continuously when selected as a
DMAC transfer factor, output by the port needs to be stopped except when
it is performed deliberately.
This pin is available as a port when DMA external transfer request input is
not in use.
120
DREQ2/PL6
121
DACK2/PL7
F
DMA external transfer request acceptance output
This function is activated when the DMAC external transfer request acceptance is allowed to be output.
This pin is available as a port when DMAC transfer request acceptance
output is not allowed.
123
124
125
DA2
DA1
DA0
D/A converter output
This function is activated when D/A converter output is allowed.
126
DAVS
Power supply pin for the D/A converter
127
DAVC
Power supply pin for the D/A converter
128
AVCC
Vcc power supply for the A/D converter
129
AVRH
A/D converter reference voltage (high potential side)
Be sure to turn on/off this pin with potential higher than AVRH applied to
VCC.
130
AVRL
A/D converter reference voltage (low potential side)
131
AVSS
VSS power supply for the A/D converter
(Continued)
9
MB91151A
(Continued)
Circuit
type
Function
AN0/PK0
AN1/PK1
AN2/PK2
AN3/PK3
AN4/PK4
AN5/PK5
AN6/PK6
AN7/PK7
N
A/D converter analog input
These pins are activated when the AIC register is designated for analog input.
These pins are available as ports when A/D converter analog input is
not in use.
27, 56, 68,
77, 97,
122, 140
VCC
Power supply pin (VCC) for digital circuit
Always power supply pin (VCC) must be connected to the power
supply.
9, 26, 44,
59, 98,
101, 144
VSS
Earth level (VSS) for digital circuit
Always power supply pin (VSS) must be connected to the power
supply.
Pin No.
Pin name
132
133
134
135
136
137
138
139
Note : On the majority of pins listed above, the I/O port and the resource I/O are multiplexed, such as XXXX/Pxx.
When the port and the resource output compete against each other on these pins, priority is given to the
resource.
10
MB91151A
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Xout
A
• High-speed oscillation circuit
Oscillation feedback resistor
= approx. 1 MΩ
X0
Standby control signal
• CMOS hysteresis input pin
CMOS hysteresis input
(standby control not attached)
Pull-up resistor
B
Digital input
Pout
Nout
C
• CMOS level I/O pin
CMOS level output
CMOS level input
(attached with standby control)
IOL = 4 mA
R
CMOS input
Standby control
Pout
Nout
F
• CMOS hysteresis I/O pin
CMOS level output
CMOS hysteresis input
(attached with standby control)
IOL = 4 mA
R
Hysteresis input
Standby control
(Continued)
11
MB91151A
Type
Circuit
Remarks
• CMOS level input pin
CMOS level input
(standby control not attached)
G
R
Digital input
Pull-up control
Pout
R
H
Nout
• CMOS hysteresis I/O pin with
pull-up control
CMOS level output
CMOS level input
(standby control not attached)
Pull-up resistance
= approx. 50 kΩ (Typ)
R
Hysteresis input
Pout
Nout
N
R
CMOS input
IOL = 4 mA
• Analog/CMOS level I/O pin.
CMOS level output
CMOS level input
(attached with standby control)
Analog input (Analog input is enabled when AIC’s corresponding
bit is set to “1.”)
IOL = 4 mA
Standby control
Analog input
(Continued)
12
MB91151A
(Continued)
Type
Circuit
Remarks
Pull-up control
Pout
R
O
Nout
R
Hysteresis input
• CMOS hysteresis I/O pin
with pull-up control
CMOS level output
CMOS hysteresis input
(attached with standby control)
Pull-up resistance
= approx. 50 kΩ (Typ)
IOL = 4 mA
Standby control
Pull-up control
Open drain control
R
P
Nout
R
• CMOS hysteresis I/O pin
with pull-up control.
CMOS level output
(attached with open drain control)
CMOS hysteresis input
(attached with standby control)
Pull-up resistance
= approx. 50 kΩ (Typ)
Hysteresis input
Standby control
Nout
Q
IOL = 4 mA
• Open drain I/O pin
• 5 V tolerance of voltage
• CMOS hysteresis input
(attached with standby control)
IOL = 15 mA
R
Hysteresis input
Standby control
13
MB91151A
■ HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over
rating across VCC and VSS may cause latchup.
This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.
2. Treatment of Pins
• Treatment of unused pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
• Treatment of open pins
Be sure to use open pins in open state.
• Treatment of output pins
Shortcircuiting an output pin with the power supply or with another output pin or connecting a large-capacity
load may causes a flow of large current. If this conditions continues for a lengthy period of time, the device
deteriorates. Take great care not to exceed the absolute maximum ratings.
• Mode pins (MD0-MD2)
These pins should be used directly connected to either VCC or VSS. In order to prevent noise from causing
accidental entry into test mode, keep the pattern length as short as possible between each mode pin and VCC
or VSS on the board and connect them with low impedance.
• Power supply pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside
of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,
to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and
to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND.
It is preferred to connect VCC and VSS of MB91151A to power supply with minimal impedance possible.
It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC and
VSS at a position as close as possible to MB91151A.
• Crystal oscillator circuit
Noises around X0 and X1 pins may cause malfunctions of MB91151A. In designing the PC board, layout X0
and X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.
It is strongly recommended to design PC board so that X0, X1 pins are surrounded by grounding area for stable
operation
3. Precautions
• External Reset Input
It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly.
• External Clocks
When using an external clock, normally, a clock of which the phase is opposite to that of X0 must be supplied
to the X0 and X1 pins simultaneously. However, when using the clock along with STOP (oscillation stopped)
mode, the X1 pin stops when “H” is input in STOP mode. To prevent one output from competing against another,
an external resistor of about 1 kΩ should be provided.
The following figure shows an example usage of an external clock.
An example usage of an external clock
X0
X1
14
MB91151A
MB91151A
4. Caution During Powering Up
• When powering up
When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power
supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycles, then set to “H” level.
• Source oscillation input
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing
waiting.
• Power on resetting
When powering up or when turning the power back on after the supply voltage drops below the operation
assurance range, be sure to reset the power.
• Power on sequence
Turn on the power in the order of VCC, AVCC and AVRH. The power should be disconnected in inverse order.
• Even when an AD converter is not in use, connect AVCC to the VCC level and AVSS to the VSS level.
• Even when a DA converter is not in use, connect DAVC to the VCC level and DAVS to the VSS level.
15
MB91151A
■ BLOCK DIAGRAM
M
O
D
E
FR30 CPU Core
I - Bus
D - Bus
( )
MD0
MD1
MD2
RST
4
Instruction
Cache 1KB
External
Interrupt
16
PD7/INT15/ATG (I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
PD2/INT10/AIN1
PD1/INT9/BIN0 (I)
PD0/INT8/AIN0 (I)
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0 (I)
External
Bus CTL
( )
P
O
R
T
UART 4 ch
UTIMER 4 ch
6
16 bit
Reload Timer
4 ch
P
O
R
T
16 bit
Free RUN Timer
1 ch
16 bit PPG
L
P
O
R
T
16 bit
Output Compare
8 ch
K
10 bit 8 input
A/D converter
D
8
P
O
R
T
C
8
8 bit
Up/Down
Counter
2 ch
External
Interrupt
16 ch
P
O
R
T
J
2
16 bit
Input Capture
4 ch
( )
Interrupt
Controller
I
6
6 ch
8
Clock
Control
H
( )
C - Bus
RAM
2 KB
P
O
R
T
( )
( )
P
O
R
T
D - Bus
7
OSC
(2)
G
( )
X0 (I)
X1 (I)
I - Bus
)
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0 (O)
PL1/DACK0 (O)
PL0/DREQ0 (I)
R - Bus
6
8
(
Up/Down
Counter
P
O
R
T
)
A/D
DMAC
P86/CLK (O)
P85/WR1 (O)
P84/WR0
P83/RD (O)
P82/BRQ (I)
P81/BGRNT (O)
P80/RDY (I)
(
Clock
( )
∼
DMAC
24
P
O
R
T
Bit Search
D - Bus
8
8
P
O
R
T
F
( )
∼
Bus
Control
P40/A00
DMAC 8 ch
( )
P
O
R
T
6
/
5
/
4
∼
P67/A23 (O)
∼
16
P50/A08
P47/A07
E
( )
∼
∼
P20/D16
P
O
R
T
Data RAM
32 KB
( )
P30/D24
P27/D23
P60/A16
P57/A15
Address
∼
∼
DATA
P
O
R
T
3
/
2
5
8 bit 3 output
D/A converter
D
A
( )
P37/D31 (IO)
3
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
Output
Compare
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PPG
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
UART
PH5/SCK1/TO1 TOX:
Reload
PI0/SIN2
Timer
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
PI5/SCK3/TO3
PJ0
PJ1
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
DA2
DA1
DA0
A/D
Input
Capture
MB91151A
■ CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory
space.
• Direct addressing area
The following area in the address space is used for I/O.
This area is called direct addressing area and an operand address can be specified directly in an instruction.
The direct addressing area varies with the data size to be accessed as follows :
→ byte data access :
000H-0FFH
→ half word data access : 000H-1FFH
→ word data access :
000H-3FFH
2. Memory Map
External bus mode
Serial start up mode
I/O
I/O
Direct
addressing
area
I/O
I/O
See "■ I/O MAP"
Not accessible
Not accessible
32 KB
internal RAM
32 KB
internal RAM
Not accessible
Not accessible
0000 0000H
0000 0400H
0000 0800H
0000 1000H
0000 9000H
0001 0000H
0001 0000H
Not accessible
0008 0000H
2 KB internal RAM
External area
0008 0800H
Not accessible
000F F800H
Serial ROM 2KB
0010 0000H
Not accessible
FFFF FFFFH
FFFF FFFFH
17
MB91151A
3. Registers
The family of FR microcontrollers has two types of registers : the registers residing in the CPU which are dedicated
to applications and the general-purpose registers residing in the memory.
• Dedicated registers :
Program counter (PC)
Program status (PS)
Tablebase register (TBR)
: A 32-bit register to indicate the location where an instructions is stored.
: A 32-bit register to store a register pointer or a condition code.
: Holds the vector table lead address used when EIT (exceptions/interrupt/
trap) is processed.
Return pointer (RP)
: Holds the address to return from a subroutine.
System stack pointer (SSP) : Points to the system stack space.
User stack pointer (USP)
: Points to the user stack space.
Multiplication and division result register (MDH/MDL) : A 32-bit multiplication and division register.
Initial value
32 bit
PC
Program counter
PS
Program status
XXXX XXXXH (Undefined)
Tablebase register
000F FC00H
Return pointer
XXXX XXXXH (Undefined)
SSP
System stack pointer
0000 0000H
USP
User stack pointer
XXXX XXXXH (Undefined)
TBR
RP
MDH
Multiplication and division register
XXXX XXXXH (Undefined)
XXXX XXXXH (Undefined)
MDL
• Program status (PS)
The PS register holds program status and is further divided into three registers which are a Condition Code
Register (CCR) , a System condition Code Register (SCR) , and an Interrupt Level Mask register (ILM) .
31
PS
20
19
18
16
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
18
17
10
9
8
7
6
5
4
3
2
1
0
D1
D0
T
S
I
N
Z
V
C
SCR
CCR
MB91151A
• Condition Code Register (CCR)
S flag : Designates the stack pointer for use as R15.
I flag
: Controls enabling and disabling of user interrupt requests.
N flag : Indicates the sign when arithmetic operation results are considered to be an integer represented
by 2’s complement.
Z flag : Indicates if arithmetic results were “0.”
V flag : Considers the operand used for an arithmetic operation to be an integer represented by 2’s complement and indicates if the operation resulted in an overflow.
C flag : Indicates whether or not an arithmetic operation resulted in a carry or a borrow from the most significant bit.
• System condition Code Register (SCR)
T flag : Designates whether or not to enable step trace trap.
• Interrupt Level Mask register (ILM)
ILM4 to ILM0
: Holds an interrupt level mask value to be used for level masking.
An interrupt request is accepted only if the corresponding interrupt level among interrupt
requests input to the CPU is higher than the value indicated by the ILM register.
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt level
High-Low
0
0
0
0
0
0
Higher
0
1
0
0
0
15
1
1
1
1
1
31
Lower
19
MB91151A
■ Instruction Cache
• Description
The instruction cache is a temporary storage memory. In the event that the instruction codes are accessed from
a low speed external memory, it holds the accessed codes internally, and is used to increase the access speed
for all subsequent accesses.
Direct read or write access can not be done by instruction cache or instruction cache tag using software.
• Instruction cache configuration
• Basic instruction length of FR series : 2 bytes
• Block layout : 2-way set associative type
• Block
1 way is configured of 32 blocks.
1 block is 16 bytes ( = 4 sub blocks)
1 sub block is 4 bytes ( = 1 bus access unit)
• Instruction Cache Configuration
Cash tag
4 bytes
I3
4 bytes
I2
4 bytes
I1
4 bytes
I0
Cash tag
Sub clock 3
Sub clock 2
Sub clock 1
Sub clock 0
Clock 0
Cash tag
Sub clock 3
Sub clock 2
Sub clock 1
Sub clock 0
Clock 31
Cash tag
Sub clock 3
Sub clock 2
Sub clock 1
Sub clock 0
Clock 0
Cash tag
Sub clock 3
Sub clock 2
Sub clock 1
Sub clock 0
Clock 31
Way 1
32 blocks
Way 2
32 blocks
20
MB91151A
■ GENERAL-PURPOSE REGISTERS
General-purpose registers are CPU registers R0 through R15 and used as accumulators during various operations and as memory access pointers (fields indicating addresses) .
• Register Bank Configuration
32 bits
R0
Initial value
XXXX XXXXH
R1
R12
R13
AC (Accumulator)
R14
FP (Frame Pointer)
XXXX XXXXH
R15
SP (Stack Pointer)
0000 0000H
Of the 16 general-purpose registers, the following registers are assumed for specific applications. For this reason,
some instructions are enhanced.
R13 : Virtual accumulator (AC)
R14 : Frame pointer (FP)
R15 : Stack pointer (SP)
Initial values to which R0 through R14 are reset are not defined. The initial value of R15 is 0000 0000H (the SSP
value) .
21
MB91151A
■ MODE SETTING
1. Mode Pins
As shown below, three pins, MD2, MD1, and MD0 are used to indicate an operation.
Mode pins and set modes
Mode pin
Reset vector
External data
Mode name
access area
bus width
MD2 MD1 MD0
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
0
1
0
External vector mode 2
External
32 bits
0
1
1
External vector mode
Internal
(Mode register)
1
Bus modes
External bus mode
Not available on this
product type
Single-chip mode*
Not available
* : Not available on this product type
2. Mode Data
The data which the CPU writes to “0000 07FFH” after reset is called mode data.
It is the mode register (MODR) that exists at “0000 07FFH.” Once a mode is set in this register, operations will
take place in that mode. The mode register can be written only once after reset.
The mode specified in the register is enabled immediately after it is written.
MODR
Address : 0000 07FFH
M1
M0
∗
∗
∗
∗
∗
∗
Initial value Access
XXXXXXXX
W
Bus mode setting bits
W : Write only, X : Undefined
[bits 7 and 6] : M1, M0
These are bus mode setting bits. Specify the bus mode to be set to after writing to the mode register.
M1
M0
Function
Remarks
0
0
Single-chip mode
0
1
Internal RAM-external bus mode
1
0
External bus mode
1
1
Setting not allowed
Setting not allowed
Note : Of the above options, only “01” or “10“ should be set for this model.
[bits 5 to 0] : ∗
These bits are reserved for the system.
“0” should be written to these bits at all times.
22
MB91151A
[Precautions When Writing to the MODR]
Before writing to the MODR, be sure to set AMD0 through AMD5 and determine the bus width in each CS (Chip
Select) area.
The MODR does not have bus width setting bits.
The bus width value set with mode pins MD2 through MD0 is enabled before writing to the MODR and the bus
width value set with BW1 and BW0 of AMD0 through AMD5 is enabled after writing to the MODR.
For example, the external reset vector is normally executed with area 0 (the area where CS0 is active) and the
bus width at that time is determined by pins MD2 through MD0. Suppose that the bus width is set to 32 or 16
bits in MD2 though MD0 but no value is specified in AMD0. If the MODR is written in this state, area 0 then
switches to 8-bit bus mode and operates the bus since the initial bus width in AMD0 is set to 8 bits. This causes
a malfunction.
In order to prevent this type of problem, AMD0 through AMD5 must always be set before writing to the MODR.
Writing to the MODR.
RST (Reset)
Designated bus width : MD2,MD1,MD0
AMD0 to AMD5 BW1, BW0
23
MB91151A
■ I/O MAP
Address
Register
+0
+1
000000H
PDR3 (R/W)
XXXXXXXX
PDR2 (R/W)
XXXXXXXX
000004H
PDR6 (R/W)
XXXXXXXX
+2
PDR5 (R/W)
XXXXXXXX
PDR4 (R/W)
XXXXXXXX
PDR8 (R/W)
- XXXXXXX
00000CH
Port Data Register
000010H
PDRF (R/W)
- - - XXXXX
PDRE (R/W)
XXXXXXXX
PDRD (R/W)
XXXXXXXX
PDRC (R/W)
XXXXXXXX
000014H
PDRJ (R/W)
- - - - - - 11
PDRI (R/W)
- - XXXXXX
PDRH (R/W)
- - XXXXXX
PDRG (R/W)
- - XXXXXX
PDRL (R/W)
XXXXXXXX
PDRK (R/W)
XXXXXXXX
000018H
Block
000008H
+3
00001CH
SSR0 (R, R/W)
00001000
SIDR0/SODR0
(R, W)
XXXXXXXX
SCR0 (R/W, W)
00000100
SMR0 (R/W)
00000 - 00
UART0
000020H
SSR1 (R, R/W)
00001000
SIDR1/SODR1
(R, W)
XXXXXXXX
SCR1 (R/W, W)
00000100
SMR1 (R/W)
00000 - 00
UART1
000024H
SSR2 (R, R/W)
00001000
SIDR2/SODR2
(R, W)
XXXXXXXX
SCR2 (R/W, W)
00000100
SMR2 (R/W)
00000 - 00
UART2
000028H
SSR3 (R, R/W)
00001000
SIDR3/SODR3
(R, W)
XXXXXXXX
SCR3 (R/W, W)
00000100
SMR3 (R/W)
00000 - 00
UART3
00002CH
TMRLR0 (W)
XXXXXXXX XXXXXXXX
TMR0 (R)
XXXXXXXX XXXXXXXX
000030H
TMCSR0 (R/W)
- - - - 0000 00000000
000034H
TMRLR1 (W)
XXXXXXXX XXXXXXXX
TMR1 (R)
XXXXXXXX XXXXXXXX
000038H
TMCSR1 (R/W)
- - - - 0000 00000000
00003CH
TMRLR2 (W)
XXXXXXXX XXXXXXXX
TMR2 (R)
XXXXXXXX XXXXXXXX
TMCSR2 (R/W)
- - - - 0000 00000000
000040H
Reload Timer 0
Reload Timer 1
Reload Timer 2
(Continued)
24
MB91151A
Address
000044H
Register
+0
+1
+2
+3
TMRLR3 (W)
XXXXXXXX XXXXXXXX
TMR3 (R)
XXXXXXXX XXXXXXXX
TMCSR3 (R/W)
- - - - 0000 00000000
000048H
00004CH
CDCR1 (R/W)
0 - - - 0000
CDCR0 (R/W)
0 - - - 0000
000050H
CDCR3 (R/W)
0 - - - 0000
CDCR2 (R/W)
0 - - - 0000
000054H
to
000058H
RCR1 (W)
00000000
RCR0 (W)
00000000
UDCR1 (R)
00000000
UDCR0 (R)
00000000
000060H
CCRH0 (R/W)
00000000
CCRL0 (R/W, W)
- 000X000
CSR0 (R/W, R)
00000000
000064H
CCRH1 (R/W)
- 0000000
CCRL1 (R/W, W)
- 000X000
CSR1 (R/W, R)
00000000
000068H
IPCP1 (R)
XXXXXXXX XXXXXXXX
IPCP0 (R)
XXXXXXXX XXXXXXXX
00006CH
IPCP3 (R)
XXXXXXXX XXXXXXXX
IPCP2 (R)
XXXXXXXX XXXXXXXX
ICS23 (R/W)
00000000
OCCP1 (R/W)
XXXXXXXX XXXXXXXX
OCCP0 (R/W)
XXXXXXXX XXXXXXXX
000078H
OCCP3 (R/W)
XXXXXXXX XXXXXXXX
OCCP2 (R/W)
XXXXXXXX XXXXXXXX
00007CH
OCCP5 (R/W)
XXXXXXXX XXXXXXXX
OCCP4 (R/W)
XXXXXXXX XXXXXXXX
000080H
OCCP7 (R/W)
XXXXXXXX XXXXXXXX
OCCP6 (R/W)
XXXXXXXX XXXXXXXX
000084H
OCS2, 3 (R/W)
XXX00000 0000XX00
OCS0, 1 (R/W)
XXX00000 0000XX00
000088H
OCS6, 7 (R/W)
XXX00000 0000XX00
OCS4, 5 (R/W)
XXX00000 0000XX00
00008CH
TCDT (R/W)
00000000 00000000
TCCS (R/W)
0 - - - - - - - 00000000
000094H
STPR0 (R/W)
0000 - - - -
STPR1 (R/W)
00000 - 00
GCN1 (R/W)
00110010 00010000
Communications
prescaler 1
8/16 bit U/D Counter
16 bit ICU
ICS01 (R/W)
00000000
000074H
000090H
Reload Timer 3
Reserved
00005CH
000070H
Block
16 bit OCU
16 bit Freerun Timer
STPR2 (R/W)
000000 - -
Stop Register 0, 1, 2
GCN2 (R/W)
00000000
PPG ctl
(Continued)
25
MB91151A
Address
Register
+0
+1
000098H
PTMR0 (R)
11111111 11111111
00009CH
PDUT0 (W)
XXXXXXXX XXXXXXXX
0000A0H
PTMR1 (R)
11111111 11111111
0000A4H
PDUT1 (W)
XXXXXXXX XXXXXXXX
0000A8H
PTMR2 (R)
11111111 11111111
0000ACH
PDUT2 (W)
XXXXXXXX XXXXXXXX
0000B0H
PTMR3 (R)
11111111 11111111
0000B4H
PDUT3 (W)
XXXXXXXX XXXXXXXX
0000B8H
PTMR4 (R)
11111111 11111111
0000BCH
PDUT4 (W)
XXXXXXXX XXXXXXXX
0000C0H
PTMR5 (R)
11111111 11111111
0000C4H
PDUT5 (W)
XXXXXXXX XXXXXXXX
0000C8H
0000CCH
EIRR0 (R/W)
00000000
0000E0H
0000E4H
0000E8H
0000ECH
to
0000F0H
+3
PCSR0 (W)
XXXXXXXX XXXXXXXX
PCNH0 (R/W)
0000000 -
PCNL0 (R/W)
00000000
PCSR1 (W)
XXXXXXXX XXXXXXXX
PCNH1 (R/W)
0000000 -
PCNL1 (R/W)
00000000
PCSR2 (W)
XXXXXXXX XXXXXXXX
PCNH2 (R/W)
0000000 -
PCNL2 (R/W)
00000000
PCSR3 (W)
XXXXXXXX XXXXXXXX
PCNH3 (R/W)
0000000 -
PCNL3 (R/W)
00000000
PCSR4 (W)
XXXXXXXX XXXXXXXX
PCNH4 (R/W)
0000000 -
PCNL4 (R/W)
00000000
PCSR5 (W)
XXXXXXXX XXXXXXXX
ENIR0 (R/W)
00000000
ELVR0 (R/W)
00000000 00000000
0000D0H
to
0000D8H
0000DCH
+2
PCNH5 (R/W)
0000000 -
PCNL5 (R/W)
00000000
EIRR1 (R/W)
00000000
ENIR1 (R/W)
00000000
ELVR1 (R/W)
00000000 00000000
Block
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
Ext int
Reserved
DACR2 (R/W)
-------0
DACR1 (R/W)
-------0
DACR0 (R/W)
-------0
DADR2 (R/W)
XXXXXXXX
DADR1 (R/W)
XXXXXXXX
DADR0 (R/W)
XXXXXXXX
ADCS1 (R/W, W)
00000000
ADCS0 (R/W)
00000000
A/D Converter
(Sequential type)
AICK (R/W)
00000000
Analog Input Control
ADCR (R, W)
00101- XX XXXXXXXX
D/A Converter
Reserved
(Continued)
26
MB91151A
Address
Register
+0
+1
+2
+3
0000F4H
PCRI (R/W)
- - 000000
PCRH (R/W)
- - 000000
PCRD (R/W)
00000000
PCRC (R/W)
00000000
0000F8H
OCRI (R/W)
- - 000000
OCRH (R/W)
- - 000000
0000FCH
DDRF (R/W)
- - - 00000
DDRE (R/W)
00000000
DDRD (R/W)
00000000
DDRC (R/W)
00000000
000100H
DDRI (R/W)
- 0000000
DDRH (R/W)
- - 000000
DDRG (R/W)
- - 000000
DDRL (R/W)
00000000
DDRK (R/W)
00000000
000104H
Block
Pull Up Control
Open drain Control
Data Direction Register
000108H
to
0001FCH
000200H
DPDP (R/W)
- - - - - - - - - - - - - - - - - - - - - - - - - 0000000
000204H
DACSR (R/W)
00000000 00000000 00000000 00000000
000208H
DATCR (R/W)
XXXXXXXX XXXX0000 XXXX0000 XXXX0000
00020CH
to
0003E0H
Reserved
0003E4H
ICHCR (R/W)
- - - - - - - - - - - - - - - - - - - - - - - - - - 000000
Instruction cache
0003E8H
to
0003ECH
Reserved
0003F0H
BSD0 (W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003E4H
BSD1 (R/W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC (W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR (R)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
DMAC
Bit Search Module
(Continued)
27
MB91151A
Address
Register
+0
+1
+2
+3
000400H
ICR00 (R/W)
- - - - 1111
ICR01 (R/W)
- - - - 1111
ICR02 (R/W)
- - - - 1111
ICR03 (R/W)
- - - - 1111
000404H
ICR04 (R/W)
- - - - 1111
ICR05 (R/W)
- - - - 1111
ICR06 (R/W)
- - - - 1111
ICR07 (R/W)
- - - - 1111
000408H
ICR08 (R/W)
- - - - 1111
ICR09 (R/W)
- - - - 1111
ICR10 (R/W)
- - - - 1111
ICR11 (R/W)
- - - - 1111
00040CH
ICR12 (R/W)
- - - - 1111
ICR13 (R/W)
- - - - 1111
ICR14 (R/W)
- - - - 1111
ICR15 (R/W)
- - - - 1111
000410H
ICR16 (R/W)
- - - - 1111
ICR17 (R/W)
- - - - 1111
ICR18 (R/W)
- - - - 1111
ICR19 (R/W)
- - - - 1111
000414H
ICR20 (R/W)
- - - - 1111
ICR21 (R/W)
- - - - 1111
ICR22 (R/W)
- - - - 1111
ICR23 (R/W)
- - - - 1111
000418H
ICR24 (R/W)
- - - - 1111
ICR25 (R/W)
- - - - 1111
ICR26 (R/W)
- - - - 1111
ICR27 (R/W)
- - - - 1111
00041CH
ICR28 (R/W)
- - - - 1111
ICR29 (R/W)
- - - - 1111
ICR30 (R/W)
- - - - 1111
ICR31 (R/W)
- - - - 1111
000420H
ICR32 (R/W)
- - - - 1111
ICR33 (R/W)
- - - - 1111
ICR34 (R/W)
- - - - 1111
ICR35 (R/W)
- - - - 1111
000424H
ICR36 (R/W)
- - - - 1111
ICR37 (R/W)
- - - - 1111
ICR38 (R/W)
- - - - 1111
ICR39 (R/W)
- - - - 1111
000428H
ICR40 (R/W)
- - - - 1111
ICR41 (R/W)
- - - - 1111
ICR42 (R/W)
- - - - 1111
ICR43 (R/W)
- - - - 1111
00042CH
ICR44 (R/W)
- - - - 1111
ICR45 (R/W)
- - - - 1111
ICR46 (R/W)
- - - - 1111
ICR47 (R/W)
- - - - 1111
000430H
DICR (R/W)
-------0
HRCL (R/W)
- - - - 1111
000434H
to
00047CH
RSRR/WTCR
(R, W)
1-XXX-00
STCR (R/W, W)
000111- -
000484H
GCR (R/W, R)
110011-1
WPR (W)
XXXXXXXX
000488H
PTCR (R/W)
00XX0XXX
Interrupt Control unit
Delay int
000480H
00048CH
to
0005FCH
Block
Reserved
PDRR (R/W)
- - - - 0000
CTBR (W)
XXXXXXXX
Clock Control unit
PLL Control
Reserved
(Continued)
28
MB91151A
(Continued)
Address
Register
+0
+1
+2
+3
000600H
DDR3 (W)
00000000
DDR2 (W)
00000000
000604H
DDR6 (W)
00000000
DDR5 (W)
00000000
DDR4 (W)
00000000
00060CH
ASR1 (W)
00000000 00000001
AMR1 (W)
00000000 00000000
000610H
ASR2 (W)
00000000 00000010
AMR2 (W)
00000000 00000000
000614H
ASR3 (W)
00000000 00000011
AMR3 (W)
00000000 00000000
000618H
ASR4 (W)
00000000 00000100
AMR4 (W)
00000000 00000000
00061CH
ASR5 (W)
00000000 00000101
AMR5 (W)
00000000 00000000
AMD0 (R/W)
- - - 00111
000624H
AMD5 (R/W)
0 - - 00000
000628H
AMD1 (R/W)
0 - - 00000
AMD32 (R/W)
00000000
EPCR0 (W)
- - - - 1100 -1111111
AMD4 (R/W)
0 - - 00000
EPCR1 (W)
- - - - - - - - 11111111
Reserved
PCR6 (R/W)
00000000
000634H
to
0007F8H
0007FCH
T-unit
00062CH
000630H
Data Direction
Register
DDR8 (W)
- 0000000
000608H
000620H
Block
Pull Up Control
Reserved
LER (W)
- - - - - 000
MODR (W)
XXXXXXXX
Little Endian
Register
Mode Register
Note : Do not execute RMW instructions on registers having a write-only bit.
RMW instructions (RMW : Read Modify Write)
AND
Rj, @Ri
OR
Rj, @Ri
EOR
Rj, @Ri
ANDH Rj, @Ri
ORH Rj, @Ri
EORH Rj, @Ri
ANDB Rj, @Ri
ORB Rj, @Ri
EORB Rj, @Ri
BANDL #u4, @Ri
BORL #u4, @Ri
BEORL #u4, @Ri
BANDH #u4, @Ri
BORH #u4, @Ri
BEORH #u4, @Ri
Data is undefined in “Reserved” or () areas.
() :
R/W :
R:
Access
Read/Write enabled
Read only
W:
:
X:
Write only
Not in use
Undefined
29
MB91151A
■ INTERRUPT FACTORS AND ASSIGNMENT OF INTERRUPT VECTORS AND RESISTERS
Interrupt No.
Decimal
Hex.
Interrupt
level
Offset
Default TBR
address
Reset
0
00
3FCH
000FFFFCH
Reserved for the system
1
01
3F8H
000FFFF8H
Reserved for the system
2
02
3F4H
000FFFF4H
Reserved for the system
3
03
3F0H
000FFFF0H
Reserved for the system
4
04
3ECH
000FFFECH
Reserved for the system
5
05
3E8H
000FFFE8H
Reserved for the system
6
06
3E4H
000FFFE4H
Reserved for the system
7
07
3E0H
000FFFE0H
Reserved for the system
8
08
3DCH
000FFFDCH
Reserved for the system
9
09
3D8H
000FFFD8H
Reserved for the system
10
0A
3D4H
000FFFD4H
Reserved for the system
11
0B
3D0H
000FFFD0H
Reserved for the system
12
0C
3CCH
000FFFCCH
Reserved for the system
13
0D
3C8H
000FFFC8H
Undefined instruction exception
14
0E
3C4H
000FFFC4H
Reserved for the system
15
0F
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
External interrupts 8 to 15
24
18
ICR08
39CH
000FFF9CH
Reserved for the system
25
19
398H
000FFF98H
UART0 (receiving complete)
26
1A
ICR10
394H
000FFF94H
UART1 (receiving complete)
27
1B
ICR11
390H
000FFF90H
UART2 (receiving complete)
28
1C
ICR12
38CH
000FFF8CH
UART3 (receiving complete)
29
1D
ICR13
388H
000FFF88H
Reserved for the system
30
1E
384H
000FFF84H
UART0 (sending complete)
31
1F
ICR15
380H
000FFF80H
UART1 (sending complete)
32
20
ICR16
37CH
000FFF7CH
UART2 (sending complete)
33
21
ICR17
378H
000FFF78H
Factor
(Continued)
30
MB91151A
Interrupt No.
Decimal
Hex.
Interrupt
level
Offset
Default TBR
address
UART3 (sending complete)
34
22
ICR18
374H
000FFF74H
System reservation
35
23
370H
000FFF70H
DMAC (End, Error)
36
24
ICR20
36CH
000FFF6CH
Reload timer 0
37
25
ICR21
368H
000FFF68H
Reload timer 1
38
26
ICR22
364H
000FFF64H
Reload timer 2
39
27
ICR23
360H
000FFF60H
Reload timer 3
40
28
ICR24
35CH
000FFF5CH
A/D (sequential type)
42
2A
ICR26
354H
000FFF54H
PPG0
43
2B
ICR27
350H
000FFF50H
PPG1
44
2C
ICR28
34CH
000FFF4CH
PPG2
45
2D
ICR29
348H
000FFF48H
PPG3
46
2E
ICR30
344H
000FFF44H
PPG4
47
2F
ICR31
340H
000FFF40H
PPG5
48
30
ICR32
33CH
000FFF3CH
U/Dcounter 0
(compare/underflow, overflow, up-down
inversion)
49
31
ICR33
338H
000FFF38H
U/Dcounter 1
(compare/underflow, overflow, up-down
inversion
50
32
ICR34
334H
000FFF34H
ICU0 (Read)
51
33
ICR35
330H
000FFF30H
ICU1 (Read)
52
34
ICR36
32CH
000FFF2CH
ICU2 (Read)
53
35
ICR37
328H
000FFF28H
ICU3 (Read)
54
36
ICR38
324H
000FFF24H
OCU0 (Match)
55
37
ICR39
320H
000FFF20H
OCU1 (Match)
56
38
ICR40
31CH
000FFF1CH
OCU2 (Match)
57
39
ICR41
318H
000FFF18H
OCU3 (Match)
58
3A
ICR42
314H
000FFF14H
OCU4/5 (Match)
59
3B
ICR43
310H
000FFF10H
OCU6/7 (Match)
60
3C
ICR44
30CH
000FFF0CH
Reserved for the system
61
3D
308H
000FFF08H
16-bit free-run timer
62
3E
ICR46
304H
000FFF04H
Delay interrupt factor bit
63
3F
ICR47
300H
000FFF00H
Factor
(Continued)
31
MB91151A
(Continued)
Interrupt No.
Decimal
Hex.
Interrupt
level
Offset
Default TBR
address
Reserved for the system
(used by REALOS*)
64
40
2FCH
000FFEFCH
Reserved for the system
(used by REALOS*)
65
41
2F8H
000FFEF8H
Reserved for the system
66
42
2F4H
000FFEF4H
Reserved for the system
67
43
2F0H
000FFEF0H
Reserved for the system
68
44
2ECH
000FFEECH
Reserved for the system
69
45
2E8H
000FFEE8H
Reserved for the system
70
46
2E4H
000FFEE4H
Reserved for the system
71
47
2E0H
000FFEE0H
Reserved for the system
72
48
2DCH
000FFEDCH
Reserved for the system
73
49
2D8H
000FFED8H
Reserved for the system
74
4A
2D4H
000FFED4H
Reserved for the system
75
4B
2D0H
000FFED0H
Reserved for the system
76
4C
2CCH
000FFECCH
Reserved for the system
77
4D
2C8H
000FFEC8H
Reserved for the system
78
4E
2C4H
000FFEC4H
Reserved for the system
79
4F
2C0H
000FFEC0H
Used with the INT instruction
80
to
255
50
to
FF
2BCH
to
000H
000FFEBCH
to
000FFC00H
Factor
* : REALOS/FR uses 0X40 and 0X41 interrupts for system codes.
32
MB91151A
■ PERIPHERAL RESOURCES
1. I/O Port
(1) Port Block Diagram
This LSI is available as an I/O port when the resource associated with each pin is set not to use a pin for input/
output.
The pin level is read from the port (PDR) when it is set for input. When the port is set for output, the value in the
data register is read. The same also applies to reload by read modify write.
When switching from input to output, output data is set in the data register beforehand. However, if a read modify
write instruction (such as bit set) is used at that time, keep in mind that it is the input data from the pin that is
read, not the latch value of the data register.
• Basic I/O Port
Data bus
Resource input
0
1
PDR read
pin
0
PDR
Resource output
1
Resource output
allowed
DDR
PDR : Port Data Register
DDR : Data Direction Register
The I/O port consists of the PDR (Port Data Register) and the DDR (Data Direction Register) .
In input mode (DDR = “0”) → PDR read : Reads the level of the corresponding external pin.
PDR write : Writes the set value to the PDR.
In output mode (DDR = “1”) → PDR read : Reads the PDR value.
PDR write : Outputs the PDR value to the corresponding external pin.
Notes : AIC controls switching between the resource and port of the analog pin (A/D) .
AICK (Analog Input Control register on port-K)
The register controls whether port K should be used for analog input or as a general-purpose port.
0 : General-purpose port
1 : Analog input (A/D)
33
MB91151A
• I/O Port (attached with a pull-up resistor)
Data bus
Resource input
0
1
Pull-up resistor (approx. 50 kΩ)
PDR read
pin
0
PDR
Resource output
1
Resource output
allowed
DDR
PCR
PDR : Port Data Register
DDR : Data Direction Register
PCR : Pull-up Control Register
Notes : • Pull-up resistor control register (PCR) R/W
Controls turning the pull-up resistor on/off.
0 : Pull-up resistor disabled
1 : Pull-up resistor enabled
• In stop mode priority is also given to the setting of the pull-up resistor control register.
• This function is not available when a relevant pin is in use as an external bus pin. Do not write “1” to this
register.
34
MB91151A
• I/O Port (attached with the open drain output function and a pull-up resistor)
Data bus
Resource input
0
1
PDR read
pin
0
PDR
Resource output
DDR
1
Resource output
allowed
OCR
PCR
PDR
DDR
OCR
PCR
: Port Data Register
: Data Direction Register
: OpenDrain Control Register
: Pull-up Control Register
Notes : • Pull-up resistor setup register (PCR) R/W
Controls turning the pull-up resistor on/off.
0 : Pull-up resistor disabled
1 : Pull-up resistor enabled
• Open drain control register (OCR) R/W
Controls open drain in output mode.
0 : Standard output port during output mode
1 : Open-drain output port during output mode
This register has no significance in input mode (output High-Z) . Input/output mode is determined by
the direction register (DDR) .
• Priority is also given to the setting of the pull-up resistor control register in stop mode.
• When a relevant pin is used as an external bus pin, neither function is available. Do not write “1” to either
register.
35
MB91151A
• I/O Port (open drain)
Data bus
RMW
Resource output
Resource input
RMW = 0
RMW = 1
pin
PDR read
PDR
PDR : Port Data Register
Notes : • When using as an input port or for resource input, set the PDR and resource output to “1.”
• During read by RMW, it is the PDR value that is read, not the pin value.
36
MB91151A
(2) Register Descriptions
• Port Data Register (PDR)
PDR2
7
6
5
4
3
2
1
0
P24
P23
P22
P21
P20
Address : 000001H
P27
P26
P25
PDR3
7
6
5
4
3
2
1
0
Address : 000000H
P37
P36
P35
P34
P33
P32
P31
P30
PDR4
7
6
5
4
3
2
1
0
Address : 000007H
P47
P46
P45
P44
P43
P42
P41
P40
PDR5
7
6
5
4
3
2
1
0
Address : 000006H
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
7
6
5
4
3
2
1
0
Address : 000005H
P67
P66
P65
P64
P63
P62
P61
P60
PDR8
7
6
5
4
3
2
1
0
Address : 00000BH
P86
P85
P84
P83
P82
P81
P80
PDRC
7
6
5
4
3
2
1
0
Address : 000013H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PDRD
7
6
5
4
3
2
1
0
Address : 000012H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDRE
7
6
5
4
3
2
1
0
Address : 000011H
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PDRF
7
6
5
4
3
2
1
0
Address : 000010H
PF4
PF3
PF2
PF1
PF0
PDRG
7
6
5
4
3
2
1
0
Address : 000017H
PG5
PG4
PG3
PG2
PG1
PG0
PDRH
7
6
5
4
3
2
1
0
Address : 000016H
PH5
PH4
PH3
PH2
PH1
PH0
PDRI
7
6
5
4
3
2
1
0
Address : 000015H
PI5
PI4
PI3
PI2
PI1
PI0
PDRJ
7
6
5
4
3
2
1
0
Address : 000014H
PJ1
PJ0
PDRK
7
6
5
4
3
2
1
0
Address : 00001BH
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
PDRL
7
6
5
4
3
2
1
0
Address : 00001AH
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
- XXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
- - - XXXXXB
R/W
Initial value Access
- - XXXXXXB
R/W
Initial value Access
- - XXXXXXB
R/W
Initial value Access
- - XXXXXXB
R/W
Initial value Access
- - - - - - 11B
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
PDR2 to PDRL are the I/O data registers of the I/O port.
Input/output is controlled with corresponding DDR2 to DDRL.
R/W : Read/Write enabled, X : Undefined, : Not in use
37
MB91151A
• Data Direction Register (DDR)
DDR2
7
6
5
4
3
2
1
0
Address : 000601H
P27
P26
P25
P24
P23
P22
P21
P20
DDR3
7
6
5
4
3
2
1
0
Address : 000600H
P37
P36
P35
P34
P33
P32
P31
P30
DDR4
7
6
5
4
3
2
1
0
Address : 000607H
P47
P46
P45
P44
P43
P42
P41
P40
DDR5
7
6
5
4
3
2
1
0
Address : 000606H
P57
P56
P55
P54
P53
P52
P51
P50
DDR6
7
6
5
4
3
2
1
0
Address : 000605H
P67
P66
P65
P64
P63
P62
P61
P60
DDR8
7
6
5
4
3
2
1
0
Address : 00060BH
P86
P85
P84
P83
P82
P81
P80
DDRC
7
6
5
4
3
2
1
0
Address : 0000FFH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DDRD
7
6
5
4
3
2
1
0
Address : 0000FEH
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DDRE
7
6
5
4
3
2
1
0
Address : 0000FDH
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
DDRF
7
6
5
4
3
2
1
0
Address : 0000FCH
PF4
PF3
PF2
PF1
PF0
DDRG
7
6
5
4
3
2
1
0
Address : 000103H
PG5
PG4
PG3
PG2
PG1
PG0
DDRH
7
6
5
4
3
2
1
0
Address : 000102H
PH5
PH4
PH3
PH2
PH1
PH0
DDRI
7
6
5
4
3
2
1
0
Address : 000101H
TEST
PI5
PI4
PI3
PI2
PI1
PI0
DDRK
7
6
5
4
3
2
1
0
Address : 000107H
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
DDRL
7
6
5
4
3
2
1
0
Address : 000106H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
DDR2 to DDRL control the I/O direction of the I/O port by bit.
DDR = 0 : Port input
DDR = 1 : Port output
Note : DDRI’s bit 6 is a test bit. Be sure to write “0” to the bit.
“0” is the value that is read.
R/W : Read/Write enabled, W : Write only, : Not in use
38
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
- 0000000B
W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
- - - 00000B
R/W
Initial value Access
- - 000000B
R/W
Initial value Access
- - 000000B
R/W
Initial value Access
- 0000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
MB91151A
• Pull-up Control Register (PCR)
PCR6
7
6
5
4
3
2
1
0
Address : 000631H
P67
P66
P65
P64
P63
P62
P61
P60
PCRC
7
6
5
4
3
2
1
0
Address : 0000F7H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCRD
7
6
5
4
3
2
1
0
Address : 0000F6H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
7
6
5
4
3
2
1
0
PH5
PH4
PH3
PH2
PH1
PH0
7
6
5
4
3
2
1
0
PI5
PI4
PI3
PI2
PI1
PI0
PCRH
Address : 0000F5H
PCRI
Address : 0000F4H
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
- - 000000B
R/W
Initial value Access
- - 000000B
R/W
PCR6 to PCRI control the pull-up resistor when the corresponding I/O port is in input mode.
PCR = 0 : Pull-up resistor not available in input mode
PCR = 1 : Pull-up resistor available in input mode
The register has no significance in output mode (a pull-up resistor not available) .
• Open Drain Control Register (OCR)
OCRH
7
6
5
Address : 0000F9H
OCRI
Address : 0000F8H
4
3
2
1
0
PH5
PH4
PH3
PH2
PH1
PH0
7
6
5
4
3
2
1
0
PI5
PI4
PI3
PI2
PI1
PI0
Initial value Access
- - 000000B
R/W
Initial value Access
- - 000000B
R/W
OCRH and OCRI control open drain when the corresponding I/O port is in output mode.
OCR = 0 : Standard output port during output mode
OCR = 1 : Open drain output port during output mode
The register has no significance in input mode (output High-Z) .
• Analog Input Control Register (AICR)
AICK
7
6
5
Address : 0000EBH
PK7
PK6
PK5
4
3
2
1
0
PK4
PK3
PK2
PK1
PK0
Initial value Access
00000000B
R/W
The AICK controls each pin of a corresponding I/O port as follows :
AIC = 0 : Port input mode
AIC = 1 : Analog input mode
The register is reset to “0.”
R/W : Read/Write enabled, : Not in use
39
MB91151A
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.
DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system.
• 8 channels
• Mode : single/block transfer, burst transfer and continuous transfer : 3 kinds of transfer
• Transfer all through the area
• Max 65536 of transfer cycles
• Interrupt function right after the transfer
• Selectable for address transfer increase/decrease by the software
• External transfer request input pin, external transfer request accept output pin, external transfer complete
output pin three pins for each
• Block Diagram
DREQ0 to DREQ2
3
Edge/level
detection circuit
3
3
Sequencer
Internal resource
transfer request
DACK0 to DACK2
3
DEOP0 to DEOP2
8
Interrupt request
5
Data buffer
Switcher
DACSR
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
40
Data bus
DPDP
MB91151A
• Registers (DMAC internal registers)
Address
00000200H
00000201H
00000202H
00000203H
bit 31
bit 16
bit 0
DPDP
00000204H
00000205H
00000206H
00000207H
00000208H
00000209H
0000020AH
0000020BH
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
X0000000B
Access
R/W
DACSR
00000000B
00000000B
00000000B
00000000B
R/W
DATCR
XXXXXXXXB
XXXX0000 B
XXXX0000 B
XXXX0000 B
R/W
R/W : Read/Write enabled
X : Undefined
• Register (DMA descriptor)
Address
DPDP + 0H
DPDP + 0CH
DPDP + 54H
bit 31
bit 0
DMA
ch0
Descriptor
DMA
ch1
Descriptor
DMA
ch7
Descriptor
41
MB91151A
3. UART
The UART is a serial I/O port for asynchronous (start and stop synchronization) communication or CLK synchronous communication. This product type contains this UART for four channels. Its features are as follows :
• Full-duplex double buffer
• Capable of asynchronous (start and stop synchronization) and CLK synchronous communication.
• Support for multiprocessor mode
• Baud rate by a dedicated baud rate generator
• Baud rate by an internal timer
The baud rate can be set with a 16-bit reload timer.
• Any baud rate can be set using an external clock.
• Error detection function (parity, framing, and overrun)
• NRZ-encoded transfer signals
• DMA transfer can be invoked by interrupt.
42
MB91151A
• Block Diagram
Control bus
Receive
interrupt signal
#26 to 29 *
Dedicated baud rate
generator
16-bit reload timer
Receive clock
(SCK0 to SCK3)
Send
interrupt signal
#31 to 34 *
Send clock
Clock
selector
Pin
Receiving
control circuit
Sending
control circuit
Start bit
detection circuit
Sending start
circuit
Receive bit
counter
Send bit
counter
Receive parity
counter
Send parity
counter
Receive
shift register
Send
shift register
SIDR0 to SIDR3
SODR0 to SODR3
(SOT0 to SOT3)
Pin
(SIN0 to SIN3)
Pin
Received status
determination circuit
Sending start
Reception error
generated signals
(to the CPU)
Internal data bus
SMR 0 - 3
registers
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR 0 - 3
registers
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR 0 - 3
registers
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
* : Interrupt numbers
43
MB91151A
• Register List
Address
bit 8
bit 0
Initial value
Access
0000001EH
SCR0
00000100B
R/W, W
00000022H
SCR1
00000100B
R/W, W
00000026H
SCR2
00000100B
R/W, W
0000002AH
SCR3
00000100B
R/W, W
0000001FH
SMR0
00000-00B
R/W
00000023H
SMR1
00000-00B
R/W
00000027H
SMR2
00000-00B
R/W
0000002BH
SMR3
00000-00B
R/W
0000001CH
SSR0
00001000B
R, R/W
00000020H
SSR1
00001000B
R, R/W
00000024H
SSR2
00001000B
R, R/W
00000028H
SSR3
00001000B
R, R/W
0000001DH
SIDR0/SODR0
XXXXXXXXB
R, W
00000021H
SIDR1/SIDR1
XXXXXXXXB
R, W
00000025H
SIDR2/SIDR2
XXXXXXXXB
R, W
00000029H
SIDR3/SIDR3
XXXXXXXXB
R, W
R/W
R
W
X
44
bit 15
: Read/Write enabled
: Read only
: Write only
: Not in use
: Undefined
MB91151A
4. PPG Timer
The PPG timer can output highly accurate PWM waveforms efficiently.
The MB91151A contains six PPG timer channels and its features are as follows :
• Each channel consists of a 16-bit down counter, a 16-bit data register attached with a frequency setting buffer,
a 16-bit compare register attached with a duty setting buffer, and a pin controller.
• The count clock for the 16-bit down counter can be selected from the following four types :
Internal clocks φ, φ/4, φ/16, and φ/64
• The counter value can be initialized by reset or counter borrow to “FFFFH.”
• PWM output (by channel)
• DMA transfer can be invoked by interrupt.
• Block Diagram (Entire configuration)
16-bit reload timer
channel 0
TRG input
PWM timer channel 0
PWM0
16-bit reload timer
channel 1
TRG input
PWM timer channel 1
PWM1
4
TRG input
PWM timer channel 2
PWM2
4
TRG input
PWM timer channel 3
PWM3
External TRG4
TRG input
PWM timer channel 4
PWM4
External TRG5
TRG input
PWM timer channel 5
PWM5
General control
register 1
(Factor selection)
General control
register 2
External TRG0 to TRG3
45
MB91151A
• Block Diagram (for one channel)
PDUT
PCSR
Prescaler
1/1
1/4
1 / 16
1 / 64
cmp
Load
ck
16-bit down counter
Start
Borrow
PPG mask
S
Peripheral system clock
Q
PWM output
R
Inverse bit
Enable
TRG input
Edge
detection
Soft trigger
46
Interrupt
selection
IRQ
MB91151A
• Register List
Address
00000094H
00000095H
bit 15
bit 8
bit 0
GCN1
00000097H
GCN2
Initial value
00110010B
00010000B
Accress
00000000B
R/W
R/W
00000098H
00000099H
PTMR0
11111111B
11111111B
R
0000009AH
0000009BH
PCSR0
XXXXXXXXB
XXXXXXXXB
W
0000009CH
0000009DH
PDUT0
XXXXXXXXB
XXXXXXXXB
W
0000000-B
R/W
00000000B
R/W
0000009EH
PCNH0
0000009FH
PCNL0
000000A0H
000000A1H
PTMR1
11111111B
11111111B
R
000000A2H
000000A3H
PCSR1
XXXXXXXXB
XXXXXXXXB
W
000000A4H
000000A5H
PDUT1
XXXXXXXXB
XXXXXXXXB
W
0000000-B
R/W
00000000B
R/W
000000A6H
PCNH1
000000A7H
PCNL1
000000A8H
000000A9H
PTMR2
11111111B
11111111B
R
000000AAH
000000ABH
PCSR2
XXXXXXXXB
XXXXXXXXB
W
000000ACH
000000ADH
PDUT2
XXXXXXXXB
XXXXXXXXB
W
0000000-B
R/W
00000000B
R/W
000000AEH
PCNH2
000000AFH
PCNL2
000000B0H
000000B1H
PTMR3
11111111B
11111111B
R
000000B2H
000000B3H
PCSR3
XXXXXXXXB
XXXXXXXXB
W
000000B4H
000000B5H
PDUT3
XXXXXXXXB
XXXXXXXXB
W
0000000-B
R/W
00000000B
R/W
000000B6H
000000B7H
PCNH3
PCNL3
R/W : Read/Write enabled R : Read only W : Write only : Not in use
X : Undefined
(Continued)
47
MB91151A
(Continued)
Address
Initial value
Access
PTMR4
11111111B
11111111B
R
000000BAH
000000BBH
PCSR4
XXXXXXXXB
XXXXXXXXB
W
000000BCH
000000BDH
PDUT4
XXXXXXXXB
XXXXXXXXB
W
0000000-B
R/W
00000000B
R/W
000000B8H
000000B9H
000000BEH
bit 15
bit 8
PCNH4
000000BFH
PCNL4
000000C0H
000000C1H
PTMR5
11111111B
11111111B
R
000000C2H
000000C3H
PCSR5
XXXXXXXXB
XXXXXXXXB
W
000000C4H
000000C5H
PDUT5
XXXXXXXXB
XXXXXXXXB
W
0000000-B
R/W
00000000B
R/W
000000C6H
PCNH5
000000C7H
R/W : Read/Write enabled
W : Write only
X : Undefined
48
bit 0
PCNL5
R : Read only
: Not in use
MB91151A
5. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating internal
count clocks, and a control register.
The input clock can be selected from three internal clock types (2/8/32 machine clock divisions) .
DMA transfer can be invoked by interrupt.
This product type contains this 16-bit reload timer for four channels.
• Block Diagram
16
16-bit reload register
8
Reload
RELD
16
16-bit down counter
OUTE
UF
OUTL
2
OUT
CTL.
GATE
INTE
R bus
2
IRQ
UF
CSL1
Clock selector
CNTE
CSL0
2
Retrigger
TRG
IN CTL.
EXCK
φ
φ
φ
21 23 25
Clear
prescaler
3
PWM (ch0, ch1)
A/D (ch2)
MOD2
MOD1
Internal clocks
MOD0
3
49
MB91151A
• Register List
Address
Initial value
Access
TMCSR0
----0000B
00000000B
R/W
0000003AH
0000003BH
TMCSR1
----0000B
00000000B
R/W
00000042H
00000043H
TMCSR2
----0000B
00000000B
R/W
0000004AH
0000004BH
TMCSR3
----0000B
00000000B
R/W
0000002EH
0000002FH
TMR0
XXXXXXXXB
XXXXXXXXB
R
00000036H
00000037H
TMR1
XXXXXXXXB
XXXXXXXXB
R
0000003EH
0000003FH
TMR2
XXXXXXXXB
XXXXXXXXB
R
00000046H
00000047H
TMR3
XXXXXXXXB
XXXXXXXXB
R
0000002CH
0000002DH
TMRLR0
XXXXXXXXB
XXXXXXXXB
W
00000034H
00000035H
TMRLR1
XXXXXXXXB
XXXXXXXXB
W
0000003CH
0000003DH
TMRLR2
XXXXXXXXB
XXXXXXXXB
W
00000044H
00000045H
TMRLR3
XXXXXXXXB
XXXXXXXXB
W
00000032H
00000033H
bit 15
R/W : Read/Write enabled
R : Read only
W : Write only
: Not in use
X : Undefined
50
bit 0
MB91151A
6. Bit Search Module
The module searches data written to the input register for “0” or “1” or a “change” and returns the detected bit
position.
• Block Diagram
Input latch
Detection
mode
D bus
Address
decoder
Changing one detection into data
Bit search circuit
Search results
• Register List
Address
000003F0H
000003F1H
000003F2H
000003F3H
bit 31
bit 16
BSD0
bit 0
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Access
W
000003F4H
000003F5H
000003F6H
000003F7H
BSD1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
000003F8H
000003F9H
000003FAH
000003FBH
BSDC
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
W
000003FCH
000003FDH
000003FEH
000003FFH
BSRR
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R
R/W : Read/Write enabled
W : Write only
R : Read only
X : Undefined
51
MB91151A
7. 8/10-bit A/D Converter (Sequential Conversion Type)
The A/D converter is a module that converts analog input voltage into a digital value. Its features are as follows :
• A minimum conversion time of 5.0 µs/ch. (Including sampling time at a 33 MHz machine clock)
• Contains a sample and hold circuit.
• Resolution : 10 or 8 bits selectable.
• Selection of analog input from eight channels by program
Single conversion mode :
Selects and converts one channel.
Continuous conversion mode : Converts a specified channel repeatedly.
Stop and convert mode :
Stops after converting one channel and stands by until invoked the next time.
(Conversion invoking can be synchronized.)
• DMA transfer can be invoked by interrupt.
• Selection of an invoking factor from software, external pin trigger (falling edge) , and 16-bit reload timer (rising
edge) .
• Block Diagram
AVSS AVR±
AVSS
MP
D/A converter
Sequential compare
register
Input
circuit
Comparator
R - Bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Decoder
Sample & hold circuit
Data register
ADCR
A/D control register 1
A/D control register 2
16-bit reload timer 2
External pin trigger
φ
52
ADCS1, 2
Operating clock
Prescaler
MB91151A
• Register List
Address
bit 15
bit 0
000000E4H
000000E5H
000000E6H
ADCR
ADCS1
Initial value
Access
00101-XXB
XXXXXXXXB
W, R
R
00000000B
R/W, W
000000E7H
ADCS0
00000000B
R/W
000000EBH
AICK
00000000B
R/W
R/W : Read/Write enabled
R : Read only
W : Write only
: Not in use
X : Undefined
53
MB91151A
8. Interrupt Controller
The interrupt controller accepts and arbitrates interrupts.
• Block Diagram
INT0*2
IM
Priority determination
OR
5
5
NMI*6
NMI processing
Level
determination
RI00
.
.
.
ICR00
.
.
.
Vector
determination
6
Request to
withdraw
HLDREQ
6
HLDCAN*3
VCT5
to VCT0*5
ICR47
RI47
(DLYIRQ)
.
.
Level vector
generation
4
LEVEL4
to LEVEL0*4
DLYI*1
R bus
*1 : DLY1 represents the delay interrupt module (delay interrupt generator) . For detailed information, see
“10. Delay Interrupt Module.”
*2 : INT0 is a wake-up signal for the clock controller in sleep or stop mode.
*3 : HLDCAN is a bus surrender request signal for bus masters except for the CPU.
*4 : LEVEL 4 to LEVEL 0 are interrupt level outputs.
*5 : VCT 5 to VCT 0 are interrupt vector outputs.
*6 : This product type does not have the NMI function.
54
MB91151A
• Register List
Address
bit 7
bit 0
Initial value Access
Address
bit 7
bit 0
Initial value Access
00000400H
ICR00
----1111B
R/W
00000414H
ICR20
----1111B
R/W
00000401H
ICR01
----1111B
R/W
00000415H
ICR21
----1111B
R/W
00000402H
ICR02
----1111B
R/W
00000416H
ICR22
----1111B
R/W
00000403H
ICR03
----1111B
R/W
00000417H
ICR23
----1111B
R/W
00000404H
ICR04
----1111B
R/W
00000418H
ICR24
----1111B
R/W
00000405H
ICR05
----1111B
R/W
00000419H
ICR25
----1111B
R/W
00000406H
ICR06
----1111B
R/W
0000041AH
ICR26
----1111B
R/W
00000407H
ICR07
----1111B
R/W
0000041BH
ICR27
----1111B
R/W
00000408H
ICR08
----1111B
R/W
0000041CH
ICR28
----1111B
R/W
00000409H
ICR09
----1111B
R/W
0000041DH
ICR29
----1111B
R/W
0000040AH
ICR10
----1111B
R/W
0000041EH
ICR30
----1111B
R/W
0000040BH
ICR11
----1111B
R/W
0000041FH
ICR31
----1111B
R/W
0000040CH
ICR12
----1111B
R/W
00000420H
ICR32
----1111B
R/W
0000040DH
ICR13
----1111B
R/W
00000421H
ICR33
----1111B
R/W
0000040EH
ICR14
----1111B
R/W
00000422H
ICR34
----1111B
R/W
0000040FH
ICR15
----1111B
R/W
00000423H
ICR35
----1111B
R/W
00000410H
ICR16
----1111B
R/W
00000424H
ICR36
----1111B
R/W
00000411H
ICR17
----1111B
R/W
00000425H
ICR37
----1111B
R/W
00000412H
ICR18
----1111B
R/W
00000426H
ICR38
----1111B
R/W
00000413H
ICR19
----1111B
R/W
00000427H
ICR39
----1111B
R/W
R/W : Read/Write enabled
: Not in use
(Continued)
55
MB91151A
(Continued)
Address
bit 7
bit 0
Access
00000428H
ICR40
----1111B
R/W
00000429H
ICR41
----1111B
R/W
0000042AH
ICR42
----1111B
R/W
0000042BH
ICR43
----1111B
R/W
0000042CH
ICR44
----1111B
R/W
0000042DH
ICR45
----1111B
R/W
0000042EH
ICR46
----1111B
R/W
0000042FH
ICR47
----1111B
R/W
00000431H
HRCL
----1111B
R/W
00000430H
DICR
-------0B
R/W
R/W : Read/Write enabled
: Not in use
56
Initial value
MB91151A
9. External Interrupt
The external interrupt controller controls external interrupt requests input to INT0 through INT15.
The level of requests to be detected can be selected from “H, ” “L, ” rising edge, and falling edge.
• Block Diagram
16
Interrupt permission register
16
R bus
Interrupt
request
Gate
16
32
Edge detection
circuit
Factor F/F
16
INT0 to INT15
Interrupt factor register
Request level setting register
• Register List
Address
bit 15
bit 8
bit 0
Initial value
Access
000000C8H
000000C9H
EIRR0
ENIR0
00000000B
00000000B
R/W
000000CAH
000000CBH
EIRR1
ENIR1
00000000B
00000000B
R/W
000000CCH
000000CDH
ELVR0
00000000B
00000000B
R/W
000000CEH
000000CFH
ELVR1
00000000B
00000000B
R/W
R/W : Read/Write enabled
10. Delay Interrupt Module
The delay interrupt is a module that generates task switching interrupts. The use of this module allows the
software to generate/cancel interrupt requests to the CPU.
For the block diagram of the delay interrupt module, see “8. Interrupt Controller.”
• Register List
Address
bit 7
00000430H
bit 0
DICR
Access
Initial value
-------0
B
R/W
R/W : Read/Write enabled
: Not in use
57
MB91151A
11. Clock Generator (Low power consumption mechanism)
The clock generator is responsible for the following functions :
• CPU clock generation (including the gear function)
• Peripheral clock generation (including the gear function)
• Reset generation and holding factors
• Standby function (including hardware standby)
• Contains PLL (multiplication circuit)
• Block Diagram
[Gear controller]
GCR register
CPU gear
Peripheral
gear
1/2
X0
X1
Oscillator
circuit
PLL
Internal clock
generating
circuit
M
P
X
CPU Clock
Internal bus clock
Internal
peripheral clock
[Stop/sleep controller]
Internal interrupt
Internal reset
STCR register
Stop state
Sleep state
CPU Hold request
DMA request
PDRR register
Power on
detection circuit
VCC
Status
transition
control
circuit
Reset
generating
F/F
[Reset factor circuit]
R
GND
RSRR register
RST pin
[Watchdog controller]
WPR register
Watchdog F/F
Count clock
CTBR register
Timebase timer
58
Internal reset
MB91151A
• Register List
Address
00000480H
bit 15
bit 8
RSRR/WTCR
00000481H
00000482H
STCR
PDRR
00000483H
00000484H
bit 0
CTBR
GCR
00000485H
WPR
Initial value
Access
1-XXX-00B
R, W
000111--B
R/W, W
----0000B
R/W
XXXXXXXXB
W
110011-1B
R/W, R
XXXXXXXXB
W
R/W : Read/Write enabled
R : Read only
W : Write only
: Not in use
X : Undefined
59
MB91151A
12. External Bus Interface
The external bus interface controls the interface between the external memory and the external I/O. Its features
are as follows :
• 24-bit (16 MB) address output
• An 8/16-bit bus width can be set by chip select area.
• Inserts an automatic and programmable memory wait (for seven cycles at maximum) .
• Unused addresses/data pins are available as I/O ports.
• Support for little endian mode
• When use of a clock doubler, bus speed is half of CPU.
• The use is not allowed when the external bus exceeds 25 MHz.
• Block Diagram
Data Bus
Address Bus
A-Out
Write
buffer
Switch
Read
buffer
Switch
M
U
X
External DATA Bus
Data Block
Address Block
+1 or +2
Address
buffer
External
Address Bus
Shifter
Inpage
4
ASR
AMR
Comparator
CS0 to CS3
3
RD
WR0, WR1
4
BRQ
BGRNT
RDY
CLK
External pin controller
Controls all blocks.
Registers
&
Control
60
MB91151A
• Register List
Address
0000060CH
0000060DH
bit 31
bit 16
bit 0
ASR1
0000060EH
0000060F H
00000610 H
00000611 H
AMR1
ASR2
00000612 H
00000613 H
00000614 H
00000615 H
AMR2
ASR3
00000616 H
00000617 H
00000618 H
00000619 H
AMR3
ASR4
0000061AH
0000061BH
0000061CH
0000061DH
AMR4
ASR5
0000061EH
0000061F H
00000620 H
AMR5
AMD0
00000621 H
AMD1
00000622 H
AMD32
00000623 H
00000624 H
00000628 H
00000629 H
AMD4
AMD5
EPCR0
0000062AH
0000062BH
000007FEH
000007FF H
EPCR1
LER
MODR
Initial value
00000000B
00000001B
Access
W
00000000B
00000000B
W
00000000B
00000010B
W
00000000B
00000000B
W
00000000B
00000011B
W
00000000B
00000000B
W
00000000B
00000100B
W
00000000B
00000000B
W
00000000B
00000101B
W
00000000B
00000000B
W
---00111B
R/W
0--00000B
R/W
00000000B
R/W
0--00000B
R/W
0--00000B
R/W
----1100B
-1111111B
W
--------B
11111111B
W
-----000B
W
XXXXXXXXB
W
R/W : Read/Write enabled
W : Write only
: Not in use
X : Undefined
61
MB91151A
13. Multifunction Timer
The multifunction timer unit consists of one 16-bit free-run timer, eight 16-bit output compare registers, four 16bit input capture registers, and six 16-bit PPG timer channels. By using this function waveforms can be output
based on the 16-bit free-run timer and the input pulse width and external clock cycle can also be measured.
• Timer Components
• 16-bit free-run timer ( × 1)
The 16-bit free-run timer consists of a 16-bit up counter, a control register, a 16-bit compare clear register,
and a prescaler. The output value of this counter is used as the basic time (base timer) for output compare
and input capture.
• Output compare ( × 8)
The output compare consists of eight 16-bit compare registers, a compare output latch, and a control register.
When the 16-bit free-run timer value agrees to the compare register value, the output level can be inverted
and an interrupt can also be generated.
• Input capture ( × 4)
The input capture consists of capture registers corresponding to four independent external input pins and a
control register. By detecting any edge of signals input from external input pins, the 16-bit free-run timer value
can be held in the capture register and an interrupt can be generated at the same time.
• 16-bit PPG timer ( × 6)
See “4. PPG Timer”.
62
MB91151A
• Block Diagram
φ
Interrupt
IVF
IVFE
STOP
MODE
SCLR
CLK2
CLK1
CLK0
Divider
Clock
16-bit free-run timer
16-bit compare clear register
(Channel 6's compare register)
Compare register 0/2/4/6
MS13 to 0
Compare circuit
R-Bus
Compare register 1/3/5/7
Interrupt
Compare circuit
ICLR
ICRE
T
Q
OC0/2/4/6
T
Q
OC1/3/5/7
CMOD
Select
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interrupt
Interrupt
Capture register 0/2
IN 0/2
Edge detection
EG11
Capture register 1/3
EG10
EG01
Edge detection
ICP0
ICP1
ICE0
EG00
IN 1/3
ICE1
Interrupt
Interrupt
63
MB91151A
• Register List
Address
000068H
000069H
bit15
bit8 bit7
bit0
IPCP1
Access
R
R
00006AH
00006BH
IPCP0
XXXXXXXXB
XXXXXXXXB
R
R
00006CH
00006DH
IPCP3
XXXXXXXXB
XXXXXXXXB
R
R
00006EH
00006FH
IPCP2
XXXXXXXXB
XXXXXXXXB
R
R
000071H
ICS23
000073H
ICS01
00000000B
R/W
00000000B
R/W
000074H
000075H
OCCP1
XXXXXXXXB
XXXXXXXXB
R/W
R/W
000076H
000077H
OCCP0
XXXXXXXXB
XXXXXXXXB
R/W
R/W
000078H
000079H
OCCP3
XXXXXXXXB
XXXXXXXXB
R/W
R/W
00007AH
00007BH
OCCP2
XXXXXXXXB
XXXXXXXXB
R/W
R/W
00007CH
00007DH
OCCP5
XXXXXXXXB
XXXXXXXXB
R/W
R/W
00007EH
00007FH
OCCP4
XXXXXXXXB
XXXXXXXXB
R/W
R/W
000080H
000081H
OCCP7
XXXXXXXXB
XXXXXXXXB
R/W
R/W
000082H
000083H
OCCP6
XXXXXXXXB
XXXXXXXXB
R/W
R/W
000084H
000085H
OCS3,2
XXX00000B
0000XX00B
R/W
R/W
000086H
000087H
OCS1,0
XXX00000B
0000XX00B
R/W
R/W
000088H
000089H
OCS7,6
XXX00000B
0000XX00B
R/W
R/W
00008AH
00008BH
OCS5,4
XXX00000B
0000XX00B
R/W
R/W
00008CH
00008DH
TCDT
00000000B
00000000B
R/W
R/W
00008EH
00008FH
TCCS
0-------B
00000000B
R/W
R/W
R/W : Read/Write enabled R : Read only : Not in use
64
Initial value
XXXXXXXXB
XXXXXXXXB
X : Undefined
MB91151A
14. 8-bit D/A Converter
This block is of an 8-bit resolution, R-2R D/A converter. The block contains three D/A converter channels and
each D/A control register can control output independently.
The D/A converter pin is a dedicated pin.
• Block Diagram
R − Bus
DA27 ∼ DA20
DA17 ∼ DA10
DAVC
DA07 ∼ DA00
DAVC
DAVC
DA27
DA17
DA07
DA20
DA10
DA00
DAE2
Standby control
DAE1
Standby control
DAE0
Standby control
D/A output channel 2
D/A output channel 1
D/A output channel 0
65
MB91151A
• Register List
bit
7
6
5
4
Address : 00000E3H
15
14
13
12
Address : 00000E2H
1
0
23
22
21
20
Address : 00000E1H
11
10
9
8
7
6
5
19
4
Address : 00000DFH
18
17
16
15
14
13
12
Address : 00000DEH
3
2
1
0
11
23
22
21
20
19
DACR2
R/W : Read/Write enabled, : Not in use, X : Undefined
Initial value
- - - - - - - 0B R/W
10
9
8
Initial value
- - - - - - - 0B R/W
DACR1
bit
Initial value
XXXXXXXXB R/W
DACR0
bit
Initial value
XXXXXXXXB R/W
DADR2
bit
Initial value Access
XXXXXXXXB R/W
DADR1
bit
66
2
DADR0
bit
Address : 00000DDH
3
18
17
16
Initial value
- - - - - - - 0B R/W
MB91151A
15. 8/16-bit Up/Down Counters/Timers
This is the up/down counter/timer block consisting of six event input pins, two 8-bit up/down counters, two 8-bit
reload/compare registers, and their control circuits.
The features of this module are as follows :
• Capable of counting in the (0) d- (255) d range by the 8-bit count register.
(In 16-bit × 1 operating mode, the register can count in the (0) d- (65535) d range.)
• Four count modes to choose from by the count clock.
• In timer mode the count clock can be selected from two internal clock types.
• In up/down count mode an external pin input signal detection edge can be selected.
• The phase-difference count mode is suitable for encoder counting, such as of motors. Rotation angles, rotating
speeds, and so on can be counted accurately and easily by inputting the output of phases A, B, and Z.
• Two types of function to choose from for the ZIN pin. (Enabled in all modes)
• Equipped with compare and reload functions which can be used individually or in combination. When combined,
these functions can count up/down at any width.
• The immediately preceding count direction can be identified by the count direction flag.
• Capable of individually controlling interrupt generation when comparison results match, at occurrence of reload
(underflow) or overflow, or when the count direction changes.
67
MB91151A
• Block Diagram
• 8/16-bit Up/Down Counter/Timer (channel 0)
Data bus
8 bit
CGE1
ZIN0
CGE0
RCR0
(Reload/compare register 0)
C/GS
RCUT
Reload control
UCRE
RLDE
Edge/level detection
UDCC
Counter clear
8 bit
UDCR0
(Up/down count register 0)
Carry
CES1
CES0
CMS1
CMS0
UDFF
CITE
Counter clock
AIN0
BIN0
Up/down count
clock selection
Prescaler
UDF1
UDF0
CDCF
CFIE
CSTR
Interrupt output
CLKS
68
UDIE
OVFF
CMPF
MB91151A
• 8/16-bit Up/Down Counter/Timer (channel 1)
Data bus
8 bit
CGE1
ZIN1
CGE0
RCR1
(Reload/compare register 1)
C/GS
RCUT
Reload control
UCRE
RLDE
Edge/level detection
Counter clear
UDCC
8 bit
UDCR1
(Up/down count register 1)
CMPF
UDFF
CMS1
CMS0
CES1
CES0
OVFF
M16E
CITE
UDIE
Carry
Counter clock
AIN1
BIN1
Up/down count
clock selection
Prescaler
UDF1
UDF0
CDCF
CFIE
CSTR
Interrupt output
CLKS
69
MB91151A
• Register List
bit
7
6
5
4
Address : 00005FH
2
1
0
15
14
13
12
Address : 00005EH
11
10
9
8
7
6
5
4
Address : 00005DH
3
2
1
0
bit
15
14
13
12
Address : 00005CH
11
10
9
8
bit
7
6
5
4
Address : 000063H
3
2
1
0
7
6
5
4
Address : 000067H
3
2
1
0
7
6
5
4
Address : 000061H
3
2
1
0
7
6
5
4
Address : 000065H
3
2
1
0
15
14
13
12
Address : 000060H
11
10
9
8
15
14
13
12
11
CCRH1
Initial value
Initial value
00000000B
CCRH0
bit
Initial value
-000X000B R/W, W
CCRL1
bit
Initial value
-000X000B R/W, W
CCRL0
bit
Initial value
00000000B R/W, R
CSR1
bit
10
9
8
R/W
Initial value
-0000000B
R/W : Read/Write enabled, R : Read only, W : Write only, : Not in use, X : Undefined
70
W
00000000B R/W, R
CSR0
bit
W
Initial value
00000000B
RCR1
R
Initial value
00000000B
RCR0
R
Initial value
00000000B
UDCR1
bit
Initial value Access
00000000B
UDCR0
bit
Address : 000064H
3
R/W
MB91151A
16. Peripheral STOP Control
This function can be used to stop the clock of unused resources in order to conserve more power.
• Register List
Address
bit7
bit0
Initial value
Access
000090H
STPR0
0000 - - - - B
R/W
000091H
STPR1
00000 - 00B
R/W
000092H
STPR2
000000 - - B
R/W
R/W : Read/Write enabled, : Not in use
71
MB91151A
■ SERIAL START UP
The serial startup mode is the internal RAM (2 KB) serial write or RAM program startup mode using the internal
dedicated ROM. While this mode executes communication through the UART channel 1 built in this model, it
can also serve for data transfer to external flash memory. Either synchronous or asynchronous communication
can be selected by setting the relevant pin. For asynchronous communication, a baud rate of 9600 bps can be
used either at a machine clock frequency of 25 MHz (oscillation frequency of 12.5 MHz) orat a machine clock
frequency of 33 MHz (oscillation frequency of 16.5 MHz) selectively.
(Note that serial startup using asynchronous communication cannot be performed at a machine clock frequency
of 36 MHz at an oscillation frequency of 18 MHz.)
• Communication specifications
(1) Asynchronous communication at a machine clock frequency of 33 MHz
The device performs serial communication in the asynchronous (normal) mode of UART channel 1.
The baud rate is 9600 bps at a machine clock frequency of 33 MHz (based on a 16.5 MHz external crystal
oscillator) .
Serial mode settings are : a data length of 8 bits, a stop bit length of 1 bit, no parity, and LSB-first transfer.
(2) Asynchronous communication at a machine clock frequency of 25 MHz
The device performs serial communication in the asynchronous (normal) mode of UART channel 1.
The baud rate is 9600 bps at a machine clock frequency of 25 MHz (based on a 12.5 MHz external crystal
oscillator) .
Serial mode settings are : a data length of 8 bits, a stop bit length of 1 bit, no parity, and LSB-first transfer.
(3) Synchronous communication
The device performs serial communication in the synchronous (normal) mode of UART channel 1.
The baud rate can be set freely depending on the external clock input (the baud rate is determined directly by
the external clock frequency) .
The maximum input frequency of the external clock is the peripheral operating clock frequency devided by 8.
(The peripheral operating clock setting is the fastest PLL frequency.)
Serial mode settings are : a data length of 8 bits, no parity, and LSB-first transfer.
In each fo these modes, the devices passes the following three items of download information data to the FR,
byte by byte in sequence from the high-order byte :
1. Command data (00H)
2. 4 bytes of the download destination RAM address (00080400H to 000807FFH)
3. 4 bytes specifying the number of bytes download (up to 000003FFH)
Then the device gives resulting SUM check data (the lower eight bits extracted from these data items added
together) , entering the RAM download routine.
The device then passes the data to be downloaded to RAM to the FR, byte by byte in sequence from the highorder byte, and the resulting SUM check data as well in the same way. Upon completion of transfer, a jump to
RAM takes place and the downloaded program is executed.
Method of setting
External pin name
72
MD2
MD1
MD0
PG5
PG4
PG3
Asynchronous communication •
machine clock 33 MHz
1
1
0
1
0
0
Asynchronous communication •
machine clock 25 MHz
1
1
0
1
0
1
Synchronous communication
1
1
0
1
1
0
MB91151A
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0.0 V)
Symbol
Rating
Min
Max
Unit
Remarks
Power supply voltage
VCC
VSS − 0.3
VSS + 3.6
V
Analog supply voltage
AVCC
VSS − 0.3
VSS + 3.6
V
*1
Analog reference voltage
AVRH
VSS − 0.3
VSS + 3.6
V
*1
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Input voltage
(open drain port J)
VI2
VSS − 0.3
VSS + 5.5
V
Analog pin input voltage
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 0.3
V
“L” level maximum output current
IOL
10
mA
*2
“L” level average output current
IOLAV
4
mA
*3
“L” level total maximum output current
ΣIOL
100
mA
ΣIOLAV
50
mA
*4
IOH
−10
mA
*2
“H” level average output current
IOHAV
−4
mA
*3
“H” level total maximum output current
ΣIOH
−50
mA
ΣIOHAV
−20
mA
Power consumption
PD
500
mW
Operating temperature
TA
0
+70
°C
Tstg
−55
+150
°C
“L” level total average output current
“H” level maximum output current
“H” level total average output current
Storage temperature
*4
*1 : Take care not to exceed VCC + 0.3 V when turning on the power, for example.
Take care also to prevent AVCC from exceeding VCC when turning on the power, for example.
*2 : The maximum output current stipulates the peak value of a single concerned pin.
*3 : The average output current stipulates the average current flowing through a single concerned pin over a period
of 100 ms.
*4 : The total average output current stipulates the average current flowing through all concerned pins over a period
of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
73
MB91151A
2. Recommended Operating Conditions
Parameter
Symbol
Power supply voltage
VCC
Analog supply voltage
(VSS = AVSS = 0.0 V)
Value
Min
Max
3.15
3.6
Unit
During normal operations.
V
2.0
3.6
AVCC
VSS + 3.15
VSS + 3.6
V
Analog reference voltage
(High voltage side)
AVRH
AVCC−0.3
AVCC
V
Analog reference voltage
(Low voltage side)
AVRL
AVSS
AVSS + 0.3
V
TA
0
+70
°C
Operating temperature
Remarks
The RAM state is retained
when stopped.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
74
MB91151A
3. DC Characteristics
Parameter
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Pin name
Condition
VIH
Input except for
hysteresis input pin*
VIHS
Symbol
Value
Unit
Remarks
Min
Typ
Max
0.65 × VCC
VCC + 0.3
V
Hysteresis input
pin*
0.8 × VCC
VCC + 0.3
V
VIL
Input except for
hysteresis input pin*
VSS − 0.3
0.25 × VCC
V
VILS
Hysteresis input
pin*
VSS − 0.3
0.2 × VCC
V
“H” level output
voltage
VOH
Except for port J.
VCC = 3.15 V,
VCC − 0.5
IOH = 4.0 mA
V
“L” level output
voltage
VOL
Except for port J.
VCC = 3.15 V,
IOL = 4.0 mA
0.4
V
Input leakage
current
ILI
VCC = 3.6 V,
VSS <VI < VCC
±5
µA
“L” level output
voltage
VOL2
Port J
VCC = 3.15 V,
IOL = 15 mA
0.4
V
Open drain
Output application voltage
VD
Port J
VCC − 0.3
VSS + 5.0
V
Open drain
50
kΩ
“H” level input
voltage
“L” level input
voltage
Pull-up
resistance
Power supply
current
Input capacity
RPULL RST, pull-up pin
ICC
VCC
VCC = 3.3 V
85
120
mA
ICCS
VCC
VCC = 3.3 V
60
100
mA
During sleep
mode
ICCH
VCC
VCC = 3.3 V,
TA = +25 °C
15
150
µA
In stop mpde
CIN
Other than VCC, VSS,
AVCC, AVSS, and
AVRH
10
pF
* : See “■ I/O CIRCUIT TYPE”.
75
MB91151A
4. AC Characteristics
(1) Clock Timing Ratings
Parameter
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Clock frequency
(high speed and self oscillation)
Clock frequency
(high speed and PLL in use)
fC
tC
Input clock pulse width
PWH
PWL
Input clock rising
tcr
Input clock falling
tcf
Internal operating clock frequency
Internal operating clock cycle
time
CPU
system
fCP
Bus
system
fCPB
Peripheral
system
fCPP
CPU
system
tCP
Bus
system
tCPB
Peripheral
system
Value
Min
Max
Unit
Remarks
Range in which self
oscillation is allowed
MHz Range in which self
oscillation and the
use of the PLL for external clock input are
allowed
10
18
10
18
X0, X1
55.6
100
ns
X0, X1
25
ns
15
ns
X0, X1
8
ns
0.625*3
36
0.625*3
25*2
0.625*3
33
Analog section excluded. *1
1
33
Analog section *1
27.8
1600*3
40*2
1600*3
30.3
1600*3
30.3
1000
X0, X1
Clock frequency
(High speed an 1/2 division
input)
Clock cycle time
Condition
tCPP
One wait is
set with the
wait controller.
Range in which exterMHz nal clocks can be input
(tcr+tcf)
MHz
ns
Analog section excluded. *1
Analog section *1
*1 : The target analog section is the A/D.
*2 : The maximum external bus operating frequency allowed is 25 MHz.
*3 : The value when a minimum clock frequency of 10 MHz is input to X0 and half a division of the oscillator circuit
and the 1/8 gear are in use.
76
MB91151A
tC
PWH
PWL
tcf
tcr
VCC
Supply voltage (V)
Operation assurance range
3.6
fCPP
3.15
fCP
0.625 M
Frequency (Hz)
36 M
The relationship between the X0 input and the internal clock set with the CHC/CCK1/CCK0 bit of the GCR (Gear
Control Register) is as shown next.
X0 input
• Source oscillation × 1
(GCR CHC bit : 0)
(a) Gear × 1 internal clock
CCK1/0 : 00
(b) Gear × 1/2 internal clock
CCK1/0 : 01
tCYC
tCYC
tCYC
(c) Gear × 1/4 internal clock
CCK1/0 : 10
tCYC
(d) Gear × 1/8 internal clock
CCK1/0 : 11
• Source oscillation × 1/2
(GCR CHC bit : 1)
(a) Gear × 1 internal clock
CCK1/0 : 00
(b) Gear × 1/2 internal clock
CCK1/0 : 01
(c) Gear × 1/4 internal clock
CCK1/0 : 10
(d) Gear × 1/8 internal clock
CCK1/0 : 11
tCYC
tCYC
tCYC
tCYC
77
MB91151A
(2) Clock Output Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin
name
tCYC
CLK
Cycle time
CLK↑→CLK↓
tCHCL
CLK
CLK↓→CLK↑
tCLCH
CLK
Value
Condition
Min
Max
tCP
tCPB
Unit
ns
Remarks
*1
At using doubla
tCYC/2−10 tCYC/2+10
ns
*2
tCYC/2−10 tCYC/2+10
ns
*3
tCYC
tCLCH
tCHCL
VOH
VOH
VOL
CLK
*1 : tCYC is a frequency for one clock including a gear cycle.
The doubler is used when the CPU runs at 25 MHz or higher.
*2 : Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, or 1/8 is set, substitute 1/2, 1/4, or 1/8 for “n” in the following equations, respectively.
• Min : (1−n/2) × tCYC−10
• Max : (1−n/2) × tCYC+10
When the doubler is used, set the gear cycle to × 1.
*3 : Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, or 1/8 is set, substitute 1/2, 1/4, or 1/8 for “n” in the following equations, respectively.
• Min : n/2 × tCYC−10
• Max : n/2 × tCYC+10
When the doubler is used, set the gear cycle to × 1.
78
MB91151A
(3) Reset Input Ratings
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Reset input time
Symbol
Pin
name
Condition
tRSTL
RST
Value
Min
Max
tCP × 5
Unit
Remarks
ns
tRSTL
RST
0.2 VCC
(4) Power On Reset
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Power supply rising time
tR
Power supply cutoff time
tOFF
Pin
name
Condition
VCC
tR
VCC
Value
Unit
Remarks
20
ms
VCC < 0.2 V before
turning up the power.
ms
Min
Max
2
tOFF
0.9 × VCC
0.2 V
A rapid change in supply voltage might activate power on reset.
When the supply voltage needs to be varied while operating, it is recommended to minimize
fluctuations to smoothly start up the voltage.
VCC
Holding RAM data.
It is recommended to keep the rising
inclination less than 50 mV/ms.
VSS
VCC
RST
tRSTL
When turning on the power, start the RST pin in
“L” level state, allow as much time as for tRSTL after
reaching the VCC power supply level and then set
the pin to the H level.
79
MB91151A
(5) Serial I/O (CH0 to CH4)
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid SIN hold time
tSHIX
Serial clock “H” pulse width
Parameter
Condition
Value
Max
8 tCPP
ns
−10
+50
ns
50
ns
50
ns
tSHSL
4 tCPP − 10
ns
Serial clock “L” pulse width
tSLSH
4 tCPP − 10
ns
SCK ↓ → SOT delay time
tSLOV
0
50
ns
Valid SIN → SCK ↑
tIVSH
50
ns
SCK ↑ → valid SIN hold time
tSHIX
50
ns
Serial busy period
tBUSY
6 tCPP
ns
Internal
clock
External
clock
Internal shift clock mode
tSCYC
SCK
tSLOV
SOT
SIN
tSHIX
tIVSH
External shift clock mode
tSLSH
tSHSL
SCK
tSLOV
SOT
SIN
tIVSH
80
Unit Remarks
Min
tSHIX
tBUSY
MB91151A
(6) External Bus Measurement Conditions
The following conditions apply to items that are not specifically stipulated.
• AC characteristics measurement conditions
VCC : 3.3 V
Input
Output
VCC
VIH
VOH
VIL
VOL
0V
VIH
2.4 V
VOH
1/2VCC
VIL
0.8 V
VOL
1/2VCC
(The input rise/fall time is less
than 10 ns.)
• Load condition
Output pin
C = 50 pF
( VCC : 3.3 V )
81
MB91151A
(7) Normal Bus Access and Read/Write Operations
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
CS0 to CS3 delay time
tCHCSL
CS0 to CS3 delay time
tCHCSH
CLK
CS0 to CS3
Address delay time
tCHAV
Data delay time
tCHDV
RD delay time
tCLRL
RD delay time
tCLRH
WR0 to WR1 delay time
tCLWL
WR0 to WR1 delay time
tCLWH
Valid address →
valid data input time
tAVDV
RD ↓ → valid data input time
tRLDV
Data setup → RD ↑ time
tDSRH
RD ↑ → Rdata hold time
tRHDX
Condition
Value
Unit
Remarks
Min
Max
15
ns
15
ns
CLK
A23 to A00
15
ns
CLK
D31 to D16
15
ns
10
ns
10
ns
10
ns
10
ns
3/2×
tCYC − 13
ns
*1, *2
tCYC − 25
ns
*1
25
ns
0
ns
CLK
RD
CLK
WR0 to WR1
A23 to A00
D31 to D16
RD
D31 to D16
*1 : If the bus is extended with either automatic wait insertion or RDY input, add the (tCYC × the number of extended
cycles) time to this value.
*2 : This is the value at the time of (gear cycle × 1) .
When the gear cycle is set to 1/2, 1/4 or 1/8, substitute “n” in the following formula with 1/2, 1/4 or 1/8 respectively.
Formula : (2 − n / 2) × tCYC − 13
82
MB91151A
tCYC
BA1
BA2
VOH
VOH
VOL
CLK
VOH
VOL
tCHCSH
tCHCSL
VOH
CS0 to CS3
VOL
tCHAV
VOH
VOL
A23 to A00
tCLRL
tCLRH
VOH
RD
VOL
tRLDV
tRHDX
tAVDV
tDSRH
VIH
VIL
D31 to D16
tCLWL
Read
VIH
VIL
tCLWH
VOH
WR0 to WR1
VOL
tCHDV
D31 to D16
VOH
VOL
Write
83
MB91151A
(8) Ready Input Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
RDY setup time → CLK ↓
CLK ↓ → RDY hold time
Symbol
Pin
name
tRDYS
RDY
CLK
tRDYH
RDY
CLK
Condition
Value
Unit
Min
Max
20
ns
0
ns
tCYC
CLK
VOH
VOH
VOL
VOL
tRDYS tRDYH
84
When
RDY wait
is applied
VIL
When
RDY wait
is not applied
VIH
tRDYS tRDYH
VIH
VIL
VIL
VIH
VIH
VIL
Remarks
MB91151A
(9) Hold Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Pin
name
Symbol
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
Pin floating → BGRNT ↓ time
tXHAL
BGRNT ↑ → Pin valid time
tHAHV
CLK
BGRNT
Condition
BGRNT
Value
Unit
Min
Max
10
ns
10
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Remarks
Note : More than one cycle exist after BRQ is fetched and before BGRNT changes.
tcyc
CLK
VOH
VOH
VOH
BRQ
tCHBGL
tCHBGH
VOH
BGRNT
VOL
tXHAL
tHAHV
Each pin
High impedance
85
MB91151A
(10) DMA Controller Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
DREQ input pulse width
tDRWH
DREQ0 to DREQ2
DACK delay time
(typical bus)
(typical DRAM)
tCLDL
DEOP delay time
(typical bus)
(typical DRAM)
DACK delay time
(Single Dram)
(Hyper Dram)
DEOP delay time
(Single Dram)
(Hyper Dram)
tCLDH
tCLEL
tCLEH
tCHDL
tCHDH
tCHEL
tCHEH
Value
Condition
Max
2 tCYC
ns
6
ns
6
ns
6
ns
6
ns
n / 2 × tCYC
ns
6
ns
n / 2 × tCYC
ns
6
ns
CLK
DACK0 to DACK2
CLK
DEOP0 to DEOP2
CLK
DACK0 to DACK2
CLK
DEOP0 to DEOP2
tcyc
VOH
VOH
CLK
VOL
DACK0 to DACK2
DEOP0 to DEOP2
(Typical bus)
(Typical DRAM)
DACK0 to DACK2
DEOP0 to DEOP2
( Single DRAM )
( Hyper DRAM )
VOL
tCLDH
tCLDL
tCLEL
tCLEH
VOH
VOL
tCHDH
tCHDL
VOH
VOL
tCHEL
tDRWH
DREQ0 to
DREQ2
86
VIH
Unit Remarks
Min
VIH
MB91151A
5. A/D Converter Electrical Characteristics
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Resolution
Conversion time
Total error
Linearity error
Differential linearity error
Zero transition error
VOT
AN0 to
AN7
Full-scale transition error
VFST
AN0 to
AN7
Analog input current
IAIN
AN0 to
AN7
Analog input voltage
VAIN
AN0 to
AN7
Reference voltage
AVRH
AVRH
Parameter
Conversion
Supply cur- in operation
rent
Conversion
stopped
Reference
voltage
supply current
AVCC = 3.3 V,
AVRH = 3.3 V
AVCC = 3.3 V,
AVRH = 3.3 V
AVCC
Conversion
stopped
IRH
AVRH
AN0 to
AN7
Unit
Min
Typ
Max
10
Bit
5.1
µs
±4.0
LSB
±3.5
LSB
±2.0
LSB
Remarks
AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB
AVRH − 5.5 AVRH − 1.5 AVRH + 0.5 LSB
0.1
10
µA
AVSS
AVRH
V
AVCC
V
3.0
5.0
mA
5.0
µA
2.0
3.0
mA
10
µA
4
LSB
AVCC = 3.3 V
IAH
IR
Value
IA
Conversion
in operation
Interchannel variation
Condition
AVCC = 3.3 V,
AVRH = 3.3 V
Notes : • The smaller the |AVRH| is, the greater the error is in general.
• The external circuit output impedance of analog input should be used in compliance with the following
requirements :
External circuit output impedance ≤ 2 (kΩ)
If the output impedance of the external circuit is too high, an analog voltage sampling duration shortage
might occur. (Sampling duration = 1.4 µs : @33 MHz)
87
MB91151A
• A/D Converter Glossary
• Resolution
: Analog changes that are identifiable by the A/D converter.
• Linearity error
: The deviation of the straight line connecting the zero transition point
(00 0000 0000 ←→ 00 0000 0001) with the full-scale transition point
(11 1111 1110 ←→ 11 1111 1111) from actual conversion characteristics.
• Differential linearity error : The deviation of input voltage needed to change the output code by one LSB
from the theoretical value.
• Total error
: The difference between actual and theoretical conversion values including a
zero transition/full-scale transition/linearity error.
Total error
3FF
3FE
Digital output
3FD
Actual conversion
characteristics
{1 LSB' ( N − 1 ) + 0.5 LSB'}
1.5 LSB'
004
VNT
(Actual measurement)
Actual conversion
characteristics
003
002
Theoretical characteristics
001
0.5 LSB'
AVSS
Analog input
1 LSB’ (theoretical value) =
AVRH − AVSS
1024
[V]
VOT’ (theoretical value) =
AVSS + 0.5 LSB’
[V]
AVRH
VFST’ (theoretical value) = AVRH − 1.5 LSB’ [V]
Total error of digital output N =
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
VNT : Voltage at which digital output changes from (N + 1) to N.
(Continued)
88
MB91151A
(Continued)
Differential linearity error
Linearity error
3FF
Actual conversion
characteristics
N+1
{1 LSB ( N − 1 ) + VOT}
Digital output
Theoretical
characteristics
VFST
(Actual
measurement)
3FD
Digital output
3FE
004
VNT
(Actual
measurement)
Actual conversion
characteristics
Theoretical characteristics
003
002
N−2
AVSS
1 LSB =
Actual conversion
characteristics
AVSS
AVRH
Analog input
Differential linearity error =
of digital output N
VFST
(Actual
measurement)
VNT
(Actual
measurement)
VOT
(Actual measurement)
=
N
N−1
001
Linearity error of digital
output N
Actual conversion
characteristics
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
[LSB]
V (N + 1) T − VNT
1 LSB
[LSB]
VFST − VOT
1022
−1
AVRH
Analog input
[V]
VOT : Voltage at which digital output changes from (000) H to (001) H.
VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
6. D/A Converter Electrical Characteristics
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Symbol
Pin
name
Condition
Min
Typ
Max
Resolution
8
Bit
Differential linearity error
1
LSB
Conversion time
20
µs
Analog output impedance
29
kΩ
Parameter
Remarks
Unit
*
* : CL = 20 pF
89
MB91151A
■ EXAMPLE CHARACTERISTICS
(1) “H” level output voltage
(2) “L” level output voltage
“H” output voltage vs. Power supply voltage
“L” output voltage vs. Power supply voltage
5
400
350
4
VOL [mV]
VOH [V]
300
3
2
250
200
150
100
1
50
0
2.8
0
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
3.0
3.2
(3) “L” level output voltage (open drain)
350
70
300
60
250
50
R [k ]
VOL [mV]
80
200
30
100
20
50
10
3.4
3.6
VCC [V]
3.8
4.0
4.2
40
150
3.2
3.8
Pull-up resistance vs. Power supply voltage
400
3.0
3.6
(4) Pull-up resistance
“L” output voltage (open drain) vs.
Power supply voltage
0
2.8
3.4
VCC [V]
VCC [V]
4.0
4.2
0
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
VCC [V]
(Continued)
90
MB91151A
(Continued)
(5) Power supply current
Power supply current vs. Voltage
(6) Power supply current at sleeping
Power supply current (sleep) vs. Voltage
120
80
ICCS [mA]
ICC [mA]
100
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
2.8
2.8
3.0
3.2
3.4
3.6
3.8
3.0
(7) Power supply current at stopping
3.6
3.8
A/D conversion power supply voltage vs.
Power supply voltage
120
5
100
4
80
IA [mA]
ICCH [ A]
3.4
(8) A/D conversion power supply voltage (36 MHz)
Power supply current (stop) vs. Voltage
60
40
0
3
2
1
20
2.8
3.0
3.2
3.4
3.6
3.8
0
2.8
3.0
VCC [V]
A/D conversion reference power supply current vs.
Voltage
3.4
3.6
3.8
(10) D/A conversion reference power supply current
per 1 ch
D/A conversion reference power supply current per
1 ch vs. power supply voltage
1.0
2.0
0.8
IADA [mA]
1.5
1.0
0.5
0.0
2.8
3.2
VCC [V]
(9) A/D conversion reference power supply current
(36 MHz)
IR [mA]
3.2
VCC [V]
VCC [V]
0.6
0.4
0.2
3.0
3.2
3.4
VCC [V]
3.6
3.8
0.0
2.8
3.0
3.2
3.4
3.6
3.8
VCC [V]
91
MB91151A
■ ORDERING INFORMATION
Part number
MB91151APMT2-G
92
Package
144-pin plastic LQFP
(FPT-144P-M08)
Remarks
MB91151A
■ PACKAGE DIMENSION
144-pin plastic LQFP
(FPT-144P-M08)
*Pins width and pins thickness include plating thickness.
22.00±0.20(.866±.008)SQ
20.00±0.10(.787±.004)SQ
108
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0°~8°
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
2000 FUJITSU LIMITED F144019S-c-2-4
Dimensions in mm (inches)
93
MB91151A
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0206
FUJITSU LIMITED Printed in Japan