FUJITSU MB91F467SAPMC-GSE2

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16617-2E
32-bit Microcontroller
CMOS
FR60 MB91460S Series
MB91F467SA
■ DESCRIPTION
MB91460S series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control
applications which require high-speed real-time processing, such as consumer devices and on-board vehicle
systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs.
This series contains the LIN-USART, CAN and APIX® controllers.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Microelectronics Limited.
■ FEATURES
1. FR60 CPU core
•
•
•
•
•
•
•
•
•
•
32-bit RISC, load/store architecture, five-stage pipeline
16-bit fixed-length instructions (basic instructions)
Instruction execution speed: 1 instruction per cycle
Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions
suitable for embedded applications
Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C
language
Register interlock function: Facilitating assembly-language coding
Built-in multiplier with instruction-level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Interrupts (save PC/PS) : 6 cycles (16 priority levels)
Harvard architecture enabling program access and data access to be performed simultaneously
Instructions compatible with the FR family
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.9
MB91460S Series
2. Internal peripheral resources
• General-purpose ports : Maximum 133 ports
• DMAC (DMA Controller)
Maximum of 5 channels able to operate simultaneously.
2 transfer sources (internal peripheral/software)
Activation source can be selected using software.
Addressing mode specifies full 32-bit addresses (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (successive approximation type)
10-bit resolution: 16 channels
Conversion time: minimum 1 μs
• External interrupt inputs : 16 channels
Shares the CAN RX pin and I2C SDA pin
• Bit search module (for REALOS)
Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word
• LIN-USART (full duplex double buffer): 6 channels
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
• I2C bus interface (supports 400 kbps): 3 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
• CAN controller (C-CAN): 2 channels
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
• APIX® controller
APIX® link (105Mbit / 6Mbit): 1 channel
Automotive Interconnect links (5Mbit / 6Mbit): 2 links
• Sound generator : 1 channel
Tone frequency : PWM frequency divide-by-two (reload value + 1)
• Alarm comparator : 1 channel
Monitor external voltage
Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage)
• 16-bit PPG timer : 16 channels
• 16-bit PFM timer : 1 channel
• 16-bit reload timer: 8 channels
• 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU)
• Input capture: 8 channels (operates in conjunction with the free-run timer)
• Output compare: 4 channels (operates in conjunction with the free-run timer)
• Up/Down counter: 4 channels (4×8-bit or 2×16 bit)
• Watchdog timer
• Real-time clock
• Low-power consumption modes : Sleep/stop mode function
• Low voltage detection circuit
• Clock monitor
2
DS07-16617-2E
MB91460S Series
• Clock supervisor
Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator,
etc.) when the oscillations stop.
• Clock modulator *
• Sub-clock calibration
Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator
• Main oscillator stabilization timer
Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization
wait time counter
• Sub-oscillator stabilization timer
Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization
wait time counter
3. Package and technology
• Package : LQFP-176
• CMOS 0.18 μm technology
• Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter)
• Operating temperature range: between − 40°C and + 105°C
* : The clock modulator is currently being evaluated and should not be used for other purpose than testing.
Note
APIX® is a registered mark of INOVA Semiconductors GmbH
DS07-16617-2E
3
MB91460S Series
■ PRODUCT LINEUP
Feature
MB91V460A
MB91F467SA
Max. core frequency (CLKB)
80MHz
100MHz
Max. resource frequency (CLKP)
40MHz
50MHz
Max. external bus freq. (CLKT)
40MHz
50MHz
Max. CAN frequency (CLKCAN)
20MHz
40MHz
Max. FlexRay frequency (SCLK)
-
-
0.35μm
0.18μm
yes
yes
Technology
Watchdog
Watchdog (RC osc. based)
yes (disengageable)
yes
Bit Search
yes
yes
Reset input (INITX)
yes
yes
Hardware Standby input (HSTX)
yes
no
Clock Modulator
yes
yes
Clock Monitor
yes
yes
Low Power Mode
yes
yes
DMA
5 ch
5 ch
MAC (μDSP)
no
no
MPU (16 ch) 1)
MPU (8 ch) 1)
Emulation SRAM 32bit read
data
1088 KByte
Satellite Flash
-
no
Flash Protection
-
yes
D-RAM
64 KByte
32 KByte
ID-RAM
64 KByte
32 KByte
Flash-Cache (Instruction cache)
16 KByte
8 KByte
4 KByte fixed
4 KByte
RTC
1 ch
1 ch
Free Running Timer
8 ch
8 ch
ICU
8 ch
8 ch
OCU
8 ch
4 ch
Reload Timer
8 ch
8 ch
PPG 16-bit
16 ch
16 ch
MMU/MPU
Flash
Boot-ROM / BI-ROM
PFM 16-bit
1 ch
1 ch
Sound Generator
1 ch
1 ch
4 ch (8-bit) / 2 ch (16-bit)
4 ch (8-bit) / 2 ch (16-bit)
Up/Down Counter (8/16-bit)
(Continued)
4
DS07-16617-2E
MB91460S Series
(Continued)
Feature
MB91V460A
MB91F467SA
6 ch (128msg)
2 ch (32msg)
4 ch + 4 ch FIFO + 8 ch
2 ch + 4 ch FIFO
4 ch
3 ch
-
2ch (1ch physical)
yes (32bit addr, 32bit data)
yes (24bit addr, 16bit data)
External Interrupts
16 ch
16 ch
NMI Interrupts
1 ch
1 ch
SMC
6 ch
-
LCD controller (40x4)
1 ch
-
ADC (10 bit)
32 ch
16 ch
Alarm Comparator
2 ch
1 ch
Supply Supervisor
yes
yes
Clock Supervisor
yes
yes
Main clock oscillator
4MHz
4MHz
Sub clock oscillator
32kHz
32kHz
RC Oscillator
C_CAN
LIN-USART
I2C (400k)
APIX
®
FR external bus
100kHz
100kHz / 2MHz
PLL
x 20
x 25
DSU4
yes
EDSU
Supply Voltage
Regulator
Power Consumption
yes (32 BP)
*1
yes (16 BP) *1
3V / 5V
3V / 5V
yes
yes
n.a.
<1W
Temperature Range (Ta)
0..70 C
-40..105 C
Package
BGA660
LQFP176
Power on to PLL run
< 20 ms
< 20 ms
Flash Download Time
n.a.
< 30 sec (2M)
*1 : MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
DS07-16617-2E
5
VSS5
P10_0 / SYSCLK / /SYSCLK
P10_1 / ASX
P10_3 / WEX
P08_0 / WRX0
P08_1 / WRX1
P08_4 / RDX
P08_7 / RDY
P24_7 / INT7
P24_6 / INT6
P24_5 / INT5 / SCL2
P24_4 / INT4 / SDA2
P24_3 / INT3
P24_2 / INT2
P24_1 / INT1
P20_0 / SIN2 / AIN0
P20_1 / SOT2 / BIN0
P20_2 / SCK2 / ZIN0 / CK2
P20_4 / SIN3 / AIN1
P20_5 / SOT3 / BIN1
P20_6 / SCK3 / ZIN1 / CK3
VDD5
VSS5
P23_0 / RX0 / INT8
P23_1 / TX0
P23_2 / RX1 / INT9
P23_3 / TX1
P16_7 / PPG15 / ATGX
P16_6 / PPG14 / PFM
P16_5 / PPG13 / SGO
P16_4 / PPG12 / SGA
P16_3 / PPG11
P16_2 / PPG10
P16_1 / PPG9
P16_0 / PPG8
P17_7 / PPG7 / TCKI1
P17_6 / PPG6 / TDA11
P17_5 / PPG5 / TDA10
P17_4 / PPG4
P17_3 / PPG3
P17_2 / PPG2 / RDA11
P17_1 / PPG1 / RDA10
P17_0 / PPG0 / RCK1
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P07_3/A3
P07_2/A2
P07_1/A1
P07_0/A0
P14_7/ICU7/TIN15/7/TTG31/23/15/7
P14_6/ICU6/TIN14/6/TTG30/22/14/6
P14_5/ICU5/TIN13/5/TTG29/21/13/5
P14_4/ICU4/TIN12/4/TTG28/20/12/4
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P22_7/SCL1
P22_6/SDA1/INT15
P22_5/SCL0
P22_4/SDA0/INT14
VSS5
VDD5
P22_2/INT13
P22_0/INT12
P23_6/INT11
P23_4/INT10
P28_7/AN15/TCKI0
P28_6/AN14/TDA01
P28_5/AN13/TDA00
P28_4/AN12
P28_3/AN11
P28_2/AN10/RDA01
P28_1/AN9/RDA00
P28_0/AN8/RCK0
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
VSS5
MB91460S Series
■ PIN ASSIGNMENT
1. MB91F467SA
(TOP VIEW)
VSS5
P07_4/A4
P07_5/A5
P07_6/A6
P07_7/A7
P06_0/A8
P06_1/A9
P06_2/A10
P06_3/A11
P06_4/A12
P06_5/A13
P06_6/A14
P06_7/A15
P05_0/A16
P05_1/A17
P05_2/A18
P05_3/A19
P05_4/A20
P05_5/A21
P05_6/A22
P05_7/A23
VDD35
VSS5
P01_0/D16
P01_1/D17
P01_2/D18
P01_3/D19
P01_4/D20
P01_5/D21
P01_6/D22
P01_7/D23
P00_0/D24
P00_1/D25
P00_2/D26
P00_3/D27
P00_4/D28
P00_5/D29
P00_6/D30
P00_7/D31
P09_0/CSX0
P09_1/CSX1
P09_2/CSX2
P09_3/CSX3
VDD35
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
LQFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS
ALARM
P18_6/SCK7/ZIN3/CK7
P18_5/SOT7/BIN3
P18_4/SIN7/AIN3
P18_2/SCK6/ZIN2/CK6
P18_1/SOT6/BIN2
P18_0/SIN6/AIN2
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
P24_0/INT0
MD_2
MD_1
MD_0
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
VSSA
VDDA
SDOUTM
SDOUTP
SDINM
SDINP
VSSA
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
VSS5
(FPT-176P-M07)
DS07-16617-2E
MB91460S Series
■ PIN DESCRIPTION
1. MB91F467SA
Pin no.
2 to 5
6 to 13
14 to 21
24 to 31
32 to 39
40 to 43
Pin name
P07_4 to P07_7
A4 to A7
P06_0 to P06_7
A8 to A15
P05_0 to P05_7
A16 to A23
P01_0 to P01_7
D16 to D23
P00_0 to P00_7
D24 to D31
P09_0 to P09_3
CSX0 to CSX3
46
47
48
49, 50
51
52
53
54
P10_0
SYSCLK
P10_1
ASX
P10_3
WEX
P08_0, P08_1
WRX0, WRX1
P08_4
RDX
P08_7
RDY
P24_7
INT7
P24_6
INT6
I/O
I/O circuit
type*
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
P24_5
55
INT5
SCL2
Function
General-purpose input/output ports
Signal pins of external address bus (bit4 to bit7)
General-purpose input/output ports
Signal pins of external address bus (bit8 to bit15)
General-purpose input/output ports
Signal pins of external address bus (bit16 to bit23)
General-purpose input/output ports
Signal pins of external data bus (bit16 to bit23)
General-purpose input/output ports
Signal pins of external data bus (bit24 to bit31)
General-purpose input/output ports
Chip select output pins
General-purpose input/output port
External bus clock output pin
General-purpose input/output port
Address strobe output pin
General-purpose input/output port
Write enable output pin
General-purpose input/output port
External write strobe output pin
General-purpose input/output port
External read strobe output pin
General-purpose input/output port
External ready input pin
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
I/O
C
External interrupt input pin
I2C bus clock input/output pin
(Continued)
DS07-16617-2E
7
MB91460S Series
Pin no.
Pin name
I/O
I/O circuit
type*
P24_4
56
INT4
General-purpose input/output port
I/O
C
58
59
P24_3
INT3
P24_2
INT2
P24_1
INT1
I/O
A
I/O
A
I/O
A
P20_0
60
SIN2
I/O
A
I/O
A
ZIN0
I/O
A
I/O
A
I/O
A
ZIN1
I/O
A
P23_1
TX0
Clock input/output pin of USART3
Up/down counter input pin
General-purpose input/output port
I/O
A
INT8
69
Data output pin of USART3
External clock input pin of free-run timer 3
P23_0
RX0
Data input pin of USART3
General-purpose input/output port
CK3
68
Up/down counter input pin
Up/down counter input pin
P20_6
SCK3
Clock input/output pin of USART2
General-purpose input/output port
BIN1
65
Data output pin of USART2
Up/down counter input pin
P20_5
SOT3
Data input pin of USART2
General-purpose input/output port
AIN1
64
External interrupt input pin
External clock input pin of free-run timer 2
P20_4
SIN3
General-purpose input/output port
General-purpose input/output port
CK2
63
External interrupt input pin
Up/down counter input pin
P20_2
SCK2
General-purpose input/output port
General-purpose input/output port
BIN0
62
External interrupt input pin
Up/down counter input pin
P20_1
SOT2
General-purpose input/output port
General-purpose input/output port
AIN0
61
External interrupt input pin
I2C bus DATA input/output pin
SDA2
57
Function
RX input/output pin of CAN0
External interrupt input pin
I/O
A
General-purpose input/output port
TX output pin of CAN0
(Continued)
8
DS07-16617-2E
MB91460S Series
Pin no.
Pin name
I/O
I/O circuit
type*
P23_2
70
RX1
General-purpose input/output port
I/O
A
INT9
71
P23_3
TX1
73
PPG15
I/O
A
I/O
A
77
78
79
P16_6
General-purpose input/output port
PPG14
I/O
A
PPG13
81
Output pin of PPG timer
Pulse frequency modulator output pin
General-purpose input/output port
I/O
A
Output pin of PPG timer
SGO
SGO output pin of sound generator
P16_4
General-purpose input/output port
PPG12
I/O
A
P16_3
PPG11
P16_2
PPG10
P16_1
PPG9
P16_0
PPG8
PPG7
Output pin of PPG timer
SGA output pin of sound generator
I/O
A
I/O
A
I/O
A
I/O
A
P17_7
80
PPG timer output pin
A/D converter external trigger input pin
SGA
76
TX output pin of CAN1
ATGX
P16_5
75
General-purpose input/output port
General-purpose input/output port
PFM
74
RX input/output pin of CAN1
External interrupt input pin
P16_7
72
Function
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
I/O
A
Output pin of PPG timer
TCKI1
AIC downlink clock of Apix® link1
P17_6
General-purpose input/output port
PPG6
TDA11
I/O
A
Output pin of PPG timer
AIC downlink data of Apix® link1
(Continued)
DS07-16617-2E
9
MB91460S Series
Pin no.
Pin name
I/O
I/O circuit
type*
P17_5
82
PPG5
General-purpose input/output port
I/O
A
84
P17_4
PPG4
P17_3
PPG3
I/O
A
I/O
A
P17_2
85
86
87
PPG2
Output pin of PPG timer
AIC downlink data of Apix® link1
TDA10
83
Function
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
I/O
A
Output pin of PPG timer
RDA11
AIC uplink data of Apix® link1
P17_1
General-purpose input/output port
PPG1
I/O
A
Output pin of PPG timer
RDA10
AIC uplink data of Apix® link1
P17_0
General-purpose input/output port
PPG0
I/O
A
Output pin of PPG timer
AIC uplink clock of Apix® link1
RCK1
90
MONCLK
O
M
91
MD_3
I
G00
92
X1
—
J1
Clock (oscillation) output
93
X0
—
J1
Clock (oscillation) input
95
X0A
—
J2
Sub clock (oscillation) input
96
X1A
—
J2
Sub clock (oscillation) output
97
INITX
I
H
External reset input pin
98
NMIX
I
H
Non-maskable interrupt input pin
100
SDINP
N1
Apix® uplink
101
SDINM
N1
Apix® uplink
102
SDOUTP
N2
Apix® downlink
103
SDOUTM
N2
Apix® downlink
112 to 114
MD_0 to MD_2
115
P24_0
INT0
I
G01
I/O
A
Clock monitor pin
Fast clock input pin
Mode setting pins
General-purpose input/output port
External interrupt input pin
(Continued)
10
DS07-16617-2E
MB91460S Series
Pin no.
116
117
Pin name
P19_0
SIN4
P19_1
SOT4
I/O
I/O circuit
type*
I/O
A
I/O
A
P19_2
118
SCK4
120
P19_4
SIN5
P19_5
SOT5
I/O
A
SCK5
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
ZIN2
I/O
A
I/O
A
BIN3
Data output pin of USART6
Clock input/output pin of USART6
Up/down counter input pin
Data input pin of USART7
Up/down counter input pin
P18_5
SOT7
Data input pin of USART6
General-purpose input/output port
AIN3
126
Clock input/output pin of USART5
External clock input pin of free-run timer 6
P18_4
SIN7
Data output pin of USART5
General-purpose input/output port
CK6
125
General-purpose input/output port
Up/down counter input pin
P18_2
SCK6
Data input pin of USART5
General-purpose input/output port
BIN2
124
General-purpose input/output port
Up/down counter input pin
P18_1
SOT6
Clock input/output pin of USART4
General-purpose input/output port
AIN2
123
Data output pin of USART4
External clock input pin of free-run timer 5
P18_0
SIN6
General-purpose input/output port
General-purpose input/output port
CK5
122
Data input pin of USART4
External clock input pin of free-run timer 4
P19_6
121
General-purpose input/output port
General-purpose input/output port
CK4
119
Function
General-purpose input/output port
I/O
A
Data output pin of USART7
Up/down counter input pin
(Continued)
DS07-16617-2E
11
MB91460S Series
Pin no.
Pin name
I/O
I/O circuit
type*
P18_6
127
SCK7
ZIN3
General-purpose input/output port
I/O
A
CK7
128
134 to 141
ALARM
P29_0 to P29_7
AN0 TO AN7
143
144
AN8
I
N1
I/O
B
146
I/O
B
148
149
General-purpose input/output ports
Analog input pins of A/D converter
Analog input pin of A/D converter
AIC uplink clock of Apix® link0
P28_1
General-purpose input/output port
AN9
I/O
B
Analog input pin of A/D converter
RDA00
AIC uplink data of Apix® link0
P28_2
General-purpose input/output port
AN10
I/O
B
P28_3
AN11
P28_4
AN12
AN13
Analog input pin of A/D converter
AIC uplink data of Apix® link0
I/O
B
I/O
B
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
I/O
B
Analog input pin of A/D converter
TDA00
AIC downlink data of Apix® link0
P28_6
General-purpose input/output port
AN14
I/O
B
Analog input pin of A/D converter
TDA01
AIC downlink data of Apix® link0
P28_7
General-purpose input/output port
AN15
I/O
B
P23_4
INT10
Analog input pin of A/D converter
AIC downlink clock of Apix® link0
TCKI0
150
Alarm comparator input pin
RCK0
P28_5
147
Up/down counter input pin
General-purpose input/output port
RDA01
145
Clock input/output pin of USART7
External clock input pin of free-run timer 7
P28_0
142
Function
I/O
A
General-purpose input/output port
External interrupt input pin
(Continued)
12
DS07-16617-2E
MB91460S Series
(Continued)
Pin no.
Pin name
P23_6
151
INT11
P22_0
152
INT12
P22_2
153
INT13
I/O
I/O circuit
type*
I/O
A
I/O
A
I/O
A
P22_4
156
SDA0
P22_5
SCL0
I/O
C
SDA1
I/O
C
P22_7
SCL1
I/O
C
OCU0 to OCU3
I/O
C
I/O
A
DS07-16617-2E
A0 to A3
General-purpose input/output port
I2C bus clock input/output pin
I2C bus data input/output pin
General-purpose input/output port
I2C bus clock input/output pin
Output compare output pins
Input capture input pins
I/O
A
TTG24/16/8/0 to
TTG31/23/15/7
P07_0 to P07_3
I2C bus data input/output pin
General-purpose input/output ports
ICU0 to ICU7
172 to 175
External interrupt input pin
Reload timer output pins
P14_0 to P14_7
TIN8/0 to TIN 15/7
General-purpose input/output port
General-purpose input/output ports
TOT0 to TOT3
164 to 171
External interrupt input pin
External interrupt input pin
P15_0 to P15_3
160 to 163
General-purpose input/output port
General-purpose input/output port
INT15
159
External interrupt input pin
External interrupt input pin
P22_6
158
General-purpose input/output port
General-purpose input/output port
INT14
157
Function
External trigger input pins of reload timer
External trigger input pins of PPG timer
I/O
A
General-purpose input/output ports
Signal pins of external address bus (bit0 to bit3)
13
MB91460S Series
[Power supply/Ground pins]
Pin no.
Pin name
I/O
Function
1, 23, 45, 67, 89, 94,
106, 111, 133, 155
VSS5
Ground pins
66, 88, 110, 132, 154
VDD5
Power supply pins
108, 109
VDD5R
129
AVSS
131
AVCC5
Power supply pin for A/D converter
130
AVRH5
Reference power supply pin for A/D converter
107
VCC18C
Capacitor connection pin for internal regulator
22, 44, 176
VDD35
Power supply pins for external bus part of I/O ring
99, 105
VSSA
Apix® ground supply pins
104
VDDA
Apix® power supply pin
Power supply pins for internal regulator
Supply
Analog ground pin for A/D converter
* : For information about the I/O circuit type, refer to “I/O CIRCUIT TYPES”.
14
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MB91460S Series
■ I/O CIRCUIT TYPES
Type
Circuit
A
Remarks
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
B
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
DS07-16617-2E
15
MB91460S Series
Type
Circuit
C
Remarks
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
D
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
16
DS07-16617-2E
MB91460S Series
Type
Circuit
E
Remarks
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
F
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
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17
MB91460S Series
Type
Circuit
Remarks
G00
CMOS Hysteresis input pin
R
Hysteresis
inputs
G01
R
Hysteresis
inputs
H
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
12 V resistant (for MD_[2:0])
CMOS Hysteresis input pin
Pull-up resistor value: 50 kΩ approx.
Pull-up
Resistor
R
Hysteresis
inputs
J1
X1
R
0
Xout
High-speed oscillation circuit:
Programmable between oscillation mode
(external crystal or resonator connected to X0/
X1 pins) and Fast external Clock Input (FCI)
mode (external clock connected to X0 pin)
Feedback resistor = approx. 2 * 0.5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled or in FCI mode.
1
FCI
R
X0
FCI or osc disable
18
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MB91460S Series
Type
Circuit
Remarks
J2
Xout
X1A
Low-speed oscillation circuit:
Feedback resistor = approx. 2 * 5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled.
R
R
X0A
osc disable
K
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
LCD SEG/COM output
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
LCD SEG/COM
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19
MB91460S Series
Type
Circuit
L
Remarks
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
LCD Voltage input
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
VLCD
M
CMOS level tri-state output
(IOL = 5mA, IOH = -5mA)
tri-state control
data line
N1/N2
Analog terminal
Type N1: Analog input pin with protection
Type N2: Analog output line with protection
analog line
20
DS07-16617-2E
MB91460S Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5 or VDD35) or less than (VSS5) is applied to an
input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground
pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown
of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
2. Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR)
before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or
VDD5 directly. Unused ALARM input pins can be connected to AVSS directly.
3. Power supply pins
In MB91460S series, devices including multiple power supply pins and ground pins are designed as follows;
pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pins and ground pins must be externally connected to the power supply and ground
respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground
level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of
the MB91460S series must be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between
power supply pin and ground pin near this device.
This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic
capacitor) to VCC18C pin for the regulator.
4. Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit
boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass
capacitors connected to ground, are located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and
X1A pins are surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
5. Notes on using external clock
5.1.
Opposite phase clock supply
When using the external clock, it is possible to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In
the described combination X0 (X0A) should be supplied with a clock signal which has the opposite phase to the
X1 (X1A) pins. However, in this case the stop mode (oscillation stop mode) must not be used (This is because
the X1 (X1A) pin stops at ”H” output in STOP mode).
With opposite phase supply at X0 and X1, a frequency up to 16 MHz is possible.
DS07-16617-2E
21
MB91460S Series
Example of using opposite phase supply
X0 (X0A)
X1 (X1A)
5.2.
Single phase clock supply
For lower frequencies, up to 4 MHz, it is possible to supply a single phase clock at X0 (X0A).
Example of using single phase supply
X0 (X0A)
X1 (X1A)
22
DS07-16617-2E
MB91460S Series
6. Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering
test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power
supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
MD_3 pin should be connected directly to ground.
7. Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may
continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed.
8. Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
9. Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in
the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
1) The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/
DIV0S instruction:
(a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due to a
data event or from the emulator menu.
-
D0 and D1 flags are updated in advance.
-
An EIT handling routine (user interrupt/NMI or emulator) is executed.
-
Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated
to the same values as those in 1).
2) The following behavior occurs when an ORCCR, STILM, MOV Ri, PS instruction is executed to enable a
user interrupt or NMI source while that interrupt is in the active state.
-
The PS register is updated in advance.
-
An EIT handling routine (user interrupt/NMI or emulator) is executed.
-
Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in 1).
DS07-16617-2E
23
MB91460S Series
■ NOTES ON DEBUGGER
1. Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding
interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the
main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base
timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base
timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.
2. Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the
current system stack pointer or to an area that contains the stack pointer, execution will break after each
instruction regardless of whether the user program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the
target of the hardware break (including an event breaks).
3. Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not
set the access to the areas containing the address of system stack pointer as a target of data event break.
24
DS07-16617-2E
MB91460S Series
■ BLOCK DIAGRAM
1. MB91F467SA
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
Flash memory
D-RAM
32 Kbytes
Bit search
1088 Kbytes
(MB91F467SA)
D-bus
32
CAN
2 channels
RX0, RX1
TX0, TX1
32 <-> 16
bus adapter
WEX
ASX
RDX
WRX0 to WRX1
ID-RAM
32 Kbytes
(MB91F467SA)
TCK0/1
TDA0/1
RCK0/1
RDA0/1
SDOUTP
SDOUTM
SDINP
SDINM
Bus converter
External
bus
interface
SYSCLK
RDY
CSX0 to CSX3
A0 to A23
APIX
DMAC
5 channels
R-bus
16
D0 to D31
Clock modulator
Clock supervisor
Clock monitor
Clock control
Interrupt controller
TTG0/8 to TTG7/15
PPG0 to PPG15
PPG timer
16 channels
TIN0 to TIN7
TOT0 to TOT3
Reload timer
8 channels
CK2 to CK7
ICU0 to ICU7
Free-run timer
8 channels
Input capture
8 channels
MONCLK
External interrupt
16 channels
INT0 to INT15
LIN-USART
6 channels
SIN2 to SIN7
SOT2 to SOT7
SCK2 to SCK7
I 2C
3 channels
SDA0 to SDA2
SCL0 to SCL2
Real time clock
OCU0 to OCU3
AIN0 to AIN3
BIN0 to BIN3
ZIN0 to ZIN3
PFM
ALARM
DS07-16617-2E
Output compare
4 channels
Up/down counter
4 channels
PFM timer
1 channel
Alarm comparator
1 channel
AN0 to AN15
A/D converter
16 channels
ATGX
Sound generator
1 channel
SGA
SGO
25
MB91460S Series
■ CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced
instructions for embedded applications.
1. Features
• Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
• General-purpose registers: 32-bit × 16 registers
• 4 Gbytes linear memory space
• Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
• Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode/stop mode
2. Internal architecture
• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent
of each other.
• A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and
peripheral resources.
• A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
26
DS07-16617-2E
MB91460S Series
3. Programming model
3.1.
Basic programming model
32 bits
Initial value
R0
XXXX XXXXH
R1
...
...
...
General-purpose registers
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply & divide registers
MDH
ILM
SCR
CCR
MDL
DS07-16617-2E
27
MB91460S Series
4. Registers
4.1.
General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
...
R1
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation
operations and as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2.
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits
is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
28
bit 10 bit 8 bit 7
SCR
bit 0
CCR
DS07-16617-2E
MB91460S Series
4.3.
CCR (Condition Code Register)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SV
S
I
N
Z
V
C
Initial value
- 000XXXXB
SV : Supervisor flag
S
: Stack flag
I
: Interrupt enable flag
N : Negative enable flag
Z
: Zero flag
V
: Overflow flag
C : Carry flag
4.4.
SCR (System Condition Register)
bit 10 bit 9
D1
bit 8
D0
Initial value
T
XX0B
Flag for step multiplication (D1, D0)
This flag stores interim data during execution of step multiplication.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
4.5.
ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
ILM4 ILM3 ILM2 ILM1 ILM0
Initial value
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
4.6.
PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
DS07-16617-2E
29
MB91460S Series
4.7.
TBR (Table Base Register)
bit 31
bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
4.8.
RP (Return Pointer)
bit 31
Initial value
bit 0
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
4.9.
USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
4.10. Multiply & divide registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
30
DS07-16617-2E
MB91460S Series
■ EMBEDDED PROGRAM/DATA MEMORY (FLASH)
1. Flash features
•
•
•
•
•
MB91F467SA: 1088 Kbytes (16 × 64 Kbytes + 8 × 8 Kbytes = 8.5 Mbits)
Programmable wait state for read/write access
Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F
Boot security
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
2. Operation modes
(1) 64-bit CPU mode :
• CPU reads and executes programs in word (32-bit) length units.
• Flash writing is not possible.
• Actual Flash Memory access is performed in d-word (64-bit) length units.
(2) 32-bit CPU mode :
• CPU reads, writes and executes programs in word (32-bit) length units.
• Actual Flash Memory access is performed in word (32-bit) length units.
(3) 16-bit CPU mode :
• CPU reads and writes in half-word (16-bit) length units.
• Program execution from the Flash is not possible.
• Actual Flash Memory access is performed in word (16-bit) length units.
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31
MB91460S Series
3. Flash access in CPU mode
3.1.
Flash configuration
3.1.1.
Flash memory map MB91F467SA
Address
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
ROMS7
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS6
addr+0
16bit read/write
32bit read/write
64bit read
32
addr+1
addr+2
dat[31:16]
addr+3
addr+4
dat[15:0]
addr+5
addr+6
dat[31:16]
dat[31:0]
addr+7
dat[15:0]
dat[31:0]
dat[63:0]
DS07-16617-2E
MB91460S Series
3.2.
Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or
maximum clock modulation) for Flash read and write access.
3.2.1.
Flash read timing settings (synchronous read)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
0
1
to 48 MHz
0
0
1
0
2
to 96 MHz
1
1
3
0
4
to 100 MHz
1
1
3
0
4
3.2.2.
Flash write timing settings (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 32 MHz
1
0
1
0
4
to 48 MHz
1
0
3
0
5
to 64 MHz
1
1
3
0
6
to 96 MHz
1
1
3
0
7
to 100 MHz
1
1
3
0
7
3.3.
Remark
Remark
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in
parallel programming.
3.3.1.
Address mapping MB91F467SA
CPU Address
Condition
(addr)
Flash
sectors
FA (flash address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
+ 00:2000h
04:0000h
to
13:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14,
SA16, SA18, SA20, SA22
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
04:0000h
to
13:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15,
SA17, SA19, SA21, SA23
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
+ 01:0000h
Note: FA result is without 20:0000h offset for parallel Flash programming .
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.
DS07-16617-2E
33
MB91460S Series
4. Parallel Flash programming mode
4.1.
Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD_[2:0] = 111):
MB91F467SA
FA[21:0]
003F:FFFFh
003F:0000h
SA23 (64KB)
003E:FFFFh
003E:0000h
SA22 (64KB)
003D:FFFFh
003D:0000h
SA21 (64KB)
003C:FFFFh
003C:0000h
SA20 (64KB)
003B:FFFFh
003B:0000h
SA19 (64KB)
003A:FFFFh
003A:0000h
SA18 (64KB)
0039:FFFFh
0039:0000h
SA17 (64KB)
0038:FFFFh
0038:0000h
SA16 (64KB)
0037:FFFFh
0037:0000h
SA15 (64KB)
0036:FFFFh
0036:0000h
SA14 (64KB)
0035:FFFFh
0035:0000h
SA13 (64KB)
0034:FFFFh
0034:0000h
SA12 (64KB)
0033:FFFFh
0033:0000h
SA11 (64KB)
0032:FFFFh
0032:0000h
SA10 (64KB)
0031:FFFFh
0031:0000h
SA9 (64KB)
0030:FFFFh
0030:0000h
SA8 (64KB)
002F:FFFFh
002F:E000h
SA7 (8KB)
002F:DFFFh
002F:C000h
SA6 (8KB)
002F:BFFFh
002F:A000h
SA5 (8KB)
002F:9FFFh
002F:8000h
SA4 (8KB)
002F:7FFFh
002F:6000h
SA3 (8KB)
002F:5FFFh
002F:4000h
SA2 (8KB)
002F:3FFFh
002F:2000h
SA1 (8KB)
002F:1FFFh
002F:0000h
SA0 (8KB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[21] = 1
34
DS07-16617-2E
MB91460S Series
4.2.
Pin connections in parallel programming mode
Resetting after setting the MD_[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s
interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of
the signals to GP-Ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set
when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash
memory’s Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MB91F467SA external pins
MBM29LV400TC
External pins
FR-CPU mode
⎯
Comment
Flash memory
mode
Normal function
Pin number
INITX
⎯
INITX
97
RESET
⎯
FRSTX
NMIX
98
⎯
⎯
MD2
MD2
114
⎯
⎯
MD1
MD1
113
⎯
⎯
MD0
MD0
112
RY/BY
FMCS:RDY bit
RY/BYX
GP19_1
117
BYTE
Internally fixed to ’H’
BYTEX
GP19_2
118
WE
WEX
GP18_0
122
OE
OEX
GP19_6
121
CEX
GP19_5
120
ATDIN
MD3
91
EQIN
MONCLK
90
⎯
TESTX
GP19_4
119
⎯
RDYI
GP19_1
117
A-1
FA0
GP09_1
41
A0 to A3
FA1 to FA4
GP06_0 to GP06_3
6 to 9
A4 to A7
FA5 to FA8
GP06_4 to GP06_7
10 to 13
FA9 to FA12
GP05_0 to GP05_3
14 to 17
A12 to A15
FA13 to FA16
GP05_4 to GP05_7
18 to 21
A16 to A19
FA17 to FA20
GP07_0 to GP07_3
172 to 175
⎯
FA21
GP09_0
40
DQ0 to DQ7
GP01_0 to GP01_7
24 to 31
DQ8 to DQ15
GP00_0 to GP00_7
32 to 39
CE
⎯
⎯
A8 to A11
Internal control signal
+ control via interface
circuit
Internal address bus
DQ0 to DQ7
Internal data bus
DQ8 to DQ15
DS07-16617-2E
35
MB91460S Series
5. Flash Security
5.1.
Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2)
controlling the protection functions of the Flash Security Module:
FSV1: 0x14:8000 BSV1: 0x14:8004
FSV2: 0x14:8008 BSV2: 0x14:800C
5.2.
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the
individual write protection of the 8 Kbytes sectors.
5.2.1.
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector FSV1 [31:16]
FSV1[18]
FSV1[17]
FSV1[16]
Write
Write
Read
FSV1[31:19]
Protection
Protection
Protection
Level
set all to “0”
set to “0”
set to “0”
set to “1”
Read Protection (all device modes,
except INTVEC mode MD_[2:0] = “000”)
set all to “0”
set to “0”
set to “1”
set to “0”
Write Protection (all device modes, without
exception)
set all to “0”
set to “0”
set to “1”
set to “1”
Read Protection (all device modes,
except INTVEC mode MD_[2:0] = “000”)
and Write Protection (all device modes)
set all to “0”
set to “1”
set to “0”
set to “1”
Read Protection (all device modes,
except INTVEC mode MD_[2:0] = “000”)
set all to “0”
set to “1”
set to “1”
set to “0”
Write Protection (all device modes,
except INTVEC mode MD_[2:0] = “000”)
set to “1”
Read Protection (all device modes,
except INTVEC mode MD_[2:0] = “000”)
and Write Protection (all device modes
except INTVEC mode MD_[2:0] = “000”)
set all to “0”
36
Flash Security Mode
set to “1”
set to “1”
DS07-16617-2E
MB91460S Series
5.2.2.
FSV1 (bit15 to bit0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the
8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV1 [15:0]
Enable Write
Disable Write
FSV1 bit
Sector
Protection
Protection
Comment
FSV1[0]
SA0
set to “0”
set to “1”
FSV1[1]
SA1
set to “0”
set to “1”
FSV1[2]
SA2
set to “0”
set to “1”
FSV1[3]
SA3
set to “0”
set to “1”
FSV1[4]
SA4
set to “0”
⎯
FSV1[5]
SA5
set to “0”
set to “1”
FSV1[6]
SA6
set to “0”
set to “1”
FSV1[7]
SA7
set to “0”
set to “1”
FSV1[8]
⎯
set to “0”
set to “1”
not available
FSV1[9]
⎯
set to “0”
set to “1”
not available
FSV1[10]
⎯
set to “0”
set to “1”
not available
FSV1[11]
⎯
set to “0”
set to “1”
not available
FSV1[12]
⎯
set to “0”
set to “1”
not available
FSV1[13]
⎯
set to “0”
set to “1”
not available
FSV1[14]
⎯
set to “0”
set to “1”
not available
FSV1[15]
⎯
set to “0”
set to “1”
not available
Write protection is mandatory!
Note : It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to
write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where
it is possible to either read out the Flash content or manipulate data by writing.
See section “Flash access in CPU mode” for an overview about the sector organization of the Flash
Memory.
DS07-16617-2E
37
MB91460S Series
5.3.
Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the
64 Kbytes sectors. It is only evaluated if write protection bit FSV1 [17] is set.
Explanation of the bits in the Flash Security Vector FSV2[31:0]
Enable Write
Disable Write
FSV1 bit
Sector
Protection
Protection
FSV2[0]
SA8
set to “0”
set to “1”
FSV2[1]
SA9
set to “0”
set to “1”
FSV2[2]
SA10
set to “0”
set to “1”
FSV2[3]
SA11
set to “0”
set to “1”
FSV2[4]
SA12
set to “0”
set to “1”
FSV2[5]
SA13
set to “0”
set to “1”
FSV2[6]
SA14
set to “0”
set to “1”
FSV2[7]
SA15
set to “0”
set to “1”
FSV2[8]
SA16
set to “0”
set to “1”
FSV2[9]
SA17
set to “0”
set to “1”
FSV2[10]
SA18
set to “0”
set to “1”
FSV2[11]
SA19
set to “0”
set to “1”
FSV2[12]
SA20
set to “0”
set to “1”
FSV2[13]
SA21
set to “0”
set to “1”
FSV2[14]
SA22
set to “0”
set to “1”
FSV2[15]
SA23
set to “0”
set to “1”
FSV2[31:16]
⎯
set to “0”
set to “1”
Comment
not available
Note : See section “Flash access in CPU mode” for an overview about the sector organization of the Flash Memory.
38
DS07-16617-2E
MB91460S Series
■ APIX® CONTROLLER
1. Overview
The integrated APIX® controller provides 2 links. Link 0 can be configured as an APIX® link or an Automotive
Interconnect (AIC) link. Link 1 only supports AIC link.
embedded PHY
Link
SB ch down
Pixel ch down
AS 0
SB ch up
ARH
AS 1
Downstream data
Upstream data
AIC Link 0
Downstream data
Upstream data
AIC Link 1
APIX® Controller
*Remark: Link 1 can be used only if Link 0 is activated (CHCTRL: TXCFG = 0)
APIX Link
Pixel Channel
downlink*
Media:
PHY
-
Sideband Channel
downlink*
PHY
AIC
uplink
PHY
AIC
AShell0
AShell0/1
*Remark: MB91460S series provides either downlink over Pixelchannel or over Sidebandchannel
DS07-16617-2E
39
MB91460S Series
2. Automotive Remote Handler
The Automotive Remote Handler provides an Interface to the APIX® controller.
2.1.
Register Description
2.1.1.
General Control
• RHCTRL: Address 07200h
31
RHCTRL
UNLOCK
R0/W
30
CANCEL
R0/W
23
R
R
R
7
6
-
UNLOCK
R
5
R0
R0
R0
R0
0(def)
Transaction on buffer TBNO is requested
1
Request unlock on waiting buffer TBNO
R
2
-
1
R0
8
EV
R
3
-
9
OFL
R
4
-
R0
10
LV
R0
-
R0
11
-
16
-
R0
12
FAT0
24
TBNO[0]
R/W
17
-
R0
13
FAT1
25
TBNO[1]
R/W
18
-
R0
14
WDG0
26
TBNO[2]
R/W
19
-
R0
15
WDG1
20
-
R0
27
TBNO[3]
R/W
R0
21
-
R0
28
-
R0
22
-
R0
29
-
0
R0
R0
Caution: Requested data gets lost or data is being received after using this
buffer with same IDX
CANCEL
TBNO[3:0]
WDG1
0(def)
Transaction on buffer TBNO is requested
1
Request cancel on pending buffer TBNO
0-15
Writing starts transaction on buffer number TBNO
readonly flag of enabled and selected CHWDG1.WDTXIRQx or enabled and
selected CHWDG1.WDRXIRQx
WDG0
readonly flag of enabled and selected CHWDG0.WDTXIRQx or enabled and
selected CHWDG0.WDRXIRQx
40
FAT0
readonly flag of enabled CHCTRL0.FATIRQ
FAT1
readonly flag of enabled CHCTRL1.FATIRQ
LV
readonly flag of enabled EVCTRL.LVIRQ
EV
readonly flag of enabled EVCTRL.EVIRQ
OFL
readonly flag of enabled EVCTRL.OFLIRQ
DS07-16617-2E
MB91460S Series
2.1.2.
Channel Control and Status
• CHCTRL0 (Link 0): Address 07208h
• CHCTRL1 (Link 1): Address 07214h
31
CHCTRL0-1
R0/WX
30
R0/WX
23
22
FATAL
14
UPRDY
R
7
Bit28
R/W
-
RX/W
5
UPVALID
R/(W)
R/W
17
FATIEN
R/W
RX/W
4
DNVALID
R/(W)
3
R0
2
TXCFG
R/W
24
-
R/W
18
-
RX/W
25
-
13
12
11
10
CONNECTED CRCERR
CRCTOUT
PERROR
READY
R
R(RM1)/W
R(RM1)/W
R(RM1)/W
R(RM1)/W
6
RX/WX
26
-
19
-
R
15
27
BYPASS
R/W
20
DNHSK
R
PLLGOOD
R
28
reserved
R/W0
21
UPHSK
R
RX/WX
29
R0/WX
16
FATIRQ
R(RM1)/W
9
8
REMOTERST
R(RM1)/W
1
RSTRTA
R/W
0
INITRH
R/W
reserved Bit
Always write 0 to this bit. The read value is the value written.
BYPASS:
0
Remote Handler active
1
Remote Handler inactive
In BYPASS mode Transaction Buffer 2 (for AShell 1) is used for downstream data (outbound) and Transaction
Buffer 3 (for AShell 1) is used for upstream data (inbound).
Valid written data in Transaction Buffer 0/2 is delivered to AShell by setting DNVALID.
Valid received data in Transaction Buffer 1/3 from AShell is marked by setting UPVALID.
FATAL
1
indicates that AShell has encountered conditions where AShell can not continue
to deliver and receive transactions. FATAL is only one CLKB cycle active.
UPHSK
1
indicates inbound handshake is performed
DNHSK
1
indicates outbound handshake is performed
FATIEN
0(def)
FATAL Interrupt disabled
1
FATAL Interrupt enabled
0(def)
FATAL Interrupt not active
1
FATAL Interrupt active, triggered by FATAL
FATIRQ
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
*Remark: While Fatal Interrupt is active, the corresponding channel is deactivated and the triggered buffers are
canceled.
UPRDY
1
indicates that upstream serial channel (APIX® PHY) is operational
CONNECTED 1
a connection to remote APIX® is established
CRCERR
indicates occurrence of CRC error in upstream data (inbound)
1
*Remark: On a RMW instruction a “1” is read; write “0” clears the flag; write “1” is ignored
CRCTOUT
1
indicates occurrence of CRC timeout in upstream data (inbound)
*Remark: On a RMW instruction a “1” is read; write “0” clears the flag; write “1” is ignored
PERROR
DS07-16617-2E
1
indicates occurrence of a protocol error
41
MB91460S Series
*Remark: On a RMW instruction a “1” is read; write “0” clears the flag; write “1” is ignored
READY
1
indicates that AShell is ready to accept outbound transactions
REMOTERST 1
indicates a restart of remote AShell was performed
*Remark: On a RMW instruction a “1” is read; write “0” clears the flag; write “1” is ignored
UPVALID
BYPASS==0
read only Read only status (ap_data_out_valid)
BYPASS==1
0(def) Cleared by SW after successful reception (read) of upstream data
1
DNVALID
Set by HW to mark upstream data as valid (ap_data_out_valid)
BYPASS==0
read only DNVALID is only operational in BYPASS mode (always read 0)
BYPASS==1
0(def) Cleared by HW after successful transfer to AShell
1
TXCFG
RSTRTA
INITRH
Set by SW to mark downstream data as valid (ap_data_in_valid)
0
AShell and PHY running (write protection on APCFG registers)
1(def)
AShell and PHY configuration (possible to change APCFG registers)
0
AShell running Level
1(def)
AShell initialization
0
Remote Handler running Level
1(def)
Remote Handler initialization (no change of TB* and TF* registers)
*Remark: PENDING requests (set while INIT==1) will be started with INIT==0
• CHSTAT0 (Link 0): Address 0720Ch
• CHSTAT1 (Link 1): Address 07218h
31
30
29
28
UPCRC[7:0]
R
CHSTAT0-1
R
R
R
23
22
-
R
14
R
7
42
13
R
6
R
11
R
3
R
4
PLLBAD[7:0]
R
R
UPCRC
0-255
Inbound CRC errors
UPSYNC
0-255
Synchronization losses
PLLBAD
0-255
PLL synchronization losses
-
R0
10
R
R0
9
R
2
R
16
-
R0
12
UPSYNC[7:0]
R
5
17
-
R0
24
R
18
-
R0
25
R
19
-
R0
26
R
20
-
R0
15
R
21
-
R0
R
27
8
R
1
R
0
R
DS07-16617-2E
MB91460S Series
2.1.3.
Channel Watchdog
• CHWDG0 (Link 0): Address 07210h
• CHWDG1 (Link 1): Address 0721Ch
CHWDG
31
30
WDTXIEN
WDRXIEN
R/W
R/W
R0
29
28
-
-
27
WTTX1
R/W
R0
26
WTTX0
R/W
25
WTRX1
R/W
24
WTRX0
R/W
23
22
21
20
19
18
17
16
WDTXIRQ3 WDTXIRQ2 WDTXIRQ1 WDTXIRQ0 WDRXIRQ3 WDRXIRQ2 WDRXIRQ1 WDRXIRQ0
R(RM1)/W
R(RM1)/W
R(RM1)/W
R(RM1)/W
R(RM1)/W
R(RM1)/W
R(RM1)/W
R(RM1)/W
15
14
CNT19
R
WDTXIEN
WDRXIEN
WTTX
WTRX
WDTXIRQ3
WDTXIRQ2
WDTXIRQ1
WDTXIRQ0
WDRXIRQ3
WDRXIRQ2
WDRXIRQ1
DS07-16617-2E
R
R
R
R
R
2
1
CNT6
R
0(def)
Watchdog interrupt for TX is disabled
1
Watchdog interrupt for TX is enabled
0(def)
Watchdog interrupt for RX is disabled
1
Watchdog interrupt for RX is enabled
0
select WDTXIRQ0
1
select WDTXIRQ1
2
select WDTXIRQ2
3
select WDTXIRQ3
0
select WDRXIRQ0
1
select WDRXIRQ1
2
select WDRXIRQ2
3
select WDRXIRQ3
0(def)
interrupt for TX at 219 is not active
1
interrupt for TX at 219 is active
0(def)
interrupt for TX at 216 is not active
1
interrupt for TX at 216 is active
0(def)
interrupt for TX at 214 is not active
1
interrupt for TX at 214 is active
0(def)
interrupt for TX at 213 is not active
1
interrupt for TX at 213 is active
0(def)
interrupt for RX at 219 is not active
1
interrupt for RX at 219 is active
0(def)
interrupt for RX at 218 is not active
1
interrupt for RX at 218 is active
0(def)
interrupt for RX at 217 is not active
1
interrupt for RX at 217 is active
CNT12
R
3
CNT7
8
CNT13
R
4
CNT8
9
CNT14
R
5
CNT9
10
CNT15
R
6
CNT10
11
CNT16
R
7
CNT11
12
CNT17
R
R
13
CNT18
0
CNT5
R
CNT4
R
43
MB91460S Series
WDRXIRQ0
0(def)
interrupt for RX at 216 is not active
1
interrupt for RX at 216 is active
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
CNT
2.1.4.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
upper 16Bit of the 20Bit watchdog freerun timer
Transaction Buffer Control
TBCTRL00 (Transaction Buffer 00): Address 07220h
TBCTRL01 (Transaction Buffer 01): Address 07222h
TBCTRL02 (Transaction Buffer 02): Address 07224h
TBCTRL03 (Transaction Buffer 03): Address 07226h
TBCTRL04 (Transaction Buffer 04): Address 07228h
TBCTRL05 (Transaction Buffer 05): Address 0722Ah
TBCTRL06 (Transaction Buffer 06): Address 0722Ch
TBCTRL07 (Transaction Buffer 07): Address 0723Eh
TBCTRL08 (Transaction Buffer 08): Address 07230h
TBCTRL09 (Transaction Buffer 09): Address 07232h
TBCTRL10 (Transaction Buffer 10): Address 07234h
TBCTRL11 (Transaction Buffer 11): Address 07236h
TBCTRL12 (Transaction Buffer 12): Address 07238h
TBCTRL13 (Transaction Buffer 13): Address 0723Ah
TBCTRL14 (Transaction Buffer 14): Address 0723Ch
TBCTRL15 (Transaction Buffer 15): Address 0723Eh
15
TBCTRL00-15
14
R0
ACTIVE
UNLOCKED
ACTIVE
R0
6
TBAINC
R/W
12
-
R0
7
TBCH
R/W
13
-
R
5
TBACT
R/W
11
10
9
8
UNLOCKED CANCELED
WAITING
PENDING
R(RM1)/W
R(RM1)/W
R
R
4
TBIMD
R/W
3
R0
2
TBDEN
R/W
1
TBIEN
R/W
0
TBIRQ
R(RM1)/W
0
No active data in Transaction Buffer
1
Active data in Transaction Buffer (delivery to AShell requested)
0(def)
No last action on this buffer
1
Last action on this Transaction Buffer was UNLOCK
*Remark: On a RMW instruction a “1” is read; write “0” clears the register write “1” is ignored
CANCELED
0(def)
No last action on this buffer
1
Last action on this Transaction Buffer was a successful CANCEL
*Remark: On a RMW instruction a “1” is read; write “0” clears the register write “1” is ignored
WAITING
0
Not waiting for requested data
1
Transaction Buffer waiting for requested data
*Remark: WAITING will be cleared at reception of requested data in buffer
PENDING
TBCH
44
0
No pending data in Transaction Buffer
1
Pending data in Transaction Buffer (not yet requested delivery to AShell)
0(def)
Transaction Buffer assigned to channel 0
DS07-16617-2E
MB91460S Series
TBAINC
1
Transaction Buffer assigned to channel 1
0(def)
Transaction Buffer Address increment disabled
1
Transaction Buffer Address increment enabled
1. increments address after WR access to TBDATA and transmission of TF
2. increments address after reception of requested TF and RD access to TBDATA,
then autonomous transmission of next read request
*Remark: The addressincrement depends on the setting of TFCTRL.SIZE
TFCTRL.SIZE 00
increment by 1
TFCTRL.SIZE 01
increment by 2
TFCTRL.SIZE 10
increment by 4
*Remark: Address increment is only supported if TBACT = 1.
TBACT
0(def)
Transaction Buffer will be activated by WR access to TBNO
1
Transaction Buffer will be activated by WR access to TBNO or TFDATA
(RD and WR)
TBIMD
TBIEN
TBDEN
TBIRQ
0(def)
Transaction Buffer Interrupt on TB idle (after transaction send)
1
Transaction Buffer Interrupt on TB valid (after read request data reception)
0(def)
Transaction Buffer Interrupt disabled
1
Transaction Buffer Interrupt enabled
0(def)
Transaction Buffer DMA disabled
1
Transaction Buffer DMA enabled
0
Transaction Buffer Interrupt not active
1
Transaction Buffer Interrupt active
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
*Remark: TBIRQ can/will be cleared by the following events:
1. Cleared by SW on write access to TBIRQ flag with data ’0’
2. Cleared by HW if TBACT==1 and read or write access to TBDATA register (both CPU or DMA)
3. Cleared by HW if TBACT==1 and DMA asserts hardware clear signal IIOC
2.1.5.
Transaction Buffer Interrupt
• TBIRQ: Address 07240h
15
TBIRQ[0]
TBIRQ
R
14
TBIRQ[1]
R
R
7
TBIRQ[15:0]
2.1.6.
1
TBIRQ[13]
R
8
TBIRQ[7]
R
2
TBIRQ[12]
R
9
TBIRQ[6]
R
3
TBIRQ[11]
R
10
TBIRQ[5]
R
4
TBIRQ[10]
R
11
TBIRQ[4]
R
5
TBIRQ[9]
R
12
TBIRQ[3]
R
6
TBIRQ[8]
R
13
TBIRQ[2]
0
TBIRQ[14]
R
TBIRQ[15]
R
Read only flags of enabled (TBIEN==1) TBCTRLxx.TBIRQ
Transaction Frame
• TFCTRL00 (Transaction Buffer 00): Address 07250h
• TFCTRL01 (Transaction Buffer 01): Address 07252h
• TFCTRL02 (Transaction Buffer 02): Address 07254h
DS07-16617-2E
45
MB91460S Series
•
•
•
•
•
•
•
•
•
•
•
•
•
TFCTRL03 (Transaction Buffer 03): Address 07256h
TFCTRL04 (Transaction Buffer 04): Address 07258h
TFCTRL05 (Transaction Buffer 05): Address 0725Ah
TFCTRL06 (Transaction Buffer 06): Address 0725Ch
TFCTRL07 (Transaction Buffer 07): Address 0725Eh
TFCTRL08 (Transaction Buffer 08): Address 07260h
TFCTRL09 (Transaction Buffer 09): Address 07262h
TFCTRL10 (Transaction Buffer 10): Address 07264h
TFCTRL11 (Transaction Buffer 11): Address 07266h
TFCTRL12 (Transaction Buffer 12): Address 07268h
TFCTRL13 (Transaction Buffer 13): Address 0726Ah
TFCTRL14 (Transaction Buffer 14): Address 0726Ch
TFCTRL15 (Transaction Buffer 15): Address 0726Eh
7
TFCTRL00-15
RW
OAEN
SZ[1:0]
ERROR
TFAINV
TFDSWP
R/W
6
TFAINV
R/W
5
4
R0
3
ERROR
R
2
SZ[1]
R/W
0
Read
1
Write
0
Offset address disabled
1
Offset address enabled
00
Byte
01
Halfword
10
Word
11
-
0
Normal operation
1
Remote Handler RX bus error occurred
0
Normal mode
1
Address inversion
SZ[0]
R/W
1
OAEN
R/W
0
RW
R/W
In address inversion mode the two least significant bits of the address are inverted
TFDSWP
...
A2
A1
A0
local
...
A2
inv A1
inv A0
remote
0
Normal mode
1
Byte swapping
In swapping mode depending on the configured size the following byte swapping of the data is performed
46
DS07-16617-2E
MB91460S Series
SZ=Word
SZ=Halfword
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3
2
1
0 local
0
1
2
3 remote
3
2
1
0 local
2
3
0
1 remote
TFIDX00 (Transaction Buffer 00): Address 07251h
TFIDX01 (Transaction Buffer 01): Address 07253h
TFIDX02 (Transaction Buffer 02): Address 07255h
TFIDX03 (Transaction Buffer 03): Address 07257h
TFIDX04 (Transaction Buffer 04): Address 07259h
TFIDX05 (Transaction Buffer 05): Address 0725Bh
TFIDX06 (Transaction Buffer 06): Address 0725Dh
TFIDX07 (Transaction Buffer 07): Address 0725Fh
TFIDX08 (Transaction Buffer 08): Address 07261h
TFIDX09 (Transaction Buffer 09): Address 07263h
TFIDX10 (Transaction Buffer 10): Address 07265h
TFIDX11 (Transaction Buffer 11): Address 07267h
TFIDX12 (Transaction Buffer 12): Address 07269h
TFIDX13 (Transaction Buffer 13): Address 0726Bh
TFIDX14 (Transaction Buffer 14): Address 0726Dh
TFIDX15 (Transaction Buffer 15): Address 0726Fh
7
TFIDX00-15
IDX[7:0]
IDX[7]
R/W
6
IDX[6]
R/W
5
IDX[5]
R/W
4
IDX[4]
R/W
3
IDX[3]
R/W
2
IDX[2]
R/W
1
IDX[1]
R/W
0
IDX[0]
R/W
Any number between 0 and 255
*Remark: Index is used for read request. Received data from a read request will be stored in an active
Transaction Buffer with matching index.
If there is no active Transaction Buffer with matching index (e.g. by using UNLOCK), the received data is
discarded.
•
•
•
•
•
•
•
•
•
•
•
•
TFADDR00 (Transaction Buffer 00): Address 07270h
TFADDR01 (Transaction Buffer 01): Address 07274h
TFADDR02 (Transaction Buffer 02): Address 07278h
TFADDR03 (Transaction Buffer 03): Address 0727Ch
TFADDR04 (Transaction Buffer 04): Address 07280h
TFADDR05 (Transaction Buffer 05): Address 07284h
TFADDR06 (Transaction Buffer 06): Address 07288h
TFADDR07 (Transaction Buffer 07): Address 0728Ch
TFADDR08 (Transaction Buffer 08): Address 07290h
TFADDR09 (Transaction Buffer 09): Address 07294h
TFADDR10 (Transaction Buffer 10): Address 07298h
TFADDR11 (Transaction Buffer 11): Address 0729Ch
DS07-16617-2E
47
MB91460S Series
•
•
•
•
TFADDR12 (Transaction Buffer 12): Address 072A0h
TFADDR13 (Transaction Buffer 13): Address 072A4h
TFADDR14 (Transaction Buffer 14): Address 072A8h
TFADDR15 (Transaction Buffer 15): Address 072ACh
31
TFADDR00-15
30
-
29
-
R0
R0
R0
20
R0
-
R0
R0
25
-
R0
21
-
26
-
R0
22
-
27
-
R0
23
-
28
-
24
-
R0
-
R0
R0
19
18
17
16
ADDR[19]
ADDR[18]
ADDR[17]
ADDR[16]
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
ADDR[7]
R/W
ADDR[19:0]
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6
ADDR[6]
R/W
5
ADDR[5]
R/W
4
ADDR[4]
R/W
3
ADDR[3]
R/W
2
ADDR[2]
R/W
1
ADDR[1]
R/W
0
ADDR[0]
R/W
Address in remote system
TFDATA00 (Transaction Buffer 00): Address 072B0h
TFDATA01 (Transaction Buffer 01): Address 072B4h
TFDATA02 (Transaction Buffer 02): Address 072B8h
TFDATA03 (Transaction Buffer 03): Address 072BCh
TFDATA04 (Transaction Buffer 04): Address 072C0h
TFDATA05 (Transaction Buffer 05): Address 072C4h
TFDATA06 (Transaction Buffer 06): Address 072C8h
TFDATA07 (Transaction Buffer 07): Address 072CCh
TFDATA08 (Transaction Buffer 08): Address 072D0h
TFDATA09 (Transaction Buffer 09): Address 072D4h
TFDATA10 (Transaction Buffer 10): Address 072D8h
TFDATA11 (Transaction Buffer 11): Address 072DCh
TFDATA12 (Transaction Buffer 12): Address 072E0h
TFDATA13 (Transaction Buffer 13): Address 072E4h
TFDATA14 (Transaction Buffer 14): Address 072E8h
TFDATA15 (Transaction Buffer 15): Address 076ECh
TFDATA00-15
31
30
29
28
27
26
25
24
DATA[31]
DATA[30]
DATA[29]
DATA[28]
DATA[27]
DATA[26]
DATA[25]
DATA[24]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
DATA[23]
DATA[22]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
DATA[7]
R/W
DATA[31:0]
48
6
DATA[6]
R/W
5
DATA[5]
R/W
4
DATA[4]
R/W
3
DATA[3]
R/W
2
DATA[2]
R/W
1
DATA[1]
R/W
0
DATA[0]
R/W
Payload data
DS07-16617-2E
MB91460S Series
2.1.7.
Event Control
• EVCTRL: Address 072F0h
31
EVCTRL
reserved
R/W0
30
22
-
15
R
R
Bit31
13
R
7
6
R/W
20
LVIRQ
R(RM1)/W
R
5
R/W
R/W
25
-
R0
21
14
26
-
R0
LVIEN
R/W
R0
27
-
R0
23
28
-
R0
MODE
R/W
R/W
29
-
-
R0
19
OFLIEN
R/W
R0
18
OFLIRQ
R(RM1)/W
12
STATUS[7:0]
R
11
4
LEVEL[7:0]
R/W
3
17
EVIEN
R/W
10
R
16
EVIRQ
R(RM1)/W
9
R
2
R/W
24
FRST
R0/W
8
R
1
R/W
0
R/W
reserved Bit
Always write 0 to this bit. The read value is the value written.
FRST
MODE
LVIEN
LVIRQ
0(def)
FIFO in normal operation
1
FIFO pointers are reset pulse (set to 0 after 1 cycle)
0 (def)
level mode On full FIFO new Events are discarded
1
ring mode
0(def)
Level Interrupt disabled
1
Level Interrupt enabled
0(def)
Level Interrupt not active
1
Level Interrupt active (if STATUS>=LEVEL)
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
OFLIEN
OFLIRQ
0(def)
Event Buffer Overflow Interrupt disabled
1
Event Buffer Overflow Interrupt enabled
0(def)
Event Buffer Overflow Interrupt not active
1
Event Buffer Overflow Interrupt active
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
EVIEN
EVIRQ
0(def)
Event Buffer Interrupt disabled
1
Event Buffer Interrupt enabled
0(def)
Event Buffer Interrupt not active
1
Event Buffer Interrupt active
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
Set by hardware, reset by software
STATUS[7:0]
0-128
Current FIFO filling status read only
LEVEL[7:0]
0-128
FIFO interrupt level (128 default)
DS07-16617-2E
49
MB91460S Series
2.1.8.
Eventbuffer
• EVBUF0: Address 072F8h
• EVBUF1: Address 072FCh
31
EVBUF0
30
-
29
-
R0
R0
R/(W)
R/(W)
R/(W)
15
14
-
13
-
R0
7
R/W
31
R/W
30
R/W
29
EVBUF1
R/(W)
R/(W)
23
R/(W)
22
R/(W)
15
R/(W)
21
R/(W)
14
R/(W)
7
R/(W)
R/(W)
13
R/(W)
6
R/(W)
5
R/(W)
9
2
-
1
-
R/W
27
20
EVDATA1[7:0]
R/(W)
R/(W)
19
12
EVDATA2[7:0]
R/(W)
R/(W)
11
4
EVDATA3[7:0]
R/(W)
R/(W)
3
R/(W)
R/(W)
R/(W)
0-255 Holds index number from Remote Handler RX event
Bit8
reserved Bit
16
R/(W)
9
R/(W)
2
EVIDX[7:0]
R/(W)
R/(W)
R/(W)
24
17
10
Holds channel number from Remote Handler RX event
R/W
25
18
EVCH
-
R/W
26
R/(W)
0
-
R/W
28
EVDATA0[7:0]
R/(W)
R/(W)
8
reserved
R/W0
R/W
3
-
16
R/(W)
-
R0
4
-
R/(W)
-
R0
5
-
17
10
-
R0
6
-
R/(W)
11
-
R0
18
24
EVCH
R/(W)
R0
19
12
-
R0
R0
R/(W)
-
R0
20
EVIDX[7:0]
R/(W)
25
-
R0
21
26
-
R0
22
27
-
R0
23
28
-
8
R/(W)
1
R/(W)
0
R/(W)
Always write 0 to this bit. The read value is the value written.
EVDATA0-3
4 bytes of payload data
*Remark: It is recommended to read first EVBUF0 and
A read access to EVBUF0 triggers a retrieve of the current event message from the event buffer fifo and returns
the channel number and event index.
A read access to EVBUF1 returns the data part of the a event message
50
DS07-16617-2E
MB91460S Series
2.1.9.
Apix® configuration
• APCFG0x (Link 0)
• APCFG1x (Link 1)
31
30
29
28
config_byte_1
APCFG00/APCFG10
0
0
R/W
0
R/W
R/W
23
R/W
R/W
R/W
15
0
0
R/W
7
5
0
R/W
R/W
1
R/W
31
30
29
1
1
R/W
1
R/W
R/W
23
21
0
R/W
R/W
R/W
15
0
0
R/W
7
5
1
R/W
R/W
0
R/W
31
30
29
0
0
R/W
0
R/W
R/W
23
21
0
R/W
R/W
15
14
0
R/W
R/W
6
-
5
-
R/W
R/W
30
29
APCFG03/APCFG13
0
R/W
R/W
R/W
23
22
1
21
0
R/W
1
R/W
R/W
15
14
1
13
0
R/W
0
R/W
R/W
7
6
0
R/W
1
5
0
R/W
R/W
9
12
config_byte_shell_3
1
1
R/W
R/W
11
4
config_byte_shell_4
R/W
R/W
3
R/W
1
0
-
-
R/W
R/W
26
25
1
24
1
R/W
0
R/W
R/W
18
17
0/1
16
0
R/W
0
R/W
R/W
10
9
0
8
1
R/W
0
R/W
R/W
2
1
0
R/W
0
R/W
2
R/W
19
8
0
-
20
config_byte_shell_2
0
0
R/W
R/W
R/W
10
R/W
27
0
R/W
0
28
config_byte_shell_1
0
0
R/W
R/W
16
1
R/W
R/W
R/W
17
0
-
24
0
R/W
18
3
-
R/W
31
4
-
R/W
0
11
R/W
12
config_byte_11
0
0
R/W
0
R/W
7
R/W
13
1
25
1
R/W
19
0
R/W
R/W
R/W
26
0
20
config_byte_10
0
0
R/W
0
0
R/W
27
0
R/W
22
0
0
1
0
R/W
28
config_byte_9
APCFG02/APCFG12
R/W
2
0
R/W
8
0
R/W
3
1
R/W
9
0
R/W
4
config_byte_8
0
R/W
10
0
R/W
16
0
R/W
11
0
R/W
6
0
0
R/W
17
0
R/W
12
config_byte_7
R/W
18
0
R/W
13
24
0
R/W
19
0
R/W
14
0
R/W
0
25
0
R/W
20
config_byte_6
0
R/W
26
0
R/W
0
0
R/W
27
0
R/W
22
0
1
1
0
R/W
28
config_byte_5
APCFG01/APCFG11
R/W
2
0
R/W
8
0
R/W
3
0
R/W
9
0
R/W
4
config_byte_4
0
R/W
10
0
R/W
16
0
R/W
11
0
R/W
6
1
0
R/W
17
0
R/W
12
config_byte_3
R/W
18
0
R/W
13
24
0
R/W
19
0
R/W
14
0
R/W
1
25
0
R/W
20
config_byte_2
1
26
0
R/W
21
0
27
0
R/W
22
0
0
0
0
R/W
0
R/W
AShell and PHY configuration.
DS07-16617-2E
51
MB91460S Series
2.1.10. Module ID
• MODULEID: Address 07320h
MODULEID[31:0]: Version of the APIX® controller
3. APIX¼® PHY Configuration
3.1.
Powerdown
Configuration Vector:
Bit
3.2.
Default
31
0
29
0
power down serializer and output driver (diff amp)
1: power down
0: power up
28
0
power down upstream path
1: power down
0: power up
Nominal Current
Bit
Default
19
0
18
0
17
0
16
0
15
0
14
0
APCFG 01
Description
nominal current setting (64 steps)
000000: min (0 mA - power down output driver)
111111: max
Pre-emphasis
Configuration Vector:
52
Description
global power down
(upstream, downstream and PLL)
1: power down
0: power up
Configuration Vector:
3.3.
APCFG 00
Bit
Default
26
0
25
0
24
0
APCFG 00
Description
pre-emphasis configuration: reduce output current (pre-emphasis) after N
equal serial bits (N = 0..7)
DS07-16617-2E
MB91460S Series
Configuration Vector:
3.4.
Bit
Default
13
0
12
0
11
0
10
0
9
0
8
0
APCFG 01
Description
pre-emphasis current setting (64 steps)
000000: min (0 mA - power down output driver)
111111: max
Sampling Offset
Configuration Vector:
3.5.
APCFG 00
Bit
Default
Description
11
0
10
0
9
0
8
0
upstream sampling point configuration
0000: optimum sampling point when operating in 62.50 Mbit/s mode
0010: optimum sampling point when operating in 41.67 Mbit/s or 31.25 Mbit/s
mode
0100: optimum sampling point when operating in 20.83 Mbit/s mode
Charge Pump Control
Configuration Vector:
Bit
Default
23
1
22
0
21
0
20
0
DS07-16617-2E
APCFG 01
Description
charge pump current control
53
MB91460S Series
4. DMA transfer request
To request a DMA transfer by a Transaction Buffer, please configure the transfer request source in DMACAx as
follows.
IS
10000
EIS(DDNO)
1010
RN
160
Function
Transfer stop request
®
available
®
APIX Transaction Buffer 0
10001
1010
161
APIX Transaction Buffer 1
available
10010
1010
162
APIX® Transaction Buffer 2
available
10011
1010
163
APIX® Transaction Buffer 3
available
10100
1010
164
®
available
®
APIX Transaction Buffer 4
10101
1010
165
APIX Transaction Buffer 5
available
10110
1010
166
APIX® Transaction Buffer 6
available
10111
1010
167
APIX® Transaction Buffer 7
available
11000
1010
168
®
available
®
APIX Transaction Buffer 8
11001
1010
169
APIX Transaction Buffer 9
available
11010
1010
170
APIX® Transaction Buffer 10
available
11011
1010
171
APIX® Transaction Buffer 11
available
11100
1010
172
®
available
®
APIX Transaction Buffer 12
11101
1010
173
APIX Transaction Buffer 13
available
11110
1010
174
APIX® Transaction Buffer 14
available
11111
1010
175
APIX® Transaction Buffer 15
available
54
DS07-16617-2E
MB91460S Series
5. Automotive Interconnect Pins
The AIC Pins also serve as general ports.
Pin name
Pin function
RCK0
AIC uplink clock
of Apix® link0
I/O format
Pull-up
Standby
Pull-down
control
Setting required to use
Set port function mode
PFR28: Bit0 = 1,
EPFR28: Bit0 = 1
Set port function mode
PFR28: Bit1 = 1,
RDA00
EPFR28: Bit1 = 1
AIC uplink data
of Apix® link0
Set port function mode
RDA01
PFR28: Bit2 = 1,
EPFR28: Bit2 = 1
Set port function mode
PFR28: Bit5 = 1,
TDA00
AIC downlink
data of Apix®
link0
EPFR28: Bit5 = 1
Set port function mode
TDA01
PFR28: Bit6 = 1,
EPFR28: Bit6 = 1
TCLI0
AIC downlink
clock of Apix®
link0
AIC uplink clock
of Apix® link1
PFR28: Bit7 = 1,
CMOS hysteresis,
CMOS Automotive
RCK1
Set port function mode
CMOS output and
hysteresis,
TTL input
Programmable
Provided
EPFR28: Bit7 = 1
Set port function mode
PFR17: Bit0 = 1,
EPFR17: Bit0 = 1
Set port function mode
PFR17: Bit1 = 1,
RDA10
AIC uplink data
of Apix® link1
RDA11
EPFR17: Bit1 = 1
Set port function mode
PFR17: Bit2 = 1,
EPFR17: Bit2 = 1
Set port function mode
TDA10
PFR17: Bit5 = 1,
AIC downlink
data of Apix®
link1
TDA11
EPFR17: Bit5 = 1
Set port function mode
PFR17: Bit6 = 1,
EPFR17: Bit6 = 1
TCLI1
DS07-16617-2E
AIC downlink
clock of Apix®
link1
Set port function mode
PFR17: Bit7 = 1,
EPFR17: Bit7 = 1
55
MB91460S Series
6. USECASES
6.1.
Communication over APIX® link
APIX® RX
MB91F467SA
6.1.1.
Downlink over Pixelchannel
Downlink over Pixelchannel is provided by default configuration. Please configure the PHY according to Chapter
“APIX¼® PHY Configuration” on page 52
6.1.2.
Downlink over Sidebandchannel
Register
Bit
Default
Value
APCFG01
31
1
0
6.2.
6.2.1.
Description
0: disable data mode / enable pixel stream mode
1: enable data mode / disable pixel stream mode
Communication over Automotive Interconnect to external AShell
1Bit Datawidth
D
C
MB91F467SA
APIX® RX
embedded TX
D
C
Register
Bit
Default
Value
APCFGn1
31
1
0
0: disable data mode / enable pixel stream mode
1: enable data mode / disable pixel stream mode
APCFGn1
29
1
0
1: enable core clock of APIX® PHY
0: disable
APCFGn3
23
1
0
1: sbup_data[1:0]
0: sbup_data[0]
APCFGn3
21
1
0
1: sbdown_data[1:0]
0: sbdown_data[0]
1
AShell: connect internal Ashell to external APIX® PHY
through GPIO interface
1: enable
0: disable
APCFGn3
56
18
0
Description
DS07-16617-2E
MB91460S Series
6.2.2.
2Bit Datawidth
D[1:0]
C
MB91F467SA
APIX® RX
embedded TX
D [1:0]
C
Register
Bit
Default
Value
APCFGn1
31
1
0
0: disable data mode / enable pixel stream mode
1: enable data mode / disable pixel stream mode
APCFGn1
29
1
0
1: enable core clock of APIX® PHY
0: disable
1
AShell: connect internal Ashell to external APIX® PHY
through GPIO interface
1: enable
0: disable
APCFGn3
6.3.
18
0
Description
Communication over Automotive Interconnect to external PHY
DACL SBDOWN DATA[1]
D
SBDOWN DATA[0]
INAP 125T24 /
embedded TX
MB91F467SA
APIX® RX
DACL SBUP_DATA[1]
D
DS07-16617-2E
SBUP_DATA[0]
57
MB91460S Series
Register
Bit
Default
Value
APCFGn1
31
1
0
0: disable data mode / enable pixel stream mode
1: enable data mode / disable pixel stream mode
APCFGn1
29
1
0
1: enable core clock of APIX® PHY
0: disable
APCFGn3
22
0
1
AShell: validate sbup_data with
1: sbup_data[1]
0: sbup_valid
APCFGn3
20
0
1
APCFGn3
19
0
0
APCFGn3
APCFGn3
6.4.
18
0
2
0
1
0
0
0
30
0
29
1
28
0
27
0
26
1
25
1
24
0
1
t.b.d.
Description
AShell: generate sbdown clock and transmit as
sbdown_data[1]
11: disable
10: with use of internal counter (asynchronous to core_clk
of APIX® PHY)
01: with use of sbdown_trigger (synchronous to core_clk of
APIX® PHY)
00: disable
AShell: connect internal Ashell to external APIX® PHY
through GPIO interface
1: enable
0: disable
AShell: configures cycle time of sbdown clock (multiples of
Ashell core clock) when sbdown_data are
asynchronous (sbdown_data[1] is used as sbdown clock)
or cfg_spi_over_sb is enabled
0x0B: recommended minimum (no low bandwidth mode,
AShell and APIX® PHY operate at same core
clock frequency)
0x14: recommended minimum (low bandwidth mode 2,
AShell and APIX® PHY operate at 62.5 MHz)
0x26: recommended minimum (low bandwidth mode 1,
AShell and APIX® PHY operate at 62.5 MHz)
Caution
Up to now only the usecases “Downlink over Pixelchannel” on page 56 and “Communication over Automotive
Interconnect to external PHY” on page 57 are guaranteed.
58
DS07-16617-2E
MB91460S Series
■ MEMORY SPACE
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access : 000H to 0FFH
Half word access : 000H to 1FFH
Word data access : 000H to 3FFH
DS07-16617-2E
59
MB91460S Series
■ MEMORY MAPS
1. MB91F467SA
MB91F467SA
00000000H
00000400H
00001000H
I/O (direct addressing area)
I/O
DMA
00002000H
00004000H
Flash-Cache (8 KBytes)
00006000H
00007000H
Flash memory control
00008000H
0000B000H
0000C000H
Boot ROM (4 Kbytes)
CAN
0000D000H
00028000H
00030000H
D-RAM (0 wait, 32 Kbytes)
ID-RAM (32 Kbytes)
00038000H
00040000H
Flash memory (1088 Kbytes)
00150000H
00180000H
External bus area
00500000H
External data bus
FFFFFFFFH
Note:
60
Access prohibited areas
DS07-16617-2E
MB91460S Series
■ I/O MAP
1. MB91F467SA
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
port data register
Read/write attribute
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1
becomes the MSB side of the data.)
Note : Initial values of register bits are represented as follows:
“ 1 ” : Initial value “ 1 ”
“ 0 ” : Initial value “ 0 ”
“ X ” : Initial value “ undefined ”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
DS07-16617-2E
61
MB91460S Series
Address
Register
+0
+1
000000H
PDR00 [R/W]
XXXXXXXX
PDR01 [R/W]
XXXXXXXX
000004H
Reserved
PDR05 [R/W]
XXXXXXXX
PDR06 [R/W]
XXXXXXXX
PDR07 [R/W]
XXXXXXXX
000008H
PDR08 [R/W]
X - - X - - XX
PDR09 [R/W]
- - - - XXXX
PDR10 [R/W]
- - - - X - XX
Reserved
PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
- - - - XXXX
00000CH
+2
Reserved
+3
Reserved
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXXXXXX
PDR18 [R/W]
- XXX - XXX
PDR19 [R/W]
- XXX - XXX
000014H
PDR20 [R/W]
- XXX - XXX
Reserved
PDR22 [R/W]
XXXX - X - X
PDR23 [R/W]
- X - XXXXX
000018H
PDR24 [R/W]
XXXXXXXX
00001CH
PDR28 [R/W]
XXXXXXXX
000024H
to
00002CH
Block
R-bus
Port Data
Register
Reserved
PDR29 [R/W]
XXXXXXXX
Reserved
Reserved
000030H
EIRR0 [R/W]
XXXXXXXX
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External interrupt
(INT 0 to INT 7)
000034H
EIRR1 [R/W]
XXXXXXXX
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External interrupt
(INT 8 to INT 15)
000038H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
RBSYNC*1
Delay Interrupt
00003CH
to
00004CH
Reserved
000050H
SCR02 [R/W, W] SMR02 [R/W, W] SSR02 [R/W, R]
00000000
00000000
00001000
000054H
ECCR02
[R/W, R, W]
-00000XX
000058H
00005CH
ESCR02 [R/W]
00000X00
ECCR03
[R/W, R, W]
-00000XX
LIN-USART
2
Reserved
SCR03 [R/W, W] SMR03 [R/W, W] SSR03 [R/W, R]
00000000
00000000
00001000
ESCR03 [R/W]
00000X00
RDR02/TDR02
[R/W]
00000000
RDR03/TDR03
[R/W]
00000000
LIN-USART
3
Reserved
(Continued)
62
DS07-16617-2E
MB91460S Series
Register
Address
000060H
000064H
000068H
00006CH
000070H
000074H
000078H
00007CH
+0
+1
+2
+3
SCR04 [R/W, W] SMR04 [R/W, W] SSR04 [R/W, R]
00000000
00000000
00001000
RDR04/TDR04
[R/W]
00000000
ECCR04
[R/W, R, W]
-00000XX
FCR04 [R/W]
0001 - 000
ESCR04 [R/W]
00000X00
FSR04 [R]
- - - 00000
SCR05 [R/W, W] SMR05 [R/W, W] SSR05 [R/W, R]
00000000
00000000
00001000
RDR05/TDR05
[R/W]
00000000
ECCR05
[R/W, R, W]
-00000XX
FCR05 [R/W]
0001 - 000
ESCR05 [R/W]
00000X00
FSR05 [R]
- - - 00000
SCR06 [R/W, W] SMR06 [R/W, W] SSR06 [R/W, R]
00000000
00000000
00001000
RDR06/TDR06
[R/W]
00000000
ECCR06
[R/W, R, W]
-00000XX
FCR06 [R/W]
0001 - 000
ESCR06 [R/W]
00000X00
FSR06 [R]
- - - 00000
SCR07 [R/W, W] SMR07 [R/W, W] SSR07 [R/W, R]
00000000
00000000
00001000
RDR07/TDR07
[R/W]
00000000
ECCR07
[R/W, R, W]
-00000XX
FCR07 [R/W]
0001 - 000
ESCR07 [R/W]
00000X00
000080H
FSR07 [R]
- - - 00000
Block
LIN-USART
4
with FIFO
LIN-USART
5
with FIFO
LIN-USART
6
with FIFO
LIN-USART
7
with FIFO
Reserved
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
BGR105 [R/W]
00000000
BGR005 [R/W]
00000000
00008CH
BGR106 [R/W]
00000000
BGR006 [R/W]
00000000
BGR107 [R/W]
00000000
BGR007 [R/W]
00000000
000090H
to
0000CCH
Baud rate
Generator
LIN-USART
2 to 7
Reserved
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8H
Reserved
IDAR0 [R/W]
00000000
ICCR0 [R/W]
- 0011111
Reserved
I2C 0
(Continued)
DS07-16617-2E
63
MB91460S Series
Address
Register
+0
+1
+2
+3
0000DCH
IBCR1 [R/W]
00000000
IBSR1 [R]
00000000
ITBAH1[R/W]
- - - - - - 00
ITBAL1 [R/W]
00000000
0000E0H
ITMKH1 [R/W]
00 - - - - 11
ITMKL1 [R/W]
11111111
ISMK1 [R/W]
01111111
ISBA1 [R/W]
- 0000000
0000E4H
Reserved
IDAR1 [R/W]
00000000
ICCR1 [R/W]
- 0011111
Reserved
0000E8H
to
0000FCH
Block
I2C 1
Reserved
000100H
GCN10 [R/W]
00110010 00010000
Reserved
GCN20 [R/W]
- - - - 0000
PPG Control
0 to 3
000104H
GCN11 [R/W]
00110010 00010000
Reserved
GCN21 [R/W]
- - - - 0000
PPG Control
4 to 7
000108H
GCN12 [R/W]
00110010 00010000
Reserved
GCN22 [R/W]
- - - - 0000
PPG Control
8 to 11
00010CH
Reserved
000110H
PTMR00 [R]
11111111 11111111
000114H
PDUT00 [W]
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R]
11111111 11111111
00011CH
PDUT01 [W]
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R]
11111111 11111111
000124H
PDUT02 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R]
11111111 11111111
00012CH
PDUT03 [W]
XXXXXXXX XXXXXXXX
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
PCSR00 [W]
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
0000000 -
PCNL00 [R/W]
000000 - 0
PCSR01 [W]
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
0000000 -
PCNL01 [R/W]
000000 - 0
PCSR02 [W]
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
0000000 -
PCNL02 [R/W]
000000 - 0
PCSR03 [W]
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
0000000 -
PCNL03 [R/W]
000000 - 0
PCSR04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
PPG 0
PPG 1
PPG2
PPG3
PPG 4
PPG 5
(Continued)
64
DS07-16617-2E
MB91460S Series
Address
Register
+0
+1
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
PTMR08 [R]
11111111 11111111
000154H
PDUT08 [W]
XXXXXXXX XXXXXXXX
000158H
PTMR09 [R]
11111111 11111111
00015CH
PDUT09 [W]
XXXXXXXX XXXXXXXX
000160H
PTMR10 [R]
11111111 11111111
000164H
PDUT10 [W]
XXXXXXXX XXXXXXXX
000168H
PTMR11 [R]
11111111 11111111
00016CH
PDUT11 [W]
XXXXXXXX XXXXXXXX
000170H
P0TMCSRH
[R/W]
- 0 - 000 - 0
+2
+3
PCSR06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
PCSR08 [W]
XXXXXXXX XXXXXXXX
PCNH08 [R/W]
0000000 -
PCNL08 [R/W]
000000 - 0
PCSR09 [W]
XXXXXXXX XXXXXXXX
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
PCSR10 [W]
XXXXXXXX XXXXXXXX
PCNH10 [R/W]
0000000 -
PCNL10 [R/W]
000000 - 0
PCSR11 [W]
XXXXXXXX XXXXXXXX
P0TMCSRL
[R/W]
- - - 00000
PCNH11 [R/W]
0000000 -
PCNL11 [R/W]
000000 - 0
P1TMCSRH
[R/W]
- 0 - 000 - 0
P1TMCSRL
[R/W]
- - - 00000
000174H
P0TMRLR [W]
XXXXXXXX XXXXXXXX
P0TMR [R]
XXXXXXXX XXXXXXXX
000178H
P1TMRLR [W]
XXXXXXXX XXXXXXXX
P1TMR [R]
XXXXXXXX XXXXXXXX
PPG 6
PPG 7
PPG 8
PPG 9
PPG 10
PPG 11
Pulse
Frequency
Modulator
Reserved
00017CH
000180H
Block
Reserved
ICS01 [R/W]
00000000
Reserved
ICS23 [R/W]
00000000
000184H
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
Input
Capture
0 to 3
(Continued)
DS07-16617-2E
65
MB91460S Series
Address
Register
+0
+1
+2
+3
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
000198H
SGCRH [R/W]
0000 - - 00
00019CH
SGAR [R/W]
00000000
0001A0H
SGCRL [R/W]
- - 0 - - 000
Reserved
ADERH [R/W]
00000000 00000000
SGFR [R/W, R]
XXXXXXXX XXXXXXXX
SGTR [R/W]
XXXXXXXX
SGDR [R/W]
XXXXXXXX
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
0001ACH
Reserved
ACSR0 [R/W]
- 11XXX00
TMRLR0 [W]
XXXXXXXX XXXXXXXX
0001B4H
Reserved
0001B8H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
0001BCH
Reserved
0001C0H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
Reserved
0001C8H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
Reserved
Output
Compare
0 to 3
Sound
Generator
ADERL [R/W]
00000000 00000000
0001A4
0001B0H
Block
A/D
Converter
Reserved
Alarm Comparator 0
TMR0 [R]
XXXXXXXX XXXXXXXX
Reload Timer 0
TMCSRH0
[R/W]
- - - 00000
TMCSRL0
[R/W]
0 - 000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSRH1
[R/W]
- - - 00000
TMCSRL1
[R/W]
0 - 000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W]
- - - 00000
TMCSRL2
[R/W]
0 - 000000
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W]
- - - 00000
TMCSRL3
[R/W]
0 - 000000
(PPG 0, PPG 1)
Reload Timer 1
(PPG 2, PPG 3)
Reload Timer 2
(PPG 4, PPG 5)
Reload Timer 3
(PPG 6, PPG 7)
(Continued)
66
DS07-16617-2E
MB91460S Series
Address
Register
+0
+1
0001D0H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
0001D4H
Reserved
0001D8H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
0001DCH
Reserved
0001E0H
TMRLR6 [W]
XXXXXXXX XXXXXXXX
0001E4H
Reserved
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
0001ECH
Reserved
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
+2
+3
TMR4 [R]
XXXXXXXX XXXXXXXX
TMCSRH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
TMR5 [R]
XXXXXXXX XXXXXXXX
TMCSRH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
TMR6 [R]
XXXXXXXX XXXXXXXX
TMCSRH6
[R/W]
- - - 00000
TMCSRL6
[R/W]
0 - 000000
TMR7 [R]
XXXXXXXX XXXXXXXX
TMCSRH7
[R/W]
- - - 00000
TMCSRL7
[R/W]
0 - 000000
Reserved
TCCS0 [R/W]
00000000
Block
Reload Timer 4
(PPG 8, PPG 9)
Reload Timer 5
(PPG 10, PPG 11)
Reload Timer 6
(PPG 12, PPG 13)
Reload Timer 7
(PPG 14, PPG 15)
(A/D Converter)
Free Running
Timer 0
(ICU 0, ICU 1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free Running
Timer 1
(ICU 2, ICU 3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free Running
Timer 2
(OCU 0, OCU 1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free Running
Timer 3
(OCU 2, OCU 3)
(Continued)
DS07-16617-2E
67
MB91460S Series
Address
Register
+0
+1
+2
+3
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
00 - - 0000
Reserved
Reserved
ICS045 [R/W]
00000000
Reserved
ICS67 [R/W]
00000000
0002D4H
IPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8H
IPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCH
to
0002ECH
0002F0H
DMAC
Reserved
000244H
to
0002CCH
0002D0H
Block
Input
Capture
4 to 7
Reserved
TCDT4 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS4 [R/W]
00000000
Free Running
Timer 4
(ICU 4, ICU 5)
(Continued)
68
DS07-16617-2E
MB91460S Series
Register
Address
+0
+1
TCDT5 [R/W]
XXXXXXXX XXXXXXXX
0002F4H
+2
+3
Reserved
TCCS5 [R/W]
00000000
Block
Free Running
Timer 5
(ICU 6, ICU 7)
0002F8H
TCDT6 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS6 [R/W]
00000000
Free Running
Timer 6
0002FCH
TCDT7 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS7 [R/W]
00000000
Free Running
Timer 7
000300H
UDRC1 [W]
00000000
UDRC0 [W]
00000000
UDCR1 [R]
00000000
UDCR0 [R]
00000000
000304H
UDCCH0 [R/W]
00000000
UDCCL0 [R/W]
00000000
Reserved
UDCS0 [R/W]
00000000
000308H
UDCCH1 [R/W]
00000000
UDCCL1[R/W]
00000000
Reserved
UDCS1 [R/W]
00000000
00030CH
Up/Down
Counter
0/1
Reserved
000310H
UDRC3 [W]
00000000
UDRC2 [W]
00000000
UDCR3 [R]
00000000
UDCR2 [R]
00000000
000314H
UDCCH2 [R/W]
00000000
UDCCL2 [R/W]
00000000
Reserved
UDCS2 [R/W]
00000000
000318H
UDCCH3 [R/W]
00000000
UDCCL3 [R/W]
00000000
Reserved
UDCS3 [R/W]
00000000
00031CH
000320H
Up/Down
Counter
2/3
Reserved
GCN13 [R/W]
00110010 00010000
000324H
to
00032CH
Reserved
GCN23 [R/W]
- - - - 0000
PPG Control
12 to 15
Reserved
000330H
PTMR12 [R]
11111111 11111111
000334H
PDUT12 [W]
XXXXXXXX XXXXXXXX
000338H
PTMR13 [R]
11111111 11111111
00033CH
PDUT13 [W]
XXXXXXXX XXXXXXXX
000340H
PTMR14 [R]
11111111 11111111
000344H
PDUT14 [W]
XXXXXXXX XXXXXXXX
PCSR12 [W]
XXXXXXXX XXXXXXXX
PCNH12 [R/W]
0000000 -
PCNL12 [R/W]
000000 - 0
PCSR13 [W]
XXXXXXXX XXXXXXXX
PCNH13 [R/W]
0000000 -
PCNL13 [R/W]
000000 - 0
PCSR14 [W]
XXXXXXXX XXXXXXXX
PCNH14 [R/W]
0000000 -
PCNL14 [R/W]
000000 - 0
PPG 12
PPG 13
PPG 14
(Continued)
DS07-16617-2E
69
MB91460S Series
Address
Register
+0
+1
000348H
PTMR15 [R]
11111111 11111111
00034CH
PDUT15 [W]
XXXXXXXX XXXXXXXX
000350H
to
000364H
+2
+3
PCSR15 [W]
XXXXXXXX XXXXXXXX
PCNH15 [R/W]
0000000 -
PCNL15 [R/W]
000000 - 0
PPG 15
Reserved
000368H
IBCR2 [R/W]
00000000
IBSR2 [R]
00000000
ITBAH2 [R/W]
- - - - - - 00
ITBAL2 [R/W]
00000000
00036CH
ITMKH2 [R/W]
00 - - - - 11
ITMKL2 [R/W]
11111111
ISMK2 [R/W]
01111111
ISBA2 [R/W]
- 0000000
000370H
Reserved
IDAR2 [R/W]
00000000
ICCR2 [R/W]
- 0011111
Reserved
000374H
to
00038CH
000390H
Block
I2C 2
Reserved
ROMS [R]
11111111 00000000
Reserved
000394H
to
0003ECH
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
ROM Select Register
Bit Search Module
(Continued)
70
DS07-16617-2E
MB91460S Series
Register
Address
+0
+1
+2
+3
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474H
ICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478H
ICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
ICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXX - 00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
---- 0000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
Block
Interrupt
Controller
Clock
Control
Reserved
000488H
00048CH
PLLDIVM [R/W]
- - - - 0000
000490H
PLLCTRL [R/W]
- - - - 0000
PLLDIVN [R/W]
- - 000000
PLLDIVG [R/W]
- - - - 0000
PLLDIVG [W]
00000000
PLL Interface
Reserved
(Continued)
DS07-16617-2E
71
MB91460S Series
Address
Register
+0
+1
+2
+3
000494H
OSCC1 [R/W]
- - - - - 010
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
OSCS2 [R/W]
00001111
000498H
PORTEN [R/W]
- - - - - - 00
Main/Sub
Oscillator
Control
Port Input Enable
Control
Reserved
00049CH
Block
Reserved
WTCER [R/W]
- - - - - - 00
WTCR [R/W]
00000000 000 - 00 - 0
0004A0H
Reserved
0004A4H
Reserved
0004A8H
WTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000
Reserved
0004ACH
CSVTR [R/W]
- - - 00010
CSVCR [R/W]
00011100
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
CMT1 [R/W]
00000000 1 - - - 0000
Reserved
CMCR [R/W]
- 001 - - 00
CMT2 [R/W]
- - 000000 - - 000000
Real Time Clock
(Watch Timer)
ClockSupervisor / Selector /
Monitor
Calibration of Sub
Clock
Clock
Modulator
0004C0H
CANPRE [R/W]
- - 000000
CANCKD [R/W]
- - - - - - 00*3
0004C4H
LVSEL [R/W]
00000111
LVDET [R/W]
0000 0 - 00
HWWDE [R/W]
- - - - - - 00
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
Main-/Sub-Oscillation
Stabilization Timer
0004CCH
OSCCR [R/W]
-------0
Reserved
REGSEL [R/W]
- - 000100
REGCTR [R/W]
- - - 0 - - 00
Main- Oscillation
Standby Control
Main-/Subregulator
Control
0004D0H
to
00063CH
Reserved
CAN Clock Control
HWWD [R/W, W] Low Voltage Detection/
00011000
Hardware Watchdog
Reserved
(Continued)
72
DS07-16617-2E
MB91460S Series
Register
Address
+0
+1
+2
+3
000640H
ASR0 [R/W]
00000000 00000000
ACR0 [R/W]
1111**00 00100000*4
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX
ACR1 [R/W]
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W]
XXXXXXXX XXXXXXXX
ACR3 [R/W]
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W]
XXXXXXXX XXXXXXXX
ACR4 [R/W]
XXXXXXXX XXXXXXXX
000654H
ASR5 [R/W]
XXXXXXXX XXXXXXXX
ACR5 [R/W]
XXXXXXXX XXXXXXXX
000658H
ASR6 [R/W]
XXXXXXXX XXXXXXXX
ACR6 [R/W]
XXXXXXXX XXXXXXXX
00065CH
ASR7 [R/W]
XXXXXXXX XXXXXXXX
ACR7 [R/W]
XXXXXXXX XXXXXXXX
000660H
AWR0 [R/W]
01001111 11111011
AWR1 [R/W]
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W]
XXXXXXXX XXXXXXXX
AWR3 [R/W]
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W]
XXXXXXXX XXXXXXXX
AWR5 [R/W]
XXXXXXXX XXXXXXXX
00066CH
AWR6 [R/W]
XXXXXXXX XXXXXXXX
AWR7 [R/W]
XXXXXXXX XXXXXXXX
000670H
MCRA [R/W]
XXXXXXXX
000674H
000678H
MCRB [R/W]
XXXXXXXX
Block
External Bus
Reserved
Reserved
IORW0 [R/W]
XXXXXXXX
00067CH
IORW1 [R/W]
XXXXXXXX
Reserved
Reserved
000680H
CSER [R/W]
00000001
CHER [R/W]
11111111
000684H
RCRH [R/W]
00XXXXXX
RCRL [R/W]
XXXX0XXX
000688H
to
0007F8H
0007FCH
IORW2 [R/W]
XXXXXXXX
Reserved
TCR [R/W]
0000**** *5
Reserved
Reserved
Reserved
MODR [W]
XXXXXXXX
Reserved
Mode Register
(Continued)
DS07-16617-2E
73
MB91460S Series
Address
Register
+0
+1
000800H
to
000CFCH
+2
+3
Reserved
000D00H
PDRD00 [R]
XXXXXXXX
PDRD01 [R]
XXXXXXXX
000D04H
Reserved
PDRD05 [R]
XXXXXXXX
PDRD06 [R]
XXXXXXXX
PDRD07 [R]
XXXXXXXX
000D08H
PDRD08 [R]
X - - X - - XX
PDRD09 [R]
- - - - XXXX
PDRD10 [R]
- - - - X - XX
Reserved
PDRD14 [R]
XXXXXXXX
PDRD15 [R]
- - - - XXXX
000D0CH
Reserved
Reserved
000D10H
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXXXXXX
PDRD18 [R]
- XXX - XXX
PDRD19 [R]
- XXX - XXX
000D14H
PDRD20 [R]
- XXX - XXX
Reserved
PDRD22 [R]
XXXX - X - X
PDRD23 [R]
-X - XXXXX
000D18H
PDRD24 [R]
XXXXXXXX
Reserved
Reserved
000D1CH
PDRD28 [R]
XXXXXXXX
PDRD29 [R]
XXXXXXXX
Reserved
000D20H
to
000D3CH
R-bus
Port Data
Direct Read
Register
Reserved
000D40H
DDR00 [R/W]
00000000
DDR01 [R/W]
00000000
000D44H
Reserved
DDR05 [R/W]
00000000
DDR06 [R/W]
00000000
DDR07 [R/W]
00000000
000D48H
DDR08 [R/W]
0 - - 0 - -00
DDR09 [R/W]
- - - - 0000
DDR10 [R/W]
- - - - 0 - 00
Reserved
000D4CH
Reserved
Reserved
DDR14 [R/W]
00000000
DDR15 [R/W]
- - - - 0000
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
00000000
DDR18 [R/W]
- 000 - 000
DDR19 [R/W]
- 000 - 000
000D54H
DDR20 [R/W]
- 000 - 000
Reserved
DDR22 [R/W]
0000 - 0 - 0
DDR23 [R/W]
- 0 - 00000
000D58H
DDR24 [R/W]
00000000
Reserved
Reserved
Reserved
000D5CH
DDR28 [R/W]
00000000
DDR29 [R/W]
00000000
000D60H
to
000D7CH
Block
Reserved
R-bus
Port Direction
Register
Reserved
Reserved
(Continued)
74
DS07-16617-2E
MB91460S Series
Register
Address
+0
+1
000D80H
PFR00 [R/W]
00000000
PFR01 [R/W]
00000000
000D84H
Reserved
PFR05 [R/W]
00000000
PFR06 [R/W]
00000000
PFR07 [R/W]
00000000
000D88H
PFR08 [R/W]
0 - - 0 - - 00
PFR09 [R/W]
- - - - 0000
PFR10 [R/W]
- - - - 0 - 00
Reserved
PFR14 [R/W]
00000000
PFR15 [R/W]
- - - - 0000
000D8CH
+2
Reserved
+3
Block
Reserved
000D90H
PFR16 [R/W]
00000000
PFR17 [R/W]
00000000
PFR18 [R/W]
- 000 - 000
PFR19 [R/W]
- 000 - 000
000D94H
PFR20 [R/W]
- 000 - 000
Reserved
PFR22 [R/W]
0000 - 0 - 0
PFR23 [R/W]
- 0 - 00000
000D98H
PFR24 [R/W]
00000000
000D9CH
PFR28 [R/W]
00000000
R-bus
Port Function
Register
Reserved
PFR29 [R/W]
00000000
000DA0H
to
000DBCH
Reserved
Reserved
000DC0H
EPFR00 [R/W]
--------
EPFR01 [R/W]
--------
000DC4H
Reserved
EPFR05 [R/W]
--------
EPFR06 [R/W]
--------
EPFR07 [R/W]
--------
000DC8H
EPFR08 [R/W]
--------
EPFR09 [R/W]
--------
EPFR10 [R/W]
-------0
Reserved
EPFR14 [R/W]
00000000
EPFR15 [R/W]
- - - - 0000
000DCCH
Reserved
Reserved
000DD0H
EPFR16 [R/W]
0000 - - - -
EPFR17 [R/W]
- 000 - 000
EPFR18 [R/W]
- 000 - 000
EPFR19 [R/W]
- 0- - - 0- -
000DD4H
EPFR20 [R/W]
- 000 - 000
Reserved
EPFR22 [R/W]
--------
EPFR23 [R/W]
--------
000DD8H
EPFR24 [R/W]
--------
000DDCH
EPFR28 [R/W]
- 000 - 000
000DE0H
to
000DFCH
R-bus Extra
Port Function
Register
Reserved
EPFR29 [R/W]
--------
Reserved
Reserved
(Continued)
DS07-16617-2E
75
MB91460S Series
Address
Register
+0
+1
000E00H
PODR00 [R/W]
00000000
PODR01 [R/W]
00000000
000E04H
Reserved
PODR05 [R/W]
00000000
PODR06 [R/W]
00000000
PODR07 [R/W]
00000000
000E08H
PODR08 [R/W]
0 - - 0 - - 00
PODR09 [R/W]
- - - - 0000
PODR10 [R/W]
- - - - 0 - 00
Reserved
PODR14 [R/W]
00000000
PODR15 [R/W]
- - - - 0000
000E0CH
+2
Reserved
+3
Reserved
000E10H
PODR16 [R/W]
00000000
PODR17 [R/W]
0000 - - - -
PODR18 [R/W]
- 000 - 000
PODR19 [R/W]
- 000 - 000
000E14H
PODR20 [R/W]
- 000 - 000
Reserved
PODR22 [R/W]
0000 - 0 - 0
PODR23 [R/W]
- 0 - 00000
000E18H
PODR24 [R/W]
00000000
000E1CH
PODR28 [R/W]
00000000
PODR29 [R/W]
00000000
Reserved
Reserved
000E40H
PILR00 [R/W]
00000000
PILR01 [R/W]
00000000
000E44H
Reserved
PILR05 [R/W]
00000000
PILR06 [R/W]
00000000
PILR07 [R/W]
00000000
000E48H
PILR08 [R/W]
0 - - 0 - - 00
PILR09 [R/W]
- - - - 0000
PILR10 [R/W]
- - - - 0 - 00
Reserved
PILR14 [R/W]
00000000
PILR15 [R/W]
- - - - 0000
Reserved
Reserved
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
0000 - - - -
PILR18 [R/W]
- 000 - 000
PILR19 [R/W]
- 000 - 000
000E54H
PILR20 [R/W]
- 000 - 000
Reserved
PILR22 [R/W]
0000 - 0 - 0
PILR23 [R/W]
- 0 - 00000
000E58H
PILR24 [R/W]
00000000
000E5CH
PILR28 [R/W]
00000000
000E60H
to
000E7CH
R-bus Port
Output Drive Select
Register
Reserved
000E20H
to
000E3CH
000E4CH
Block
R-bus Port
Input Level Select
Register
Reserved
PILR29 [R/W]
00000000
Reserved
Reserved
(Continued)
76
DS07-16617-2E
MB91460S Series
Register
Address
+0
+1
000E80H
EPILR00 [R/W]
00000000
EPILR01 [R/W]
00000000
000E84H
Reserved
EPILR05 [R/W]
00000000
EPILR06 [R/W]
00000000
EPILR07 [R/W]
00000000
000E88H
EPILR08 [R/W]
0 - - 0 - - 00
EPILR09 [R/W]
- - - - 0000
EPILR10 [R/W]
- - - - 0 - 00
Reserved
EPILR14 [R/W]
00000000
EPILR15 [R/W]
- - - - 0000
000E8CH
+2
Reserved
+3
Block
Reserved
000E90H
EPILR16 [R/W]
00000000
EPILR17 [R/W]
0000 - - - -
EPILR18 [R/W]
- 000 - 000
EPILR19 [R/W]
- 000 - 000
000E94H
EPILR20 [R/W]
- 000 - 000
Reserved
EPILR22 [R/W]
0000 - 0 - 0
EPILR23 [R/W]
- 0 - 00000
000E98H
EPILR24 [R/W]
00000000
000E9CH
EPILR28 [R/W]
00000000
R-bus Extra
Port Input Level
Select Register
Reserved
EPILR29 [R/W]
00000000
000EA0H
to
000EBCH
Reserved
Reserved
000EC0H
PPER00 [R/W]
00000000
PPER01 [R/W]
00000000
000EC4H
Reserved
PPER05 [R/W]
00000000
PPER06 [R/W]
00000000
PPER07 [R/W]
00000000
000EC8H
PPER08 [R/W]
0 - - 0 - - 00
PPER09 [R/W]
- - - - 0000
PPER10 [R/W]
- - - - 0 - 00
Reserved
PPER14 [R/W]
00000000
PPER15 [R/W]
- - - - 0000
000ECCH
Reserved
Reserved
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
0000 - - - -
PPER18 [R/W]
- 000 - 000
PPER19 [R/W]
- 000 - 000
000ED4H
PPER20 [R/W]
- 000 - 000
Reserved
PPER22 [R/W]
0000 - 0 - 0
PPER23 [R/W]
- 0 - 00000
000ED8H
PPER24 [R/W]
00000000
000EDCH
PPER28 [R/W]
00000000
000EE0H
to
000EFCH
R-bus Port
Pull-Up/Down Enable
Register
Reserved
PPER29 [R/W]
00000000
Reserved
Reserved
(Continued)
DS07-16617-2E
77
MB91460S Series
Address
Register
+0
+1
000F00H
PPCR00 [R/W]
11111111
PPCR01 [R/W]
11111111
000F04H
Reserved
PPCR05 [R/W]
11111111
PPCR06 [R/W]
11111111
PPCR07 [R/W]
11111111
000F08H
PPCR08 [R/W]
1 - - 1- - 11
PPCR09 [R/W]
- - - - 1111
PPCR10 [R/W]
- - - - 1 - 11
Reserved
PPCR14 [R/W]
11111111
PPCR15 [R/W]
- - - - 1111
000F0CH
+2
Reserved
+3
Block
Reserved
000F10H
PPCR16 [R/W]
11111111
PPCR17 [R/W]
11111111
PPCR18 [R/W]
- 111 - 111
PPCR19 [R/W]
- 111 - 111
000F14H
PPCR20 [R/W]
- 111 - 111
Reserved
PPCR22 [R/W]
1111 - 1 - 1
PPCR23 [R/W]
- 1 - 11111
000F18H
PPCR24 [R/W]
11111111
000F1CH
PPCR28 [R/W]
11111111
R-bus Port
Pull-Up/Down Control
Register
Reserved
PPCR29 [R/W]
11111111
Reserved
000F20H
to
000F3CH
Reserved
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
(Continued)
78
DS07-16617-2E
MB91460S Series
Address
Register
+0
+1
001028H
to
001FFCH
002000H
to
006FFCH
007000H
007004H
+2
+3
Block
Reserved
MB91F467SA Flash-cache size is 8 Kbytes : 004000H to 005FFCH
FMCS [R/W]
01101000
FMCR [R]
- - - 00000
FMWT [R/W]
11111111 11111111
FCHCR [R/W]
- - - - - - 00 10000011
FMWT2 [R]
- 001 - - - -
FMPS [R/W]
- - - - - 000
007008H
FMAC [R]
00000000 00000000 00000000 00000000
00700CH
FCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007014H
to
0071FCH
Reserved
007200H
RHCTRL[R/W]
00 - - 0000 - - - - - - - - 0000 - 000 - - - - - - - -
007204H
Reserved
007208H
CHCTRL0[R/W]
- - - - 0 - - - 000 - - - 00 00000000 - - 00 - - 000
00720CH
CHSTAT0[R]
00000000 - - - - - - - - 00000000 00000000
007210H
CHWDG0[R/W]
00 - - 0000 00000000 xxxxxxxx xxxxxxxx
007214H
CHCTRL1[R/W]
- - - - 0 - - - 000 - - - 00 00000000 - - 00 - - 000
007218H
CHSTAT1[R]
00000000 - - - - - - - - 00000000 00000000
00721CH
CHWDG1[R/W]
00 - - 0000 00000000 xxxxxxxx xxxxxxxx
Flash-cache /
I-RAM area
Flash Memory/
Flash-cache/
I-RAM Control
Register
Flash-cache Noncacheable area setting
Register
Automotive Remote
Handler Control
APIX® Control/Status
(Continued)
DS07-16617-2E
79
MB91460S Series
Address
Register
+0
+1
+2
+3
007220H
TBCTRL00[R/W]
- - - 00000 0000 - 000
TBCTRL01[R/W]
- - - 00000 0000 - 000
007224H
TBCTRL02[R/W]
- - - 00000 0000 - 000
TBCTRL03[R/W]
- - - 00000 0000 - 000
007228H
TBCTRL04[R/W]
- - - 00000 0000 - 000
TBCTRL05[R/W]
- - - 00000 0000 - 000
00722CH
TBCTRL06[R/W]
- - - 00000 0000 - 000
TBCTRL07[R/W]
- - - 00000 0000 - 000
007230H
TBCTRL08[R/W]
- - - 00000 0000 - 000
TBCTRL09[R/W]
- - - 00000 0000 - 000
007234H
TBCTRL10[R/W]
- - - 00000 0000 - 000
TBCTRL11[R/W]
- - - 00000 0000 - 000
007238H
TBCTRL12[R/W]
- - - 00000 0000 - 000
TBCTRL13[R/W]
- - - 00000 0000 - 000
00723CH
TBCTRL14[R/W]
- - - 00000 0000 - 000
TBCTRL15[R/W]
- - - 00000 0000 - 000
007240H
TBIRQ[R]
00000000 00000000
Reserved
007244H
to
00724CH
Block
Automotive Remote
Handler Transaction
Buffer Control
Automotive Remote
Handler Interrupt
Reserved
007250H
TFCRTL00[R/W]
00 - 00000
TFIDX00[R/W]
00000000
TFCRTL01[R/W]
00 - 00000
TFIDX01[R/W]
00000000
007254H
TFCRTL02[R/W]
00 - 00000
TFIDX02[R/W]
00000000
TFCRTL03[R/W]
00 - 00000
TFIDX03[R/W]
00000000
007258H
TFCRTL04[R/W]
00 - 00000
TFIDX04[R/W]
00000000
TFCRTL05[R/W]
00 - 00000
TFIDX05[R/W]
00000000
00725CH
TFCRTL06[R/W]
00 - 00000
TFIDX06[R/W]
00000000
TFCRTL07[R/W]
00 - 00000
TFIDX07[R/W]
00000000
007260H
TFCRTL08[R/W]
00 - 00000
TFIDX08[R/W]
00000000
TFCRTL09[R/W]
00 - 00000
TFIDX09[R/W]
00000000
007264H
TFCRTL10[R/W]
00 - 00000
TFIDX10[R/W]
00000000
TFCRTL11[R/W]
00 - 00000
TFIDX11[R/W]
00000000
007268H
TFCRTL12[R/W]
00 - 00000
TFIDX12[R/W]
00000000
TFCRTL13[R/W]
00 - 00000
TFIDX13[R/W]
00000000
00726CH
TFCRTL14[R/W]
00 - 00000
TFIDX14[R/W]
00000000
TFCRTL15[R/W]
00 - 00000
TFIDX15[R/W]
00000000
007270H
TFADDR00[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
007274H
TFADDR01[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
Transaction Frame
(Continued)
80
DS07-16617-2E
MB91460S Series
Address
Register
+0
+1
+2
007278H
TFADDR02[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
00727CH
TFADDR03[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
007280H
TFADDR04[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
007284H
TFADDR05[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
007288H
TFADDR06[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
00728CH
TFADDR07[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
007290H
TFADDR08[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
007294H
TFADDR09[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
007298H
TFADDR10[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
00729CH
TFADDR11[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
0072A0H
TFADDR12[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
0072A4H
TFADDR13[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
0072A8H
TFADDR14[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
0072ACH
TFADDR15[R/W]
- - - - - - - - - - - - 0000 00000000 00000000
0072B0H
TFDATA00[R/W]
00000000 00000000 00000000 00000000
0072B4H
TFDATA01[R/W]
00000000 00000000 00000000 00000000
0072B8H
TFDATA02[R/W]
00000000 00000000 00000000 00000000
0072BCH
TFDATA03[R/W]
00000000 00000000 00000000 00000000
0072C0H
TFDATA04[R/W]
00000000 00000000 00000000 00000000
0072C4H
TFDATA05[R/W]
00000000 00000000 00000000 00000000
0072C8H
TFDATA06[R/W]
00000000 00000000 00000000 00000000
+3
Block
(Continued)
DS07-16617-2E
81
MB91460S Series
Address
Register
+0
+1
+2
0072CCH
TFDATA07[R/W]
00000000 00000000 00000000 00000000
0072D0H
TFDATA08[R/W]
00000000 00000000 00000000 00000000
0072D4H
TFDATA09[R/W]
00000000 00000000 00000000 00000000
0072D8H
TFDATA10[R/W]
00000000 00000000 00000000 00000000
0072DCH
TFDATA11[R/W]
00000000 00000000 00000000 00000000
0072E0H
TFDATA12[R/W]
00000000 00000000 00000000 00000000
0072E4H
TFDATA13[R/W]
00000000 00000000 00000000 00000000
0072E8H
TFDATA14[R/W]
00000000 00000000 00000000 00000000
0072ECH
TFDATA15[R/W]
00000000 00000000 00000000 00000000
0072F0H
EVCTRL[R/W]
- - - - - - - 0 0 - 000000 00000000 00000000
0072F4H
Reserved
0072F8H
EVBUF0[R/W]
- - - - - - - 0 00000000 - - - - - - - - - - - - - - - -
0072FCH
EVBUF1[R/W]
00000000 00000000 00000000 00000000
007300H
APCFG00[R/W]
00000000 00110000 00000000 10010000
007304H
APCFG01[R/W]
11110000 10000000 00000000 01001000
007308H
APCFG02[R/W]
00000010 00000010 01000000 - - - - - - - -
00730CH
APCFG03[R/W]
00100110 10100000 10011010 00 - - - 000
007310H
APCFG10[R/W]
00000000 00110000 00000000 10010000
007314H
APCFG11[R/W]
11110000 00000000 00000000 01001000
007318H
APCFG12[R/W]
00000010 00000010 01000000 - - - - - - - -
00731CH
APCFG13[R/W]
00100110 10100100 10011010 00 - - - 000
+3
Block
Automotive Remote
Handler Eventcontrol
Automotive Remote
Handler Eventqueue
APIX® Configuration
(Continued)
82
DS07-16617-2E
MB91460S Series
Address
Register
+0
+1
+2
+3
007320H
MODULEID[R]
0 - - - - - - - ******** ******** ******** *6
007324H
to
007FFCH
Reserved
008000H
to
00BFFCH
MB91F467SA Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH
(instruction access is 1 wait cycle, data access is 1 wait cycle)
00C000H
CTRLR0 [R/W]
00000000 00000001
STATR0 [R/W]
00000000 00000000
00C004H
ERRCNT0 [R]
00000000 00000000
BTR0 [R/W]
00100011 00000001
00C008H
INTR0 [R]
00000000 00000000
TESTR0 [R/W]
00000000 X0000000
00C00CH
BRPE0 [R/W]
00000000 00000000
CBSYNC*2
00C010H
IF1CREQ0 [R/W]
00000000 00000001
IF1CMSK0 [R/W]
00000000 00000000
00C014H
IF1MSK20 [R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
00C018H
IF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
00C01CH
IF1MCTR0 [R/W]
00000000 00000000
Reserved
00C020H
IF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
00C024H
IF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
00C028H,
00C02CH
Reserved
00C030H
IF1DTA20 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
00C034H
IF1DTB20 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
00C038H,
00C03CH
Block
Version of APIX® Controller
Boot ROM area
CAN 0
Control
Register
CAN 0
IF 1 Register
CAN 0
IF 1 Register
Reserved
(Continued)
DS07-16617-2E
83
MB91460S Series
Address
Register
+0
+1
+2
+3
00C040H
IF2CREQ0 [R/W]
00000000 00000001
IF2CMSK0 [R/W]
00000000 00000000
00C044H
IF2MSK20 [R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
00C048H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
00C04CH
IF2MCTR0 [R/W]
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
00C054H
IF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
00C058H,
00C05CH
IF2DTA20 [R/W]
00000000 00000000
IF2DTA10 [R/W]
00000000 00000000
00C064H
IF2DTB20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
00C068H
to
00C07CH
Reserved
TREQR20 [R]
00000000 00000000
00C084H
to
00C08CH
00C090H
NEWDT20 [R]
00000000 00000000
00C0B4H
to
00C0FCH
NEWDT10 [R]
00000000 00000000
CAN 0
Status Flags
Reserved
INTPND20 [R]
00000000 00000000
00C0A4H
to
00C0ACH
00C0B0H
TREQR10 [R]
00000000 00000000
Reserved
00C094H
to
00C09CH
00C0A0H
CAN 0
IF 2 Register
Reserved
00C060H
00C080H
Block
INTPND10 [R]
00000000 00000000
Reserved
MSGVAL20 [R]
00000000 00000000
MSGVAL10 [R]
00000000 00000000
Reserved
(Continued)
84
DS07-16617-2E
MB91460S Series
Address
Register
+0
+1
+2
+3
00C100H
CTRLR1 [R/W]
00000000 00000001
STATR1 [R/W]
00000000 00000000
00C104H
ERRCNT1 [R]
00000000 00000000
BTR1 [R/W]
00100011 00000001
00C108H
INTR1 [R]
00000000 00000000
TESTR1 [R/W]
00000000 X0000000
00C10CH
BRPE1 [R/W]
00000000 00000000
Reserved
00C110H
IF1CREQ1 [R/W]
00000000 00000001
IF1CMSK1 [R/W]
00000000 00000000
00C114H
IF1MSK21 [R/W]
11111111 11111111
IF1MSK11 [R/W]
11111111 11111111
00C118H
IF1ARB21 [R/W]
00000000 00000000
IF1ARB11 [R/W]
00000000 00000000
00C11CH
IF1MCTR1 [R/W]
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W]
00000000 00000000
IF1DTA21 [R/W]
00000000 00000000
00C124H
IF1DTB11 [R/W]
00000000 00000000
IF1DTB21 [R/W]
00000000 00000000
00C128H,
00C12CH
CAN 1
Control
Register
CAN 1
IF 1 Register
Reserved
00C130H
IF1DTA21 [R/W]
00000000 00000000
IF1DTA11 [R/W]
00000000 00000000
00C134H
IF1DTB21 [R/W]
00000000 00000000
IF1DTB11 [R/W]
00000000 00000000
00C138H,
00C13CH
Block
CAN 1
IF 1 Register
Reserved
(Continued)
DS07-16617-2E
85
MB91460S Series
Address
Register
+0
+1
+2
+3
00C140H
IF2CREQ1 [R/W]
00000000 00000001
IF2CMSK1 [R/W]
00000000 00000000
00C144H
IF2MSK21 [R/W]
11111111 11111111
IF2MSK11 [R/W]
11111111 11111111
00C148H
IF2ARB21 [R/W]
00000000 00000000
IF2ARB11 [R/W]
00000000 00000000
00C14CH
IF2MCTR1 [R/W]
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W]
00000000 00000000
IF2DTA21 [R/W]
00000000 00000000
00C154H
IF2DTB11 [R/W]
00000000 00000000
IF2DTB21 [R/W]
00000000 00000000
00C158H,
00C15CH
IF2DTA21 [R/W]
00000000 00000000
IF2DTA11 [R/W]
00000000 00000000
00C164H
IF2DTB21 [R/W]
00000000 00000000
IF2DTB11 [R/W]
00000000 00000000
00C168H
to
00C17CH
Reserved
TREQR21 [R]
00000000 00000000
00C184H
to
00C18CH
00C190H
NEWDT21 [R]
00000000 00000000
00C1B4H
to
00C1FCH
NEWDT11 [R]
00000000 00000000
CAN 1
Status Flags
Reserved
INTPND21 [R]
00000000 00000000
00C1A4H
to
00C1ACH
00C1B0H
TREQR11 [R]
00000000 00000000
Reserved
00C194H
to
00C19CH
00C1A0H
CAN 1
IF 2 Register
Reserved
00C160H
00C180H
Block
INTPND11 [R]
00000000 00000000
Reserved
MSGVAL21 [R]
00000000 00000000
MSGVAL11 [R]
00000000 00000000
CAN 1
Status Flags
Reserved
(Continued)
86
DS07-16617-2E
MB91460S Series
Address
Register
+0
+1
+2
00C200H
to
00EFFCH
Reserved
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008H
BIAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F00CH
BOAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F010H
BIRQ [R/W]
- - - - - - - - - - - - - - - - 00000000 00000000
+3
Block
EDSU / MPU
00F014H
to
00F01CH
Reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
BCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H
to
00F07CH
Reserved
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDSU / MPU
(Continued)
DS07-16617-2E
87
MB91460S Series
(Continued)
Address
Register
+0
+1
+2
+3
Block
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H
to
01FFFCH
Reserved
020000H
to
02FFFCH
MB91F467SA D-RAM size is 32 Kbytes : 028000H to 02FFFCH
(data access is 0 wait cycles)
D-RAM area
030000H
to
037FFCH
MB91F467SA ID-RAM size is 32 Kbytes : 030000H to 037FFCH
(instruction access is 0 wait cycles, data access is 1 wait cycle)
ID-RAM area
038000H
to
03FFFCH
Reserved
EDSU / MPU
*1 : Use a read access ( byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt
acceptance of the CPU) to a preceding write access to the resources on R-bus (e.g. to an interrupt flag) on
following address (0x0000-0x01FF, 0x0280-0x037F, 0x0400-0x063F and 0x0C00-0x0FFF).
*2 : Use a read access ( byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt
acceptance of the CPU) to a preceding write access to the CANS on D-bus (e.g. to an interrupt flag) on following
address (0x0000-0xFFFF).
*3 : depends on the number of available CAN channels
*4 : ACR0 [11 : 10] depends on Mode vector fetch information on bus width
*5 : TCR [3 : 0] INIT value = 0000, keeps value after RST
*6 : Datecode of APIX® controller version
88
DS07-16617-2E
MB91460S Series
2.
Flash memory and external bus area
32bit write mode
16bit write mode
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
040000H
to
05FFF8H
SA8 (64kB)
SA9 (64kB)
ROMS0
060000H
to
07FFF8H
SA10 (64kB)
SA11 (64kB)
ROMS1
080000H
to
09FFF8H
SA12 (64kB)
SA13 (64kB)
ROMS2
0A0000H
to
0BFFF8H
SA14 (64kB)
SA15 (64kB)
ROMS3
0C0000H
to
0DFFF8H
SA16 (64kB)
SA17 (64kB)
ROMS4
0E0000H
to
0FFFF0H
SA18 (64kB)
SA19 (64kB)
0FFFF8H
FMV [R]
06 00 00 00H
FRV [R]
00 00 BF F8H
100000H
to
11FFF8H
SA20 (64kB)
SA21 (64kB)
120000H
to
13FFF8H
SA22 (64kB)
SA23 (64kB)
140000H
to
143FF8H
SA0 (8kB)
SA1 (8kB)
144000H
to
17FF8H
SA2 (8kB)
SA3 (8kB)
148000H
to
14BFF8H
SA4 (8kB)
SA5 (8kB)
14C000H
to
14FFF8H
SA6 (8kB)
SA7 (8kB)
150000H
to
17FFF8H
ROMS5
ROMS6
ROMS7
Reserved
(Continued)
DS07-16617-2E
89
MB91460S Series
(Continued)
32bit write mode
16bit write mode
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
180000H
to
1BFFF8H
ROMS8
1C0000H
to
1FFFF8H
ROMS9
200000H
to
27FFF8H
ROMS10
280000H
to
2FFFF8H
ROMS11
300000H
to
37FFF8H
External Bus Area
ROMS12
380000H
to
3FFFF8H
ROMS13
400000H
to
47FFF8H
ROMS14
480000H
to
4FFFF8H
ROMS15
Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the
values shown above will be read.
90
DS07-16617-2E
MB91460S Series
■ INTERRUPT VECTOR TABLE
Interrupt
number
Interrupt
Interrupt level*1
Decimal
Hexadecimal
Reset
0
00
⎯
⎯
Mode vector
1
01
⎯
System reserved
2
02
System reserved
3
System reserved
DMA
Interrupt vector*2
Setting
Register
RegisOffset
address
ter
Default Vector
address
RN*5
Stop*6
3FCH
000FFFFCH
⎯
⎯
⎯
3F8H
000FFFF8H
⎯
⎯
⎯
⎯
3F4H
000FFFF4H
⎯
⎯
03
⎯
⎯
3F0H
000FFFF0H
⎯
⎯
4
04
⎯
⎯
3ECH
000FFFECH
⎯
⎯
CPU supervisor mode
(INT #5 instruction) *7
5
05
⎯
⎯
3E8H
000FFFE8H
⎯
⎯
Memory Protection exception
*7
6
06
⎯
⎯
3E4H
000FFFE4H
⎯
⎯
System reserved
7
07
⎯
⎯
3E0H
000FFFE0H
⎯
⎯
System reserved
8
08
⎯
⎯
3DCH
000FFFDCH
⎯
⎯
System reserved
9
09
⎯
⎯
3D8H
000FFFD8H
⎯
⎯
System reserved
10
0A
⎯
⎯
3D4H
000FFFD4H
⎯
⎯
System reserved
11
0B
⎯
⎯
3D0H
000FFFD0H
⎯
⎯
System reserved
12
0C
⎯
⎯
3CCH
000FFFCCH
⎯
⎯
System reserved
13
0D
⎯
⎯
3C8H
000FFFC8H
⎯
⎯
Undefined instruction exception
14
0E
⎯
⎯
3C4H
000FFFC4H
⎯
⎯
NMI request
15
0F
3C0H
000FFFC0H
⎯
⎯
External Interrupt 0
16
10
3BCH
000FFFBCH
0, 16
⎯
External Interrupt 1
17
11
3B8H
000FFFB8H
1, 17
⎯
External Interrupt 2
18
12
3B4H
000FFFB4H
2, 18
⎯
External Interrupt 3
19
13
3B0H
000FFFB0H
3, 19
⎯
External Interrupt 4
20
14
3ACH
000FFFACH
20
⎯
External Interrupt 5
21
15
3A8H
000FFFA8H
21
⎯
External Interrupt 6
22
16
3A4H
000FFFA4H
22
⎯
External Interrupt 7
23
17
3A0H
000FFFA0H
23
⎯
External Interrupt 8
24
18
39CH
000FFF9CH
⎯
⎯
External Interrupt 9
25
19
398H
000FFF98H
⎯
⎯
External Interrupt 10
26
1A
394H
000FFF94H
⎯
⎯
External Interrupt 11
27
1B
390H
000FFF90H
⎯
⎯
External Interrupt 12
28
1C
38CH
000FFF8CH
⎯
⎯
External Interrupt 13
29
1D
388H
000FFF88H
⎯
⎯
FH fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
ICR06
446H
(Continued)
DS07-16617-2E
91
MB91460S Series
Interrupt
number
Interrupt
Decimal
Hexadecimal
External Interrupt 14
30
1E
External Interrupt 15
31
1F
Reload Timer 0
32
20
Reload Timer 1
33
21
Reload Timer 2
34
22
Reload Timer 3
35
23
Reload Timer 4
36
24
Reload Timer 5
37
25
Reload Timer 6
38
26
Reload Timer 7
39
27
Free Run Timer 0
40
28
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
Free Run Timer 3
43
2B
Free Run Timer 4
44
2C
Free Run Timer 5
45
2D
Free Run Timer 6
46
2E
Free Run Timer 7
47
2F
CAN 0
48
30
CAN 1
49
31
System reserved
50
32
System reserved
51
33
System reserved
52
34
System reserved
53
35
System reserved
54
36
System reserved
55
37
System reserved
56
38
System reserved
57
39
LIN-USART 2 RX
58
3A
LIN-USART 2 TX
59
3B
LIN-USART 3 RX
60
3C
LIN-USART 3 TX
61
3D
Interrupt level*1
Setting
Register
RegisOffset
address
ter
ICR07
447H
ICR08
448H
ICR09
449H
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
DMA
Interrupt vector*2
Default Vector
address
RN*5
Stop*6
384H
000FFF84H
⎯
⎯
380H
000FFF80H
⎯
⎯
37CH
000FFF7CH
4, 32
⎯
378H
000FFF78H
5, 33
⎯
374H
000FFF74H
34
⎯
370H
000FFF70H
35
⎯
36CH
000FFF6CH
36
⎯
368H
000FFF68H
37
⎯
364H
000FFF64H
38
⎯
360H
000FFF60H
39
⎯
35CH
000FFF5CH
40
⎯
358H
000FFF58H
41
⎯
354H
000FFF54H
42
⎯
350H
000FFF50H
43
⎯
34CH
000FFF4CH
44
⎯
348H
000FFF48H
45
⎯
344H
000FFF44H
46
⎯
340H
000FFF40H
47
⎯
33CH
000FFF3CH
⎯
⎯
338H
000FFF38H
⎯
⎯
334H
000FFF34H
⎯
⎯
330H
000FFF30H
⎯
⎯
32CH
000FFF2CH
⎯
⎯
328H
000FFF28H
⎯
⎯
324H
000FFF24H
6, 48
⎯
320H
000FFF20H
7, 49
⎯
31CH
000FFF1CH
8, 50
⎯
318H
000FFF18H
9, 51
⎯
314H
000FFF14H
52
⎯
310H
000FFF10H
53
⎯
30CH
000FFF0CH
54
⎯
308H
000FFF08H
55
⎯
(Continued)
92
DS07-16617-2E
MB91460S Series
Interrupt
number
Interrupt
Decimal
Hexadecimal
System reserved
62
3E
Delayed Interrupt
63
3F
System reserved *4
64
40
4
65
41
LIN-USART (FIFO) 4 RX
66
42
LIN-USART (FIFO) 4 TX
67
43
LIN-USART (FIFO) 5 RX
68
44
LIN-USART (FIFO) 5 TX
69
45
LIN-USART (FIFO) 6 RX
70
46
LIN-USART (FIFO) 6 TX
71
47
LIN-USART (FIFO) 7 RX
72
48
LIN-USART (FIFO) 7 TX
73
49
IC0/IC2
74
4A
I2C 1
75
4B
APIX® Event/ Eventlevel/
Eventbufferoverflow/ Fatal Error/ Watchdog
76
4C
System reserved
77
4D
System reserved
78
4E
System reserved
79
4F
APIX® Transaction Buffer
80
50
System reserved
81
51
System reserved
82
52
System reserved
83
53
System reserved
84
54
System reserved
85
55
System reserved
86
56
System reserved
87
57
System reserved
88
58
System reserved
89
59
System reserved
90
5A
System reserved
91
5B
System reserved *
2
2
Interrupt level*1
Setting
Register
RegisOffset
address
ter
ICR23 *3
457H
(ICR24)
(458H)
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
DMA
Interrupt vector*2
Default Vector
address
RN*5
Stop*6
304H
000FFF04H
⎯
⎯
300H
000FFF00H
⎯
⎯
2FCH
000FFEFCH
⎯
⎯
2F8H
000FFEF8H
⎯
⎯
2F4H
000FFEF4H
10, 56
10, 56
2F0H
000FFEF0H
11, 57
⎯
2ECH
000FFEECH
12, 58
12, 58
2E8H
000FFEE8H
13, 59
⎯
2E4H
000FFEE4H
60
60
2E0H
000FFEE0H
61
⎯
2DCH
000FFEDCH
62
62
2D8H
000FFED8H
63
⎯
2D4H
000FFED4H
28, 30
28, 30
2D0H
000FFED0H
29
29
2CCH
000FFECCH
⎯
⎯
2C8H
000FFEC8H
65
⎯
2C4H
000FFEC4H
66
⎯
2C0H
000FFEC0H
67
⎯
2BCH
000FFEBCH
160175
160175
2B8H
000FFEB8H
69
⎯
2B4H
000FFEB4H
70
⎯
2B0H
000FFEB0H
71
⎯
2ACH
000FFEACH
72
⎯
2A8H
000FFEA8H
73
⎯
2A4H
000FFEA4H
74
⎯
2A0H
000FFEA0H
75
⎯
29CH
000FFE9CH
76
⎯
298H
000FFE98H
77
⎯
294H
000FFE94H
78
⎯
290H
000FFE90H
79
⎯
(Continued)
DS07-16617-2E
93
MB91460S Series
Interrupt
number
Interrupt
Decimal
Hexadecimal
Input Capture 0
92
5C
Input Capture 1
93
5D
Input Capture 2
94
5E
Input Capture 3
95
5F
Input Capture 4
96
60
Input Capture 5
97
61
Input Capture 6
98
62
Input Capture 7
99
63
Output Compare 0
100
64
Output Compare 1
101
65
Output Compare 2
102
66
Output Compare 3
103
67
System reserved
104
68
System reserved
105
69
System reserved
106
6A
System reserved
107
6B
Sound Generator
108
6C
Phase Frequency Modulator
109
6D
System reserved
110
6E
System reserved
111
6F
PPG0
112
70
PPG1
113
71
PPG2
114
72
PPG3
115
73
PPG4
116
74
PPG5
117
75
PPG6
118
76
PPG7
119
77
PPG8
120
78
PPG9
121
79
PPG10
122
7A
PPG11
123
7B
Interrupt level*1
Setting
Register
RegisOffset
address
ter
ICR38
466H
ICR39
467H
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47 *3
46FH
ICR48
470H
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
DMA
Interrupt vector*2
Default Vector
address
RN*5
Stop*6
28CH
000FFE8CH
80
⎯
288H
000FFE88H
81
⎯
284H
000FFE84H
82
⎯
280H
000FFE80H
83
⎯
27CH
000FFE7CH
84
⎯
278H
000FFE78H
85
⎯
274H
000FFE74H
86
⎯
270H
000FFE70H
87
⎯
26CH
000FFE6CH
88
⎯
268H
000FFE68H
89
⎯
264H
000FFE64H
90
⎯
260H
000FFE60H
91
⎯
25CH
000FFE5CH
92
⎯
258H
000FFE58H
93
⎯
254H
000FFE54H
94
⎯
250H
000FFE50H
95
⎯
24CH
000FFE4CH
⎯
⎯
248H
000FFE48H
⎯
⎯
244H
000FFE44H
⎯
⎯
240H
000FFE40H
⎯
⎯
23CH
000FFE3CH
15, 96
⎯
238H
000FFE38H
97
⎯
234H
000FFE34H
98
⎯
230H
000FFE30H
99
⎯
22CH
000FFE2CH
100
⎯
228H
000FFE28H
101
⎯
224H
000FFE24H
102
⎯
220H
000FFE20H
103
⎯
21CH
000FFE1CH
104
⎯
218H
000FFE18H
105
⎯
214H
000FFE14H
106
⎯
210H
000FFE10H
107
⎯
(Continued)
94
DS07-16617-2E
MB91460S Series
(Continued)
Interrupt
number
Interrupt
Decimal
Hexadecimal
PPG12
124
7C
PPG13
125
7D
PPG14
126
7E
PPG15
127
7F
Up/Down Counter 0
128
80
Up/Down Counter 1
129
81
Up/Down Counter 2
130
82
Up/Down Counter 3
131
83
Real Time Clock
132
84
Calibration Unit
133
85
A/D Converter 0
134
86
System reserved
135
87
Alarm Comparator 0
136
88
System reserved
137
89
Low Voltage Detection
138
8A
SMC Comparator 0 to 5
139
8B
Timebase Overflow
140
8C
PLL Clock Gear
141
8D
DMA Controller
142
8E
Main/Sub OSC stability wait
143
8F
Security vector
144
Used by the INT instruction.
145
to
255
Interrupt level*1
DMA
Interrupt vector*2
Setting
Register
RegisOffset
address
ter
Default Vector
address
RN*5
Stop*6
20CH
000FFE0CH
108
⎯
208H
000FFE08H
109
⎯
204H
000FFE04H
110
⎯
200H
000FFE00H
111
⎯
1FCH
000FFDFCH
⎯
⎯
1F8H
000FFDF8H
⎯
⎯
1F4H
000FFDF4H
⎯
⎯
1F0H
000FFDF0H
⎯
⎯
1ECH
000FFDECH
⎯
⎯
1E8H
000FFDE8H
⎯
⎯
1E4H
000FFDE4H
14, 112
⎯
1E0H
000FFDE0H
⎯
⎯
1DCH
000FFDDCH
⎯
⎯
1D8H
000FFDD8H
⎯
⎯
1D4H
000FFDD4H
⎯
⎯
1D0H
000FFDD0H
⎯
⎯
1CCH
000FFDCCH
⎯
⎯
1C8H
000FFDC8H
⎯
⎯
1C4H
000FFDC4H
⎯
⎯
1C0H
000FFDC0H
⎯
⎯
ICR54
476H
ICR55
477H
ICR56
478H
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
ICR63
47FH
90
⎯
⎯
1BCH
000FFDBCH
⎯
⎯
91
to
FF
⎯
⎯
1B8H to
000H
000FFDB8H
to
000FFC00H
⎯
⎯
*1 : The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is
provided for each interrupt request.
*2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the
table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the
table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set
to 000FFC00H after the internal boot ROM is executed.
*3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])
*4 : Used by REALOS
*5 :DMA RN is the resource number used for DMA operation. No number means that this resource interrupt cannot
be used to trigger a DMA transfer.
*6 :DMA Stop shows the DMA Transfer Stop Request feature.
*7 :Memory Protection Unit (MPU) support
DS07-16617-2E
95
MB91460S Series
■ RECOMMENDED SETTINGS
1. PLL and Clockgear settings
Please note that for MB91F467SA the core base clock frequencies are valid in the 1.8V operation mode of the
Main regulator and Flash.
Recommended PLL divider and clockgear settings
PLL
Input (CLK)
[MHz]
96
Frequency Parameter
Clockgear Parameter
PLL
Core Base
Output (X)
Clock
[MHz]
[MHz]
DIVM
DIVN
DIVG
MULG
4
2
25
16
24
200
100
4
2
24
16
24
192
96
4
2
23
16
24
184
92
4
2
22
16
24
176
88
4
2
21
16
20
168
84
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
Remarks
MULG
DS07-16617-2E
MB91460S Series
2. Clock Modulator settings
The clock modulator is currently being evaluated and should not be used for other purpose than testing.
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from
32MHz up to 88MHz.
The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings
should be set according to base clock frequency.
Clock Modulator settings, frequency range and supported supply voltage
Modulation Degree
Random No
CMPR
Baseclk
Fmin
(k)
(N)
[hex]
[MHz]
[MHz]
Fmax
[MHz]
1
3
026F
88
79.5
98.5
1
3
026F
84
76.1
93.8
1
3
026F
80
72.6
89.1
1
5
02AE
80
68.7
95.8
2
3
046E
80
68.7
95.8
1
3
026F
76
69.1
84.5
1
5
02AE
76
65.3
90.8
1
7
02ED
76
62
98.1
2
3
046E
76
65.3
90.8
3
3
066D
76
62
98.1
1
3
026F
72
65.5
79.9
1
5
02AE
72
62
85.8
1
7
02ED
72
58.8
92.7
2
3
046E
72
62
85.8
3
3
066D
72
58.8
92.7
1
3
026F
68
62
75.3
1
5
02AE
68
58.7
80.9
1
7
02ED
68
55.7
87.3
1
9
032C
68
53
95
2
3
046E
68
58.7
80.9
2
5
04AC
68
53
95
3
3
066D
68
55.7
87.3
4
3
086C
68
53
95
1
3
026F
64
58.5
70.7
1
5
02AE
64
55.3
75.9
1
7
02ED
64
52.5
82
1
9
032C
64
49.9
89.1
1
11
036B
64
47.6
97.6
2
3
046E
64
55.3
75.9
Remarks
(Continued)
DS07-16617-2E
97
MB91460S Series
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
2
5
04AC
64
49.9
89.1
3
3
066D
64
52.5
82
4
3
086C
64
49.9
89.1
5
3
0A6B
64
47.6
97.6
1
3
026F
60
54.9
66.1
1
5
02AE
60
51.9
71
1
7
02ED
60
49.3
76.7
1
9
032C
60
46.9
83.3
1
11
036B
60
44.7
91.3
2
3
046E
60
51.9
71
2
5
04AC
60
46.9
83.3
3
3
066D
60
49.3
76.7
4
3
086C
60
46.9
83.3
5
3
0A6B
60
44.7
91.3
1
3
026F
56
51.4
61.6
1
5
02AE
56
48.6
66.1
1
7
02ED
56
46.1
71.4
1
9
032C
56
43.8
77.6
1
11
036B
56
41.8
84.9
1
13
03AA
56
39.9
93.8
2
3
046E
56
48.6
66.1
2
5
04AC
56
43.8
77.6
2
7
04EA
56
39.9
93.8
3
3
066D
56
46.1
71.4
3
5
06AA
56
39.9
93.8
4
3
086C
56
43.8
77.6
5
3
0A6B
56
41.8
84.9
6
3
0C6A
56
39.9
93.8
1
3
026F
52
47.8
57
1
5
02AE
52
45.2
61.2
1
7
02ED
52
42.9
66.1
1
9
032C
52
40.8
71.8
1
11
036B
52
38.8
78.6
1
13
03AA
52
37.1
86.8
1
15
03E9
52
35.5
96.9
Remarks
(Continued)
98
DS07-16617-2E
MB91460S Series
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
2
3
046E
52
45.2
61.2
2
5
04AC
52
40.8
71.8
2
7
04EA
52
37.1
86.8
3
3
066D
52
42.9
66.1
3
5
06AA
52
37.1
86.8
4
3
086C
52
40.8
71.8
5
3
0A6B
52
38.8
78.6
6
3
0C6A
52
37.1
86.8
7
3
0E69
52
35.5
96.9
1
3
026F
48
44.2
52.5
1
5
02AE
48
41.8
56.4
1
7
02ED
48
39.6
60.9
1
9
032C
48
37.7
66.1
1
11
036B
48
35.9
72.3
1
13
03AA
48
34.3
79.9
1
15
03E9
48
32.8
89.1
2
3
046E
48
41.8
56.4
2
5
04AC
48
37.7
66.1
2
7
04EA
48
34.3
79.9
3
3
066D
48
39.6
60.9
3
5
06AA
48
34.3
79.9
4
3
086C
48
37.7
66.1
5
3
0A6B
48
35.9
72.3
6
3
0C6A
48
34.3
79.9
7
3
0E69
48
32.8
89.1
1
3
026F
44
40.6
48.1
1
5
02AE
44
38.4
51.6
1
7
02ED
44
36.4
55.7
1
9
032C
44
34.6
60.4
1
11
036B
44
33
66.1
1
13
03AA
44
31.5
73
1
15
03E9
44
30.1
81.4
2
3
046E
44
38.4
51.6
2
5
04AC
44
34.6
60.4
2
7
04EA
44
31.5
73
Remarks
(Continued)
DS07-16617-2E
99
MB91460S Series
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
2
9
0528
44
28.9
92.1
3
3
066D
44
36.4
55.7
3
5
06AA
44
31.5
73
4
3
086C
44
34.6
60.4
4
5
08A8
44
28.9
92.1
5
3
0A6B
44
33
66.1
6
3
0C6A
44
31.5
73
7
3
0E69
44
30.1
81.4
8
3
1068
44
28.9
92.1
1
3
026F
40
37
43.6
1
5
02AE
40
34.9
46.8
1
7
02ED
40
33.1
50.5
1
9
032C
40
31.5
54.8
1
11
036B
40
30
59.9
1
13
03AA
40
28.7
66.1
1
15
03E9
40
27.4
73.7
2
3
046E
40
34.9
46.8
2
5
04AC
40
31.5
54.8
2
7
04EA
40
28.7
66.1
2
9
0528
40
26.3
83.3
3
3
066D
40
33.1
50.5
3
5
06AA
40
28.7
66.1
3
7
06E7
40
25.3
95.8
4
3
086C
40
31.5
54.8
4
5
08A8
40
26.3
83.3
5
3
0A6B
40
30
59.9
6
3
0C6A
40
28.7
66.1
7
3
0E69
40
27.4
73.7
8
3
1068
40
26.3
83.3
9
3
1267
40
25.3
95.8
1
3
026F
36
33.3
39.2
1
5
02AE
36
31.5
42
1
7
02ED
36
29.9
45.3
1
9
032C
36
28.4
49.2
1
11
036B
36
27.1
53.8
Remarks
(Continued)
100
DS07-16617-2E
MB91460S Series
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
13
03AA
36
25.8
59.3
1
15
03E9
36
24.7
66.1
2
3
046E
36
31.5
42
2
5
04AC
36
28.4
49.2
2
7
04EA
36
25.8
59.3
2
9
0528
36
23.7
74.7
3
3
066D
36
29.9
45.3
3
5
06AA
36
25.8
59.3
3
7
06E7
36
22.8
85.8
4
3
086C
36
28.4
49.2
4
5
08A8
36
23.7
74.7
5
3
0A6B
36
27.1
53.8
6
3
0C6A
36
25.8
59.3
7
3
0E69
36
24.7
66.1
8
3
1068
36
23.7
74.7
9
3
1267
36
22.8
85.8
1
3
026F
32
29.7
34.7
1
5
02AE
32
28
37.3
1
7
02ED
32
26.6
40.2
1
9
032C
32
25.3
43.6
1
11
036B
32
24.1
47.7
1
13
03AA
32
23
52.5
1
15
03E9
32
22
58.6
2
3
046E
32
28
37.3
2
5
04AC
32
25.3
43.6
2
7
04EA
32
23
52.5
2
9
0528
32
21.1
66.1
2
11
0566
32
19.5
89.1
3
3
066D
32
26.6
40.2
3
5
06AA
32
23
52.5
3
7
06E7
32
20.3
75.9
4
3
086C
32
25.3
43.6
4
5
08A8
32
21.1
66.1
5
3
0A6B
32
24.1
47.7
5
5
0AA6
32
19.5
89.1
Remarks
(Continued)
DS07-16617-2E
101
MB91460S Series
(Continued)
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
6
3
0C6A
32
23
52.5
7
3
0E69
32
22
58.6
8
3
1068
32
21.1
66.1
9
3
1267
32
20.3
75.9
10
3
1466
32
19.5
89.1
102
Remarks
DS07-16617-2E
MB91460S Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute maximum ratings
Parameter
Symbol
Rating
Min
Max
Unit
⎯
⎯
50
V/ms
1
VDD5R
− 0.3
+ 6.0
V
1
VDD5
− 0.3
+ 6.0
V
Power supply voltage 3*
1
VDD35
− 0.3
+ 6.0
V
Power supply voltage 4*
1,7
Power supply slew rate
Power supply voltage 1*
Power supply voltage 2*
Relationship of the supply
voltages
VDDA
Remarks
V
VDD5-0.3
VDD5+0.3
V
At least one pin of the
Ports 28 to 29 (ANn) is
used as digital input or
output
VSS5-0.3
VDD5+0.3
V
All pins of the Ports 28 to
29 (ANn) follow the condition of VIA
AVCC5
Analog power supply voltage*1
AVCC5
− 0.3
+ 6.0
V
*2
Analog reference
power supply voltage*1
AVRH5
− 0.3
+ 6.0
V
*2
VI1
Vss5 − 0.3
VDD5 + 0.3
V
VI2
Vss5 − 0.3
VDD35 + 0.3
V
Input voltage 1*1
1
Input voltage 2*
External bus
VIA
AVss − 0.3
AVcc5 + 0.3
V
Output voltage 1*
1
VO1
Vss5 − 0.3
VDD5 + 0.3
V
Output voltage 2*
1
VO2
Vss5 − 0.3
VDD35 + 0.3
V
ICLAMP
− 4.0
+ 4.0
mA
*3
Σ |ICLAMP|
⎯
20
mA
*3
IOL
⎯
10
mA
“L” level average
output current*5
IOLAV
⎯
8
mA
“L” level total maximum
output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH
⎯
-10
mA
“H” level average
output current*5
IOHAV
⎯
−4
mA
“H” level total maximum
output current
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 25
mA
Analog pin input voltage*
1
Maximum clamp current
Total maximum clamp current
“L” level maximum
output current*4
“L” level total average
output current*6
“H” level maximum
output current*4
“H” level total average output
current*6
External bus
(Continued)
DS07-16617-2E
103
MB91460S Series
(Continued)
Parameter
Symbol
Rating
Min
Max
Unit
Power consumption
PD
⎯
1000
mW
Operating temperature
TA
− 40
+ 105
°C
Tstg
− 55
+ 150
°C
Storage temperature
Remarks
*1 : The parameter is based on VSS5 = AVSS5 = 0.0 V.
*2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V.
*3 : •Use within recommended operating conditions.
•Use with DC voltage (current).
•+B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by
connecting a limiting resistor between the +B signal and the microcontroller.
•The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed the rated value at any time, either instantaneously or for an extended period, when the +B signal
is input.
•Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting
other devices.
•Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through
the +B input pin; therefore, the microcontroller may partially operate.
•Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset
may not function in the power supply voltage.
•Do not leave +B input pins open.
•Example of recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
Limiting
resistor
P-ch
+B input (0 V to 16 V)
N-ch
R
*4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding
pins.
*5 : Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period.
*6 : Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
104
DS07-16617-2E
MB91460S Series
2. Recommended operating conditions
(VSS5 = AVSS5 = 0.0 V)
Parameter
Power supply voltage
Symbol
Value
Unit
Remarks
Min
Typ
Max
VDD5
3.0
⎯
5.5
V
VDD5R
3.0
⎯
5.5
V
Internal regulator
VDD35
3.0
⎯
5.5
V
External bus
VDDA
1.7
⎯
1.9
V
APIX®
VPPA
⎯
⎯
50
mV
AVCC5
3.0
⎯
5.5
V
A/D converter
Use a X7R ceramic capacitor or
a capacitor that has similar frequency characteristics. Use a capacitor with a capacitance
greater than Cs as the smoothing
capacitor on the supply pin.
Smoothing capacitor
CS
⎯
4.7
⎯
μF
Power supply slew rate
⎯
⎯
⎯
50
V/ms
Operating temperature
TA
− 40
⎯
+ 105
°C
Main Oscillation
stabilization time
10
⎯
⎯
ms
Lock-up time PLL
(4 MHz ->16 ...100MHz)
⎯
⎯
0.6
ms
kV
ESD Protection
(Human body model)
Vsurge
2
⎯
⎯
RC Oscillator
fRC100kHz
fRC2MHz
50
1
100
2
200
4
VDDA, VSSA peak-peak supply
noise
Rdischarge = 1.5kΩ
Cdischarge = 100pF
kHz
VDDCORE ≥ 1.65V
MHz
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-16617-2E
105
MB91460S Series
VCC18C
VSS5
AVSS5
CS
106
DS07-16617-2E
MB91460S Series
3. DC characteristics
Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or VDD5 for other pins.
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter Symbol
Pin name
Value
Min
Unit
Remarks
Typ
Max
⎯
VDD + 0.3
V
CMOS
hysteresis
input
⎯
VDD + 0.3
V
4.5 V ≤ VDD ≤ 5.5 V
⎯
VDD + 0.3
⎯
Port inputs if CMOS
Hysteresis 0.8/0.2 0.8 × VDD
input is selected
⎯
Port inputs if CMOS 0.7 × VDD
Hysteresis 0.7/0.3
0.74 × VDD
input is selected
⎯
AUTOMOTIVE
Hysteresis input is
selected
0.8 × VDD
⎯
VDD + 0.3
V
⎯
Port inputs if TTL
input is selected
2.0
⎯
VDD + 0.3
V
VIH
Input “H”
voltage
Condition
3 V ≤ VDD < 4.5 V
VIHR
INITX
⎯
0.8 × VDD
⎯
VDD + 0.3
V
INITX input pin
(CMOS
Hysteresis)
VIHM
MD2 to MD0
⎯
VDD − 0.3
⎯
VDD + 0.3
V
MDx input pins
VIHX0S
X0, X0A
⎯
2.5
⎯
VDD + 0.3
V
External clock in
“Oscillation mode”
VIHX0F
X0
⎯
0.8 × VDD
⎯
VDD + 0.3
V
External clock in
“Fast Clock Input
mode”
⎯
Port inputs if CMOS
Hysteresis 0.8/0.2 VSS5 − 0.3
input is selected
⎯
0.2 × VDD
V
⎯
Port inputs if CMOS
Hysteresis 0.7/0.3 VSS5 − 0.3
input is selected
⎯
0.3 × VDD
V
VSS5 − 0.3
⎯
0.5 × VDD
V
4.5 V ≤ VDD ≤ 5.5 V
⎯
Port inputs if
AUTOMOTIVE
Hysteresis input is
selected
VSS5 − 0.3
⎯
0.46 × VDD
V
3 V ≤ VDD < 4.5 V
⎯
Port inputs if TTL
input is selected
VSS5 − 0.3
⎯
0.8
V
VIL
Input “L”
voltage
VILR
INITX
⎯
VSS5 − 0.3
⎯
0.2 × VDD
V
INITX input pin
(CMOS
Hysteresis)
VILM
MD2 to MD0
⎯
VSS5 − 0.3
⎯
VSS5 + 0.3
V
MDx input pins
VILXDS
X0, X0A
⎯
VSS5 − 0.3
⎯
0.5
V
External clock in
“Oscillation mode”
(Continued)
DS07-16617-2E
107
MB91460S Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter Symbol
Input “L”
voltage
Output “H”
voltage
Pin
name
Condition
X0
⎯
Value
Unit
Remarks
0.2 × VDD
V
External clock in
“Fast Clock Input
mode”
⎯
⎯
V
Driving strength
set to 2 mA
VDD − 0.5
⎯
⎯
V
Driving strength
set to 5 mA
VDD − 0.5
⎯
⎯
V
VDD − 0.5
⎯
⎯
V
Driving strength
set to 30mA
⎯
⎯
0.4
V
Driving strength
set to 2 mA
VOL5
4.5V ≤ VDD ≤ 5.5V,
I
Normal OL = + 5mA
outputs 3.0V ≤ VDD < 4.5V,
IOL = + 3mA
⎯
⎯
0.4
V
Driving strength
set to 5 mA
VOL3
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOL = + 3mA
⎯
⎯
0.4
V
⎯
⎯
0.5
V
Min
Typ
Max
VSS5 − 0.3
⎯
VOH2
4.5V ≤ VDD ≤ 5.5V,
I
Normal OH = − 2mA
outputs 3.0V ≤ VDD < 4.5V,
IOH = − 1.6mA
VDD − 0.5
VOH5
4.5V ≤ VDD ≤ 5.5V,
Normal IOH = − 5mA
outputs 3.0V ≤ VDD < 4.5V,
IOH = − 3mA
VOH3
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOH = − 3mA
VILXDF
4.5V ≤ VDD ≤ 5.5V,
TA = -40 °C,
IOH = -40mA
VOH30
VOL2
Output “L“
voltage
High
current 4.5V ≤ VDD ≤ 5.5V,
outputs IOH = -30mA
3.0V ≤ VDD < 4.5V,
IOH = -20mA
4.5V ≤ VDD ≤ 5.5V,
Normal IOL = + 2mA
outputs 3.0V ≤ VDD < 4.5V,
IOL = + 1.6mA
4.5V ≤ VDD ≤ 5.5V,
TA = -40 °C,
IOL = +40mA
VOL30
High
current 4.5V ≤ VDD ≤ 5.5V,
outputs IOL = +30mA
Driving strength
set to 30mA
3.0V ≤ VDD < 4.5V,
IOL = +20mA
(Continued)
108
DS07-16617-2E
MB91460S Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter Symbol
Pin
name
Input leakage current
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
Pnn_m TA = 25 °C
*1
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
TA = 105 °C
IIL
Analog input leakage current
IAIN
ADIN
Condition
Value
Min
Typ
Max
−1
⎯
+1
−3
⎯
+3
3.0V ≤ VDD ≤ 5.5V
AVSS5 ≤ VI ≤ AVCC5
TA = 25 °C
−1
⎯
+1
3.0V ≤ VDD ≤ 5.5V
AVSS5 ≤ VI ≤ AVCC5
TA = 105 °C
−3
⎯
+3
⎯
13
130
μA
Sum input
leakage
Σ IL
Pull-up
resistance
Pnn_m 3.0V ≤ VDD ≤ 3.6V
*1,
INITX 4.5V ≤ VDD ≤ 5.5V
40
100
160
RUP
25
50
100
Pull-down
resistance
RDOWN
Pnn_m 3.0V ≤ VDD ≤ 3.6V
*1
4.5V ≤ VDD ≤ 5.5V
40
100
160
25
50
100
RTERM
SDINM
SDINP
SDOUTM
SDOUTMP
35
⎯
65
⎯
Remarks
μA
VDD5 ≥ VIN ≥ VSS5
AVCC5, AVRH5 ≥
VIN ≥ AVSS5
Pnn_m Σ (1 to n) [max (|ILALARM
Hi|, |ILLi|)]
(n = number of IO =
133 GPIO + 1
ALARM)
APIX®
terminal
resistance
Unit
μA
kΩ
kΩ
Ω
(Continued)
DS07-16617-2E
109
MB91460S Series
(Continued)
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter Symbol
Pin
name
Condition
Value
Min
Typ
Max
Unit
Remarks
(Conditions at
MB91F467SA)
ICC
VDD5R
⎯
⎯
125
155
mA
CLKB:
100
MHz
CLKP: 50 MHz
CLKT: 50 MHz
CLKCAN: 40
MHz
Code fetch from
Flash
VDDA
Power
supply
current
VDD5R
ICCH
⎯
12
60
TA = + 25 °C
⎯
30
150
μA
TA = + 105 °C
⎯
400
2000
μA
TA = + 25 °C
⎯
100
500
μA
TA = + 105 °C
⎯
500
2400
μA
TA = + 25 °C
⎯
50
250
μA
TA = + 105 °C
⎯
450
2200
μA
RTC :
100 kHz mode *2
APIX®
At stop mode *2
RTC :
4 MHz mode *2
VDDA
⎯
⎯
10
50
μA
APIX® powerdown
ILVE
VDD5
⎯
⎯
70
150
μA
External low voltage
detection
ILVI
VDD5R
⎯
⎯
50
100
μA
Internal low voltage
detection
⎯
⎯
250
500
μA
Main clock
(4 MHz)
⎯
⎯
20
40
μA
Sub clock
(32 kHz)
⎯
5
15
pF
IOSC
Input
capacitance
⎯
CIN
VDD5
All except
VDD5,
VDD5R,
VSS5, f = 1 MHz
AVCC5,
AVSS,
VDDA,
VSSA,
*1 Pnn_m includes all pins unless the pins, which include analog inputs.
*2
110
Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
DS07-16617-2E
MB91460S Series
4. A/D converter characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol Pin name
Value
Min
Typ
Max
Unit
Remarks
Resolution
⎯
⎯
⎯
⎯
10
bit
Total error
⎯
⎯
−3
⎯
+3
LSB
Nonlinearity error
⎯
⎯
− 2.5
⎯
+ 2.5
LSB
Differential nonlinearity
error
⎯
⎯
− 1.9
⎯
+ 1.9
LSB
Zero reading voltage
VOT
ANn
AVRL−
1.5 LSB
AVRL +
0.5 LSB
AVRL +
2.5 LSB
V
Full scale reading voltage
VFST
ANn
AVRH−
3.5 LSB
AVRH−
1.5 LSB
AVRH +
0.5 LSB
V
1.0
⎯
16,500
μs
4.5 V ≤ AVCC5 ≤
5.5 V
2.0
⎯
⎯
μs
3.0 V ≤ AVCC5 <
4.5 V
0.4
⎯
⎯
μs
4.5 V ≤ AVCC5 ≤
5.5 V,
REXT < 2 kΩ
1.0
⎯
⎯
μs
3.0 V ≤ AVCC5 <
4.5 V,
REXT < 1 kΩ
1.4
⎯
⎯
μs
4.5 V ≤ AVCC5 ≤
5.5 V
3.0
⎯
⎯
μs
3.0 V ≤ AVCC5 <
4.5 V
⎯
⎯
11
pF
⎯
⎯
2.6
kΩ
4.5 V ≤ AVCC5 ≤
5.5 V
⎯
⎯
12.1
kΩ
3.0 V ≤ AVCC5 <
4.5 V
−1
⎯
+1
μA
TA = + 25 °C
−3
⎯
+3
μA
TA = + 105 °C
Compare time
Sampling time
Conversion time
Input capacitance
Input resistance
Tcomp
Tsamp
Tconv
CIN
RIN
⎯
⎯
⎯
ANn
ANn
Analog input leakage
current
IAIN
ANn
Analog input voltage range
VAIN
ANn
AVRL
⎯
AVRH
V
Offset between input channels
⎯
ANn
⎯
⎯
4
LSB
(Continued)
Note : The accuracy gets worse as AVRH - AVRL becomes smaller
DS07-16617-2E
111
MB91460S Series
(Continued)
Parameter
Symbol Pin name
Reference voltage current
per ADC macro *3
Min
Typ
Max
Unit
Remarks
AVRH
AVRH5
0.75 ×
AVCC5
⎯
AVCC5
V
AVRL
AVSS5
AVSS5
⎯
AVCC5 ×
0.25
V
IA
AVCC5
⎯
2.5
5
mA
A/D Converter
active
IAH
AVCC5
⎯
⎯
5
μA
A/D Converter
not operated *1
IR
AVRH5
⎯
0.7
1
mA
A/D Converter
active
IRH
AVRH5
⎯
⎯
5
μA
A/D Converter
not operated *2
Reference voltage range
Power supply current
per ADC macro *3
Value
*1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating,
(VDD5 = AVCC5 = AVRH = 5.0 V)
*2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
*3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the
current values have to be multiplied by the number of macros.
Sampling Time Calculation
Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V
Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V ≤ AVCC5 < 4.5V
Conversion Time Calculation
Tconv = Tsamp + Tcomp
Definition of A/D converter terms
• Resolution
Analog variation that is recognizable by the A/D converter.
• Nonlinearity error
Deviation between actual conversion characteristics and a straight line connecting the zero transition point
(00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B).
• Differential nonlinearity error
Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.
• Total error
This error indicates the difference between actual and theoretical values, including the zero transition error,
full scale transition error, and nonlinearity error.
112
DS07-16617-2E
MB91460S Series
Total error
3FFH
1.5 LSB’
3FEH
Actual conversion
characteristics
Digital output
3FDH
{1 LSB’ (N - 1) + 0.5 LSB’}
004H
VNT
003H
(measurement value)
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS5
AVRH
Analog input
1LSB' (ideal value) = AVRH − AVSS5 [V]
1024
Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'}
1 LSB'
N : A/D converter digital output value
VOT' (ideal value) = AVSS5 + 0.5 LSB' [V]
VFST' (ideal value) = AVRH − 1.5 LSB' [V]
VNT : Voltage at which the digital output changes from (N + 1) H to NH
(Continued)
DS07-16617-2E
113
MB91460S Series
(Continued)
Nonlinearity error
3FFH
Differential nonlinearity error
Actual conversion characteristics
Actual conversion characteristics
(N+1)H
3FEH
{1 LSB (N - 1) + VOT}
VFST
004H
VNT
(measurement value)
003H
002H
Ideal
characteristics
(measurement value)
Digital output
Digital output
3FDH
NH
(N-1)H
VFST
Actual conversion
characteristics
VNT
(measurement value)
Ideal characteristics
(N-2)H
001H
Actual conversion
characteristics
VTO (measurement value)
AVSS5
AVSS5
AVRH
Analog input
Nonlinearity error of digital output N =
VFST − VOT
1022
AVRH
Analog input
VNT − {1LSB × (N − 1) + VOT} [LSB]
1LSB
Differential nonlinearity error of digital output N =
1LSB =
(measurement value)
V (N + 1) T − VNT
1LSB
− 1 [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which the digital output changes from 000H to 001H.
VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
114
DS07-16617-2E
MB91460S Series
5. Alarm comparator characteristics
Parameter
Symbol
Pin name
Min
⎯
IA5ALMF
Power supply
current
Value
Typ
25
Max
40
Unit
Remarks
μA
Alarm comparator enabled in
fast mode
(one channel)
IA5ALMS
⎯
7
10
μA
Alarm comparator enabled in
fast mode
(one channel)
IA5ALMH
⎯
⎯
5
μA
Alarm comparator disabled
−1
⎯
+1
−3
⎯
+3
AVCC5
TA = + 25 °C
ALARM pin input current
IALIN
ALARM pin input voltage
range
VALIN
0
⎯
AVCC5
V
Alarm upper
limit
voltage
VIAH
AVCC5 × 0.78
− 3%
AVCC5 × 0.78
AVCC5 × 0.78
+ 3%
V
Alarm lower
limit
voltage
VIAL
AVCC5 × 0.36
− 5%
AVCC5 × 0.36
AVCC5 × 0.36
+ 5%
V
VIAHYS
50
⎯
250
mV
RIN
5
⎯
⎯
MΩ
tCOMPF
⎯
0.1
0.2
μs
ACSR.MD=1
tCOMPS
⎯
1
2
μs
ACSR.MD=0
Alarm hysteresis
voltage
Alarm input
resistance
Comparison
time
DS07-16617-2E
ALARM
μA
TA = + 105 °C
115
MB91460S Series
6. FLASH memory program/erase characteristics
6.1.
MB91F467SA
(TA = 25oC, Vcc = 5.0V)
Parameter
Value
Unit
Remarks
2.0
s
Erasure programming time not
included
n*0.5
n*2.0
s
n is the number of Flash sector
of the device
6
100
μs
System overhead time not included
Min
Typ
Max
Sector erase time
-
0.5
Chip erase time
-
Word (16-bit width) programming time
-
Programme/Erase cycle
10 000
cycle
Flash data retention time
20
year
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
116
DS07-16617-2E
MB91460S Series
7. AC characteristics
7.1.
Clock timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Clock frequency
Symbol Pin name
fC
Value
Unit
Condition
16
MHz
Opposite phase external
supply or crystal
100
kHz
Min
Typ
Max
X0
X1
3.5
4
X0A
X1A
32
32.768
• Clock timing condition
tC
X0,
X1,
X0A,
X1A
0.8 VCC
0.2 VCC
PWH
DS07-16617-2E
PWL
117
MB91460S Series
7.2.
Reset input ratings
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
INITX input time
(at power-on)
INITX input time
(other than the above)
Symbol
tINTL
Pin name
Condition
Value
Unit
Min
Max
8
⎯
ms
20
⎯
μs
⎯
INITX
tINTL
INITX
118
0.2 VCC
DS07-16617-2E
MB91460S Series
7.3.
LIN-USART Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
• All AC tests were measured under the following conditions:
• - IOdrive = 5 mA
• - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
• - VSS5 = 0 V
• - Ta = -40 °C to +105 °C
• - Cl = 50 pF (load capacity value of pins when testing)
• - VOL = 0.2 x VDD5,
• - VOH = 0.8 x VDD5
• - EPILR = 0, PILR = 1 (Automotive Level = worst case)
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
Serial clock
cycle time
tSCYCI
SCKn
SCK ↓ → SOT
delay time
tSLOVI
SCKn
SOTn
SOT → SCK ↓
delay time
tOVSHI
SCKn
SOTn
Valid SIN →
SCK ↑ setup time
tIVSHI
SCKn
SINn
SCK ↑ → valid
SIN hold time
tSHIXI
Serial clock
“H” pulse width
Condition
VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V
Unit
Min
Max
Min
Max
4 tCLKP
⎯
4 tCLKP
⎯
ns
− 30
30
− 20
20
ns
m×
tCLKP − 30*
⎯
m×
tCLKP − 20*
⎯
ns
tCLKP + 55
⎯
tCLKP + 45
⎯
ns
SCKn
SINn
0
⎯
0
⎯
ns
tSHSLE
SCKn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
Serial clock
“L” pulse width
tSLSHE
SCKn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
SCK ↓ → SOT
delay time
tSLOVE
SCKn
SOTn
⎯
2 tCLKP + 55
⎯
2 tCLKP + 45
ns
Valid SIN →
SCK ↑ setup time
tIVSHE
SCKn
SINn
10
⎯
10
⎯
ns
SCK ↑ → valid
SIN hold time
tSHIXE
SCKn
SINn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
SCK rising time
tFE
SCKn
⎯
20
⎯
20
ns
SCK falling time
tRE
SCKn
⎯
20
⎯
20
ns
Internal
clock
operation
(master
mode)
External
clock
operation
(slave
mode)
* : Parameter m depends on tSCYCI and can be calculated as :
• if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2
• if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1
Notes : • The above values are AC characteristics for CLK synchronous mode.
• tCLKP is the cycle time of the peripheral clock.
DS07-16617-2E
119
MB91460S Series
• Internal clock mode (master mode)
tSCYCI
SCKn
for ESCR:SCES = 0
VOH
VOL
VOL
VOH
SCKn
for ESCR:SCES = 1
VOH
VOL
tSLOVI
tOVSHI
VOH
VOL
SOTn
tIVSHI
tSHIXI
VIH
VIL
SINn
VIH
VIL
• External clock mode (slave mode)
tSLSHE
SCKn
for ESCR:SCES = 0
VOH
SCKn
for ESCR:SCES = 1
VOL
tSHSLE
VOH
VOL
VOL
VOH
VOH
VOL
VOH
VOL
tRE
tFE
tSLOVE
SOTn
VOH
VOL
tIVSHE
SINn
120
VIH
VIL
tSHIXE
VIH
VIL
DS07-16617-2E
MB91460S Series
7.4.
I2C AC Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 3 mA
- VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta = − 40 °C to + 105 °C
- Cl = 50 pF
- VOL = 0.3 × VDD5,
VOH = 0.7 × VDD5
- EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5)
Fast mode:
(VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
fSCL
Value
Unit
Min
Max
SCLn
0
400
kHz
tHD;STA
SCLn, SDAn
0.6
⎯
μs
LOW period of the SCL clock
tLOW
SCLn
1.3
⎯
μs
HIGH period of the SCL clock
tHIGH
SCLn
0.6
⎯
μs
Setup time for a repeated START
condition
tSU;STA
SCLn, SDAn
0.6
⎯
μs
Data hold time for I2C-bus devices
tHD;DAT
SCLn, SDAn
0
0.9
μs
Data setup time
tSU;DAT
SCLn SDAn
100
⎯
ns
Rise time of both SDA and SCL
signals
tr
SCLn, SDAn
20 + 0.1Cb
300
ns
Fall time of both SDA and SCL
signals
tf
SCLn, SDAn
20 + 0.1Cb
300
ns
Setup time for STOP condition
tSU;STO
SCLn, SDAn
0.6
⎯
μs
Bus free time between a STOP
and START condition
tBUF
SCLn, SDAn
1.3
⎯
μs
Capacitive load for each bus line
Cb
SCLn, SDAn
⎯
400
pF
Pulse width of spike suppressed
by input filter
tSP
SCLn, SDAn
0
(1..1.5) ×
tCLKP
ns
SCL clock frequency
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
Remark
*1
*1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles
of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
DS07-16617-2E
121
122
SCL
SDA
tHD;STA
tf
S
tr
tHD;DAT
tLOW
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSP
tr
P
tSU;ST0
tBUF
S
tf
MB91460S Series
DS07-16617-2E
MB91460S Series
7.5.
Free-run timer clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
CKn
⎯
Value
Min
Max
4tCLKP
⎯
Unit
ns
Note : tCLKP is the cycle time of the peripheral clock.
CKn
VIH
VIH
tTIWH
7.6.
VIL
VIL
tTIWL
Trigger input timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Input capture input trigger
A/D converter trigger
Symbol
Pin name
Condition
tINP
ICUn
tATGX
ATGX
Value
Unit
Min
Max
⎯
5tCLKP
⎯
ns
⎯
5tCLKP
⎯
ns
Note : tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn,
ATGX
DS07-16617-2E
123
MB91460S Series
7.7.
External Bus AC Timings at VDD35 = 4.5 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD35 = 4.5 V to 5.5 V, Iload = 5 mA
- VSS5 = 0 V
- Ta = − 40 °C to + 105 °C
- Cl = 50 pF
- VOL = 0.2 × VDD35,
VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
7.7.1.
Basic Timing
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK
SYSCLK ↓ to CSXn delay time
SYSCLK ↑ to CSXn delay time
(Addr → CS delay)
SYSCLK ↓ to ASX delay time
SYSCLK ↓ to Address valid delay time
Symbol
tCLCH
tCHCL
Pin name
Max
1/2 x tCLKT − 1
1/2 × tCLKT + 1
ns
1/2 × tCLKT − 1
1/2 × tCLKT + 1
ns
⎯
5
ns
⎯
5
ns
3
7
ns
SYSCLK
ASX
⎯
5
ns
⎯
5
ns
SYSCLK
A23 to A0
⎯
7
ns
SYSCLK
SYSCLK
CSXn
tCHCSL
tCLASL
tCLASH
tCLAV
Unit
Min
tCLCSL
tCLCSH
Value
Note : tCLKT is the cycle time of the external bus clock.
124
DS07-16617-2E
MB91460S Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL
tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
DS07-16617-2E
125
MB91460S Series
7.7.2.
Synchronous/Asynchronous read access
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
TCHRL
SYSCLK ↑ to RDX delay time
TCHRH
Pin name
SYSCLK RDX
Value
Unit
Min
Max
2
5
ns
2
5
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D16
12
⎯
ns
RDX ↑ to Data valid hold time
TRHDX
RDX
D31 to D16
0
⎯
ns
SYSCLK
WRXn
⎯
5
ns
2
⎯
ns
SYSCLK
CSXn
⎯
5
ns
⎯
5
ns
TCLWRL
SYSCLK ↓ to WRXn
(as byte enable) delay time
TCLWRH
TCLCSL
SYSCLK ↓ to CSXn delay time
TCLCSH
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tRHDX
DATA IN
126
DS07-16617-2E
MB91460S Series
7.7.3.
Synchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↓ to WEX delay time
Symbol
Pin name
TCLWL
TCLWH
Value
Unit
Min
Max
SYSCLK
WEX
⎯
5
ns
2
⎯
ns
Data valid to WEX ↓ setup time
TDSWL
WEX
D31 to D16
−1
⎯
ns
WEX ↑ to Data valid hold time
TWHDH
WEX
D31 to D16
tCLKT − 1
⎯
ns
SYSCLK ↓ to WRXn (as byte enable)
delay time
TCLWRL
SYSCLK
WRXn
⎯
5
ns
2
⎯
ns
SYSCLK
CSXn
⎯
5
ns
⎯
5
ns
SYSCLK ↓ to CSXn delay time
TCLWRH
TCLCSL
TCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCLWH
tCLWL
WEX
tDSWL
tWHDH
DATA OUT
DS07-16617-2E
127
MB91460S Series
7.7.4.
Synchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↓ to WRXn delay time
Symbol
Pin name
TCLWRL
TCLWRH
Value
Unit
Min
Max
SYSCLK
WRXn
⎯
5
ns
2
⎯
ns
Data valid to WRXn ↓ setup time
TDSWRL
WRXn
D31 to D16
−1
⎯
ns
WRXn ↑ to Data valid hold time
TWRHDH
WRXn
D31 to D16
tCLKT − 1
⎯
ns
SYSCLK
CSXn
⎯
5
ns
⎯
5
ns
SYSCLK ↓ to CSXn delay time
TCLCSL
TCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
128
DS07-16617-2E
MB91460S Series
7.7.5.
Asynchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
TWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT − 1
⎯
ns
TDSWL
WEX
D31 to D16
1/2 × tCLKT − 1
⎯
ns
TWHDH
WEX
D31 to D16
1/2 × tCLKT − 1
⎯
ns
WEX
WRXn
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT − 1
⎯
ns
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT − 1
⎯
ns
TWRLWL
TWHWRH
TCLWL
TWHCH
WEX
CSXn
CSXn
tWHCH
tCLWL
WRXn
(as byte enable)
tWHWRH
tWRLWL
tWLWH
WEX
tDSWL
tWHDH
DATA OUT
DS07-16617-2E
129
MB91460S Series
7.7.6.
Asynchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
TWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT − 1
⎯
ns
TDSWRL
WRXn
D31 to D16
1/2 × tCLKT − 1
⎯
ns
TWRHDH
WRXn
D31 to D16
1/2 × tCLKT − 1
⎯
ns
WRXn
CSXn
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT − 1
⎯
ns
TCLWRL
TWRHCH
CSXn
TWRHCH
TCLWRL
TWRLWRH
WRXn
TDSWRL
TWRHDH
DATA OUT
130
DS07-16617-2E
MB91460S Series
7.7.7.
RDY waitcycle insertion
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
RDY setup time
TRDYS
RDY hold time
TRDYH
Value
Unit
Min
Max
SYSCLK
RDY
8
⎯
ns
SYSCLK
RDY
0
⎯
ns
SYSCLK
tRDYS
tRDYH
RDY
DS07-16617-2E
131
MB91460S Series
7.8.
External Bus AC Timings at VDD35 = 3.0 to 4.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD35 = 3.0 V to 4.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta = − 40 °C to + 105 °C
- Cl = 50 pF
- VOL = 0.2 × VDD35,
VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
7.8.1.
Basic Timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK
SYSCLK ↓ to CSXn delay time
SYSCLK ↑ to CSXn delay time
(Addr → CS delay)
SYSCLK ↓ to ASX delay time
SYSCLK ↓ to Address valid delay
time
132
Symbol
TCLCH
TCHCL
Pin name
Max
1/2 × tCLKT
1/2 × tCLKT + 2
ns
1/2 × tCLKT − 2
1/2 × tCLKT
ns
⎯
11
ns
⎯
7
ns
2
6
ns
SYSCLK
ASX
⎯
6
ns
⎯
7
ns
SYSCLK
A23 to A0
⎯
13
ns
SYSCLK
SYSCLK
CSXn
TCHCSL
TCLASL
TCLASH
TCLAV
Unit
Min
TCLCSL
TCLCSH
Value
DS07-16617-2E
MB91460S Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL
tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
DS07-16617-2E
133
MB91460S Series
7.8.2.
Synchronous/Asynchronous read access
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↑ to RDX delay time
Symbol
Pin name
TCHRL
SYSCLK
RDX
TCHRH
Value
Unit
Min
Max
1
4
ns
2
6
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D16
16
⎯
ns
RDX ↑ to Data valid hold time
TRHDX
RDX
D31 to D16
0
⎯
ns
SYSCLK
WRXn
⎯
6
ns
3
⎯
ns
SYSCLK
CSXn
⎯
11
ns
⎯
7
ns
TCLWRL
SYSCLK ↓ to WRXn
(as byte enable) delay time
TCLWRH
TCLCSL
SYSCLK ↓ to CSXn delay time
TCLCSH
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tRHDX
DATA IN
134
DS07-16617-2E
MB91460S Series
7.8.3.
Synchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↓ to WEX delay time
Symbol
Pin name
TCLWL
TCLWH
Value
Unit
Min
Max
SYSCLK
WEX
⎯
6
ns
3
⎯
ns
Data valid to WEX ↓ setup time
TDSWL
WEX
D31 to D16
−7
⎯
ns
WEX ↑ to Data valid hold time
TWHDH
WEX
D31 to D16
tCLKT − 3
⎯
ns
SYSCLK ↓ to WRXn (as byte enable)
delay time
TCLWRL
SYSCLK
WRXn
⎯
6
ns
3
⎯
ns
SYSCLK
CSXn
⎯
11
ns
⎯
7
ns
SYSCLK ↓ to CSXn delay time
TCLWRH
TCLCSL
TCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCLWH
tCLWL
WEX
tDSWL
tWHDH
DATA OUT
DS07-16617-2E
135
MB91460S Series
7.8.4.
Synchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↓ to WRXn delay time
Symbol
Pin name
TCLWRL
TCLWRH
Value
Unit
Min
Max
SYSCLK
WRXn
⎯
6
ns
3
⎯
ns
Data valid to WRXn ↓ setup time
TDSWRL
WRXn
D31 to D16
−7
⎯
ns
WRXn ↑ to Data valid hold time
TWRHDH
WRXn
D31 to D16
tCLKT − 3
⎯
ns
SYSCLK
CSXn
⎯
11
ns
⎯
7
ns
SYSCLK ↓ to CSXn delay time
TCLCSL
TCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
136
DS07-16617-2E
MB91460S Series
7.8.5.
Asynchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
TWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT
⎯
ns
TDSWL
WEX
D31 to D16
1/2 × tCLKT − 7
⎯
ns
TWHDH
WEX
D31 to D16
1/2 × tCLKT − 3
⎯
ns
WEX
WRXn
⎯
1/2 × tCLKT + 1
ns
1/2 × tCLKT − 1
⎯
ns
⎯
1/2 × tCLKT − 1
ns
1/2 × tCLKT − 1
⎯
ns
TWRLWL
TWHWRH
TCLWL
TWHCH
WEX
CSXn
CSXn
TCLWL
TWHCH
WRXn
(as byte enable)
TWHWRH
TWRLWL
TWLWH
WEX
TDSWL
TWHDH
DATA OUT
DS07-16617-2E
137
MB91460S Series
7.8.6.
Asynchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
TWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT
⎯
ns
TDSWRL
WRXn
D31 to D16
1/2 × tCLKT − 7
⎯
ns
TWRHDH
WRXn
D31 to D16
1/2 × tCLKT − 3
⎯
ns
WRXn
CSXn
⎯
1/2 × tCLKT+1
ns
1/2 × tCLKT − 1
⎯
ns
TCLWRL
TWRHCH
CSXn
TWRHCH
TCLWRL
TWRLWRH
WRXn
TDSWRL
TWRHDH
DATA OUT
138
DS07-16617-2E
MB91460S Series
7.8.7.
RDY waitcycle insertion
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
RDY setup time
TRDYS
RDY hold time
TRDYH
Value
Unit
Min
Max
SYSCLK
RDY
12
⎯
ns
SYSCLK
RDY
0
⎯
ns
SYSCLK
tRDYS
tRDYH
RDY
DS07-16617-2E
139
MB91460S Series
■ ORDERING INFORMATION
Part number
MB91F467SAPMC-GSE2
140
Package
176-pin plastic LQFP
(FPT-176P-M07)
Remarks
Lead-free package
DS07-16617-2E
MB91460S Series
■ PACKAGE DIMENSION
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0˚~8˚
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
©2004-2008
FUJITSU MICROELECTRONICS LIMITED F176013S-c-1-2
C
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-16617-2E
141
MB91460S Series
142
Version
Date
Remark
0.10
2007-10-04
Initial draft
0.11
2007-10-10
corrected pindescription
0.12
2007-10-10
added scope
0.13
2007-11-07
updated pinning and featurelist
0.14
2007-11-19
updated the IO-map, Interrupt table and Flash access
0.15
2007-11-26
added APIX® register description, changed scope
0.16
2007-12-04
added trademark information, changed scope
0.17
2008-01-20
updated APIX® register description
0.18
2008-02-12
updated product lineup
0.19
2008-04-10
updated APIX® register description
0.20
2008-04-11
updated APIX® register description, Interruptvectortable
0.21
2008-07-31
added APIX® overview and DMA trigger settings
0.22
2008-08-01
updated APIX® PHY configuration
0.23
2008-08-27
updated APIX® controller description
0.24
2008-09-03
updated electrical characteristics and APIX® controller description
0.25
2009-02-02
updated APIX® RH description, operating conditions and AC characteristics,
added clockmodulator limitation
0.26
2009-02-04
updated APIX® RH description and operating conditions
0.27
2009-02-10
added trademark information
0.28
2009-03-03
updated product lineup and electrical characteristics
0.29
2009-03-10
updated ADC electrical characteristics
0.30
2009-05-08
corrected default values for PFR00 to PFR10 and level for AC specification
1.00
2009-06-02
corrected AC specification
1.01
2009-06-05
updated DC characteristics
1.02
2009-06-17
updated ordering information
DS07-16617-2E
MB91460S Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Preliminary Data Sheet → Data Sheet
The vertical lines marked in the left side of the page show the changes.
DS07-16617-2E
143
MB91460S Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
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Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
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10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
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Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
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system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
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Edited: Sales Promotion Department