74ACT11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993
•
•
•
•
•
•
•
D OR N PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Fully Buffered to Offer Maximum Isolation
From External Disturbance
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2J
t
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1J
1K
1CLK
1CLR
VCC
2CLR
2CLK
2K
description
This device contains two independent J-K negative-edge-triggered flip-flops. A low level at the PRE or CLR
input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the
negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to
the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed
without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying
J and K high.
The 74ACT11112 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
OUTPUTS
INPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
↓
L
L
Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
TOGGLE
H
H
H
X
X
Q0
{
{
Q0
Q0
† This configuration is nonstable; that is, it will not
persist when either PRE or CLR returns to the
inactive (high) level.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
2–1
74ACT11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993
logic symbol†
1 PRE
1
S
16
1J
1 CLK
1K
1 CLR
2 PRE
2J
2CLK
2 CLR
1Q
C1
15
13
7
3
1K
1Q
R
S
6
8
2J
2Q
10
C2
9
2K
2
1J
14
11
5
2K
2Q
R
† This symbol is in accordnace with ANSI/IEEE Std 91-1984 and IEC Publication 617-42.
logic diagram, each flip-flop (positive logic)
PRE
C
J
C
TG
Q
TG
C
K
CLK
C
C
C
C
C
TG
TG
C
C
Q
CLR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
74ACT11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993
recommended operating conditions
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
Dt /Dv
Low-level output current
TA
Operating free-air temperature
High-level input voltage
2
High-level output current
Input transition rise or fall rate
UNIT
V
V
0.8
V
VCC
VCC
V
– 24
mA
V
24
mA
0
10
ns/ V
– 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = – 50 mA
VOH
IOH = – 24 mA
VOL
MIN
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
5.5 V
4.94
4.8
MAX
IOL = 50 mA
4.5 V
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
VI = VCC or GND,
3.85
5.5 V
IO = 0
VI = VCC or GND
UNIT
V
5.5 V
IOL = 75 mA†
VI = VCC or GND
DICC‡
TA = 25°C
TYP
MAX
IOH = – 75 mA†
IOL = 24 mA
II
ICC
MIN
V
1.65
5.5 V
± 0.1
±1
5.5 V
4
40
mA
mA
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5V
3.5
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This parameter is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↓
th
Hold time after CLK↓
MIN
125
PRE or CLR low
4
4
CLK high or low
4
4
Data high or low
3.5
4.5
2
2
1.5
1.5
PRE or CLR inactive
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• DALLAS, TEXAS 75265
MAX
UNIT
125
MHz
ns
ns
ns
2–3
74ACT11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
fmax
tPLH
tPHL
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
MIN
125
PRE or CLR
Q or Q
CLK
Q or Q
tPLH
tPHL
MAX
125
UNIT
MHz
1.5
3.6
6.3
1.5
6.8
1.5
4.6
7.4
1.5
8
1.5
4.2
7
1.5
7.7
1.5
4.7
7.4
1.5
8.4
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per flip-flop
CL = 50 pF,
f = 1 MHz
TYP
UNIT
39
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
tw
CL = 50 pF
(see Note A)
3V
500 Ω
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
3V
Input
(see Note B)
3V
Timing Input
(see Note B)
0V
tsu
Data Input
1.5 V
0V
tPHL
tPLH
1.5 V
th
1.5 V
In-Phase
Output
50% VCC
3V
1.5 V
tPLH
tPHL
1.5 V
0V
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–4
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