HITTITE HMC983LP5E

v00.0911
HMC983LP5E
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Typical Applications
Features (Continued)
The HMC983LP5E is suitable for:
Integrated Frequency Sweeper
- Linear, Coherent Sweeps
- 2-Way, 1-Way, & User Defined Sweep Modes
- Automatic or Triggered
- Programmable Seed
-SPI & External Triggering
5-GPIO’s, can be used for External DSM
• Test Equipment
• Portable Instruments
• High Performance Fractional-N Frequency Synthesizers with Ultra Low Spurious
• Stand-Alone Divider and/or Delta-Sigma Modulator
Features
Wideband: DC - 7 GHz Input
-20-bit Frequency Divider
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6-1
Cycle Slip Prevention Support with PFD Chip
(HMC984LP4E)
Differential VCO Input & Divider Output
Low Noise: -160 dBc/Hz
Programmable Output Current Control:
-5 mA to 17.5 mA Open Collector Output Driver
Low Spurious: Largest Spurious - 95 dBc
32 pin, 5 x 5 mm, LP5 Package
48-bit 100 MHz Delta-Sigma Modulator (DSM)
- Configurable DSM Size
- Programmable Seed
Functional Diagram
General Description
HMC983LP5E is a fractional frequency divider
targeted for fractional-N frequency synthesis, and
stand-alone low noise frequency divider applications
that require exceptional spurious performance.
Although the HMC983LP5E can work with any VCO
and/or compatible Phase Detector, best performance
and features will be achieved when paired with the
companion part, the HMC984LP4E.
Fabricated in SiGe BiCMOS process, the
HMC983LP5E features a 48-bit Delta Sigma
Fractional Modulator (DSM) with programmable
phase accumulator size, enabling precise control of
frequency step size and resolution. Integrated DSM
can generate frequencies with nearly 0 Hz frequency
error. The DSM also includes a built-in programmable
frequency sweep capability, with various automatic
and user defined sweep modes and triggering options,
including hardware trigger pin, or SPI trigger with
optional delayed trigger.
HMC983LP5E is a versatile part capable of various
configurations. It has 5 general purpose I/Os (GPIOs).
DSM outputs are made available from the GPIO port,
enabling the HMC983LP5E to import and/or export
DSM sequences for various configuration options.
HMC983LP5E divider outputs are differential, open
collector with programmable current to accommodate
different off-chip loads.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 1. Electrical Specifications
TA = +25 °C, AVDD, VCCPS, VCCHF, VDDM, DVDD = 3 V ± 10%; VPPBUF = 5 V ± 10%; GND = 0 V
Parameter
Conditions
Min.
Typ.
Max.
Units
7
GHz
0
dBm
3
pF
RF Input Characteristics
RF Input Frequency range
DC
RF Input Sensitivity
RF Input Capacitance
-15
-10
External Match Recommended
Divider Range (20-bit)
32
1,048,575
Fractional Mode
36
1,048,571
Divider Output Characteristics
Output Buffer Current
Programmable in 2.5 mA Steps
5
12.5
17.5
mA
Output Voltage Swing
Single- Ended, Vpullup = 5 V
0.75
1
2
V
Mode A and Mode B
DC
DC
150
125
MHz
Output Frequency Range
Integer Mode
Fractional Mode
Phase Noise
Fractional Spurious
50 MHz PFD, 6 GHz Input, Integer Mode
-160
Largest observed at 10 kHz Fractional
Offset from Integer Boundary
-95
dBc/Hz
-85
dBc
DVDD-0.4
V
Logic Inputs
Input High Voltage (VIH)
Input Low Voltage (VIL)
0.4
V
Logic Outputs
Output High Voltage (VOH)
DVDD-0.4
Output Low Voltage (VOL)
0.4
V
DC Load
Serial Port Clock Frequency
V
Main SPI and AUXSPI
1.5
mA
30
MHz
Power Supplies
AVDD, VCCPS, VCCHF
VPPBUF
VDDM, DVDD
Analog Supplies. AVDD should be equal
to DVDD.
2.7
3
3.3
V
Output Buffer Supply.
4.5
5
5.5
V
Digital Supplies
2.7
3
3.3
V
Current Consumption
IDD - Total Current Consumption
Integer Mode / Fractional Mode
(50 MHz Divider Output)
104 / 122
mA
I - AVDD (AVDD Current, 3 V)
Integer Mode / Fractional Mode
5/5
mA
I - VCCPS (VCCPS Current, 3 V)
Integer Mode / Fractional Mode
79 / 79
mA
I - VCCHF (VCCHF Current, 3 V)
Integer Mode / Fractional Mode
8/8
mA
I - VDDM (VDDM Current, 3 V)
Integer Mode / Fractional Mode
11 / 11
mA
I - DVDD (Total DVDD Current, 3 V)
Integer Mode / Fractional Mode
1 / 19
mA
5
uA
I - VPPBUF (Total VPPBUF Current,
5 V)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6
FREQUENCY DIVIDERS & DETECTORS - SMT
Integer Mode
6-2
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Figure 2. Output Phase Noise, 6 GHz
Input Frequency [2]
Figure 1. RF Input Sensitivity [1]
40
-60
Maximum Input Power Limit
100 MHz Output Frequency Frac Mode A
-80
PHASE NOISE (dBc/Hz)
RF INPUT POWER (dBm)
20
0
Recommended Operating Range
-20
-40
-60
+27 C
+85 C
-40 C
Minimum Input Power Limit
RF Input Signal Phase Noise
-160
100 MHz Output Frequency Integer Mode
2000
4000
6000
8000
10000
10
2
10
3
RF INPUT FREQUENCY (MHz)
10
4
10
5
10
6
10
7
10
8
OFFSET FREQUENCY (Hz)
Figure 3. Output Phase Noise with 6 GHz
Input in Integer Mode [3]
Figure 4. Time Domain 10 MHz Output,
6.5 GHz Input [4]
-60
5.5
142 MHz Output Frequency
-80
OUTOUT VOLTAGE (V)
PHASE NOISE (dBc/Hz)
divCkPFDp Pin Output
-100
RF Input Signal Phase Noise
-120
100 MHz Output Frequency
-140
-160
5
4.5
50 MHz Output Frequency
-180
divCkPFDn Pin Output
Calculated Phase Noise
-200
10
4
2
10
3
10
4
10
5
10
6
10
7
10
8
0
50
100
150
OFFSET FREQUENCY (Hz)
200
250
300
350
TIME (ns)
Figure 5. Time Domain 18 MHz Output,
6.5 GHz Input [4]
Figure 6. Time Domain 35 MHz Output,
6.5 GHz Input [4]
5.5
5.5
divCkPFDp Pin Output
OUTPUT VOLTAGE (V)
divCkPFDp Pin Output
OUTPUT VOLTAGE (V)
FREQUENCY DIVIDERS & DETECTORS - SMT
-140
-200
0
6-3
-120
-180
-80
6
100 MHz Output Frequency Frac Mode B
-100
5
4.5
5
4.5
divCkPFDn Pin Output
divCkPFDn Pin Output
4
4
0
50
100
TIME (ns)
150
200
0
20
40
60
80
100
TIME (ns)
[1] The maximum and minimum levels indicate operational limits of the HMC983LP5E. Performance may degrade with input power greater than
0 dBm for frequencies higher than 6500 MHz.
[2] Due to Delta Sigma modulation in fractional mode, the output phase noise peaks at frequency offset of fout/2 from the output. Agilent MXG N5182A
used as a signal source.
[3] Rohde & Schwarz SMBV100A used as a signal source.
[4] Measured with 50 Ω impedance per line, integer Mode, 15 mA Output Buffer Current (Reg 0Fh[4:2]) selected
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Figure 7. Time Domain 124 MHz Output,
6.5 GHz Input [5]
Figure 8. Time Domain 66 MHz Output,
6.5 GHz Input [5]
5.5
5.5
divCkPFDp Pin Output
OUTPUT VOLTAGE (V)
5
4.5
5
4.5
divCkPFDn Pin Output
divCkPFDn Pin Output
4
4
0
5
10
15
20
25
0
30
10
20
Figure 9. Time Domain 61 MHz Output,
6.5 GHz Input [5]
50
6
5.5
divCkPFDp Pin Output
OUTPUT VOLTAGE (V)
divCkPFDp Pin Output
OUTPUT VOLTAGE (V)
40
Figure 10. Time Domain 66 MHz Output,
6.5 GHz Input [5]
5.5
5
4.5
5
4.5
divCkPFDn Pin Output
divCkPFDn Pin Output
4
4
0
10
20
30
40
50
0
10
20
TIME (ns)
40
50
Figure 12. 50 MHz Output Swing vs Buffer
Current [6]
0.9
SINGLE-ENDED OUTPUT SWING (Vpp)
0.9
0.85
0.8
0.75
0.7
0.65
-40 C
0.6
+27 C
0.55
+85 C
0.85
0.8
0.75
0.7
0.65
-40 C
0.6
+27 C
0.55
+85 C
0.5
0.5
12
30
TIME (ns)
Figure 11. 10 MHz Output Swing vs
Buffer Current [6]
SINGLE-ENDED OUTPUT SWING (Vpp)
30
TIME (ns)
TIME (ns)
13
14
15
16
OUTPUT BUFFER CURRENT (mA)
17
18
12
13
14
15
16
17
18
OUTPUT BUFFER CURRENT (mA)
[5] Measured with 50 Ω impedance per line, integer Mode, 15 mA Output Buffer Current (Reg 0Fh[4:2]) selected
[6] Measured with 50 Ω impedance per line. Buffer current is controled via Reg 0Fh[4:2].
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
OUTPUT VOLTAGE (V)
divCkPFDp Pin Output
6-4
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Figure 13. 100 MHz Output Swing vs
Buffer Current [7]
Figure 14. Input Return Loss
0
0.85
0.8
RETURN LOSS (dB)
SINGLE-ENDED OUTPUT SWING (Vpp)
0.9
0.75
0.7
0.65
-40 C
0.6
0.55
-15
+85 C
-20
12
13
14
15
16
17
0
18
2000
4000
Figure 15. Two Way Frequency Sweep,
50 MHz PFD [8]
8000
Figure 16. One Way Frequency Sweep,
10 MHz PFD and 10 Hz external trigger [8]
7000
7000
6900
6900
FREQUENCY (MHz)
FREQUENCY (MHz)
6000
FREQUENCY (MHz)
OUTPUT BUFFER CURRENT (mA)
6800
6700
6600
6800
6700
6600
6500
6500
6400
6400
0
5
10
TIME (ms)
15
0
20
Figure 17. PLL Cycle Slip Prevention,
100 MHz PFD [8]
200
400
600
TIME (ms)
800
1000
Figure 18. PLL Cycle Slip Prevention,
50 MHz PFD [8]
7050
7050
CSP Enabled
Reg0Eh[18:15] = 1h
7000
PLL OUTPUT FREQUENCY (GHz)
PLL OUTPUT FREQUENCY (MHz)
FREQUENCY DIVIDERS & DETECTORS - SMT
6-5
-10
+27 C
0.5
6
-5
CSP Enabled
Reg0Eh[18:15] = 8h
6950
6900
6850
Cycle Slip Disabled
6800
6750
6700
CSP Enabled
Reg0Eh[18:15] = Fh
7000
CSP Enabled
Reg0Eh[18:15] = 5h
6950
6900
6850
Cycle Slip Disabled
6800
6750
6700
0
50
100
150
TIME (us)
200
250
300
0
50
100
150
200
250
300
TIME (us)
[7] Measured with 50 Ω impedance per line. Buffer current is controled via Reg 0Fh[4:2].
[8] Measured with HMC983LP5E/HMC984LP4E chip set as fractional-N synthesizer. Crystal input frequency = 100 MHz, CP current = 2.5 mA, CP
offset current = 245 uA, Loop filter bandwidth = 87 KHz, DSM Mode B selected. Cycle Slip Prevention (CSP) is disabled in HMC984LP4E by setting
Reg 01h [4] = 0. Setting Reg 01h [4] = 1 enables CSP in the two chip PLL.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 2. Pin Descriptions
Function
Description
1,
2,
3
SENb
SDI
SCK
Main SPI Data Input
4,
5
D1
D0
GPIO bit 1
GPIO bit 0
6,
7,
8
AUX_SCLK
AUX_SENb
AUX_SDO
9
BIAS
External Decoupling for Analog Bias Circuits
10
AVDD
3 Volt Power Supply Pin for Internal Reference Current Sources
11
VCCPS
3 Volt Power Supply Pin for Prescaler
12,
13
VCOIN,
VCIOP
Negative Pin for Prescaler Differential Input, AC-Coupled
Positive Pin for Prescaler Differential Input, AC-Coupled
Interface Schematic
Auxiliary SPI Clock Output
Auxiliary SPI Enable
Auxiliary SPI Data Output
14
VCCHF
3 Volt Power Supply Pin for Prescaler Input Buffer
15
VPPBUF
5 Volt Power Supply Pin for Divider Output Buffer
16
N/C
No Connect Pin
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6
FREQUENCY DIVIDERS & DETECTORS - SMT
Pin Number
6-6
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 2. Pin Descriptions (Continued)
Pin Number
Function
Description
17,
18
divCkPFDn,
divCkPFDp
Negative Pin for Open Collector Divider Output Driver
Positive Pin for Open Collector Divider Output Driver
19
VDDM
3V Supply Pin for Digital Section of the Frequency Divider
20,
21,
22
D2,
D3,
D4
GPIO bit 2,
GPIO bit 3,
GPIO bit 4
23
REF_Eno
Gate Control (Output) to request TCXO Clock Export from
HMC984LP4E
24,
25,
26
CHIP1,
CHIP2,
CHIP3
Chip Address Pin 1,
Chip Address Pin 2,
Chip Address Pin 3
27, 30
DVDD
3V Power Supply for Digital
28,
DNSAT,
VCO Saturation Input flag from HMC984LP4E Chip
Interface Schematic
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6-7
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 2. Pin Descriptions (Continued)
Pin Number
Function
Description
29
UPSAT
Reference Saturation Input flag from HMC984LP4E Chip
Interface Schematic
31
CEN
Chip Enable
32
SDO
Main SPI Data Output
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6-8
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 3. Absolute Maximum Ratings
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6-9
Nominal 3V Supplies to GND
-0.3 to 3.6 V
Nominal 3V Digital Supply to 3V
Analog Supply
-0.3 to +0.3 V
Nominal 5V Supply to GND (VPPBUF)
-0.3 to 5.5 V
divCkp, divCkn common mode DC
VCCPS + 0.5 V min
VCOIP, VCOIN Single Ended AC 50 Ω
Source
+ 7 dBm
VCOIP, VCOIN Differential AC 50 Ω
Source
+ 13 dBm
Digital Input Voltage Range
-0.25 to DVDD + 0.5 V
Minimum Digital Load
1 kΩ
Operating Temperature Range
-40 °C to +85 °C
Maximum Junction Temperature
125 °C
Storage Temperature
-65 to +125 °C
Thermal Resistance (Rth)
(junction to ground paddle)
40 °C/W
Reflow Soldering
Peak Temperature
Time at Peak Temperature
260 °C
40 s
ESD Sensitivity (HBM)
Class 1B
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational section of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
Outline Drawing
NOTES:
[1] PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC
SILICA AND SILICON IMPREGNATED.
[2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY.
[3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN.
[4] DIMENSIONS ARE IN INCHES [MILLIMETERS].
[5] LEAD SPACING TOLERANCE IS NON-CUMULATIVE.
[6] PAD BURR LENGTH SHALL BE 0.15 mm MAX. PAD BURR HEIGHT SHALL BE
0.25 m MAX.
[7] PACKAGE WARP SHALL NOT EXCEED 0.05 mm
[8] ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB
RF GROUND.
[9] REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND
PATTERN.
Package Information
Part Number
Package Body Material
Lead Finish
MSL Rating [2]
Package Marking [1]
HMC983LP5E
RoHS-compliant Low Stress Injection Molded Plastic
100% matte Sn
MSL1
H983
XXXX
[1] 4-Digit lot number XXXX
[2] Max peak reflow temperature of 260 °C
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Evaluation PCB
The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohms
impedance while the package ground leads and exposed paddle should be connected directly to the ground plane
similar to that shown unless mentioned otherwise. A sufficient number of via holes should be used to connect the top
and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request.
Table 4. Evaluation Order Information
Item
Evaluation Kit
Contents
HMC983LP5E and HMC984LP4E PLL Chipset Evaluation PCB
USB Interface Board
6’ USB A Male to USB B Female Cable
CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software)
Part Number
EKIT01-HMC983LP5E
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 10
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Evaluation PCB Block Diagram
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 11
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Theory of Operation
The HMC983LP5E can be used in following configurations:
1. Fractional-N or Integer Mode RF Frequency Divider or Prescaler
2. Fractional-N Frequency Synthesizer with an appropriate Phase Detector and VCO
Primary target application of the HMC983LP5E is to be used in conjunction with the HMC984LP4E as shown in Figure
19. Together these two components form a high performance, low noise, ultra low spurious emissions fractional-N
frequency synthesizer.
Figure 19. Typical Application of HMC984LP4E with HMC983LP5E to Form a Frequency Synthesizer
The HMC983LP5E consists of the following functional blocks
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
RF Input Buffer
7 GHz Frequency Prescaler and Multi Modulus Divider
48-bit Configurable Fractional Delta Sigma Modulator
Bias Circuit
Differential Output Driver
Frequency Sweeper
Main Serial Port Interface
Auxiliary Serial Port Interface (Output Only)
General Purpose Digital IO
Power On Reset Circuit
RF Input Buffer
The RF input stage provides the path from the external VCO to the fractional RF Divider. The RF input path is rated
to operate nominally from DC to 7 GHz. The HMC983LP5E RF input stage is a differential common emitter stage with
DC coupling, and is protected by ESD diodes as shown in Figure 20. RF input is not matched to 50 Ω due to wide input
frequency range. At low frequencies, a simple shunt 50 Ω resistor can be used external to the package to provide a
50 Ω match. For better performance it is recommended to match the RF inputs externally and provide differential drive
from the VCO. In most applications the input is used single-ended into either the VCOIP or VCOIN pin with the other
input connected to ground through a DC blocking capacitor. The preferred input level for best spectral performance
is -10 dBm.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 12
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
6
FREQUENCY DIVIDERS & DETECTORS - SMT
Figure 20. RF Input Stage
6 - 13
RF Path Fractional-N Divider
The RF input buffer is followed by a high frequency prescaler and a multi modulus divider. The divider has been
designed for the best output phase noise and spurious performance in both fractional and integer mode. The
fractional-N divider can divide input frequencies from 32 to 220 -1 (1048575) in integer mode and from 36 to 220 -5
(1048571) in fractional-N mode. The divider output pulse width depends on the RF input period and is adjustable via
SPI setting (refer to Duty Cycle Setting in register Reg 0Fh[14:12]). The output pulse width recommended setting is
40% to 60% where possible. At low output frequencies it may not be possible to set 50% duty cycle. In such cases the
maximum pulse width setting is recommended.
Figure 21. Divider Path
Divider Output Buffer
The divider output is differential and the output buffer stage is an open collector amplifier with off-chip pull-up resistors.
Due to sharp rise and fall times at the divider output, the external path should be designed differentially using RF
techniques.
When HMC983LP5E and HMC984LP4E are operating together as a frequency synthesizer, 50 Ω pull-up resistors are
provided in HMC984LP4E.
VPPBUF pin should be connected to 5 V power supply. This pin does not sink DC current and is only used to bias the
internal ESD diodes and to provide an appropriate voltage level for the phase detector chip (HMC984LP4E). The two
possible interface configurations are shown in Figure 22 and Figure 23 below.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Figure 22. Generic Divider Output Interface
Figure 23. Divider Interface with HMC984LP4E
Chip Address Pins
The HMC983LP5E has three SPI chip address pins (SPI address [2:0] = ‘CHIP3, CHIP2, CHIP1’), which enable
multiple HMC983LP5E devices to use the same SPI bus. SPI chip address bits are read at power up, or every time
HMC983LP5E is reset. By default, all three pins are internally pulled to DVDD, thus there is no need to connect
the pins to DVDD to set them to logic high. To assign a ‘0’ to any chip address bit, the corresponding pin should be
connected to ground.
When used on the same SPI bus together with the companion part (the HMC984LP4E), to form a frequency synthesizer,
some SPI commands, such as changing the reference division ratio to the HMC984LP4E may also require an action
by the HMC983LP5E. In order to avoid the necessity to write two separate SPI transfers to implement one command
(one to configure HMC984LP4E, and the other one to configure the HMC983LP5E), it is possible to write the SPI
address of the companion part (HMC984LP4E) into Reg 09h of the HMC983LP5E. In such cases, the HMC983LP5E
is able to recognize an SPI command to the companion part (the HMC984LP4E) that requires its own action, and act
accordingly to update its own corresponding registers. Writing HMC983LP5E’s own chip address to the companion
chip address register Reg 09h will disable this feature.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 14
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Saturation Detection Input Pins DNSAT, UPSAT
When the HMC983LP5E is operating with its companion chip the HMC984LP4E as a frequency synthesizer, it
automatically detects large phase errors and tries to tune the VCO faster by using its algorithm for cycle-slip prevention
(CSP). The UPSAT and DNSAT provide indication which frequency is higher (VCO or Reference) from the counterpart
Phase Detector/Charge Pump (the HMC984LP4E). The CSP algorithm manipulates the RF Divider and the Phase
Detector at appropriate intervals to lock faster. See HMC984LP4E data sheet for more details. These pins should be
connected to ground if not used.
REF_Eno Pin
REF_Eno pin is a digital output pin that is used by the HMC983LP5E to request crystal oscillator clock from the Phase
Detector / Charge Pump chip (the HMC984LP4E).
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 15
The crystal oscillator clock is multiplexed on the HMC983LP5E’s DNSAT pin. The internal frequency divider,
programmed in Reg 02h, is used to generate the actual reference frequency present at the phase detector. The
imported clock is only used to communicate through the AUXSPI. At all other times, the clock and the local reference
dividers are turned off.
In stand-alone applications, if the HMC983LP5E is required to communicate through the auxiliary SPI, the
HMC983LP5E will expect to receive the auxiliary SPI clock on DNSAT pin. Setting Reg 04h[15] = 1 keeps the auxiliary
SPI clock enabled on the DNSAT pin.
Multi Purpose Digital IO Pins D0, D1, D2, D3, D4 (GPIO Pins)
The five general purpose digital input/outputs can be used for various modes of operation as well as test/debugging
purposes. GPIO pins are enabled by writing Reg 01h[4] = 1 (GPIO master enable). Setting Reg 01h[4] = 0 places the
GPIO pins in tri-state high impedance mode.
GPIO pins are configured in Reg 08h[13:0]. All of the pins can configured to be either inputs or outputs by writing to
Reg 08h[13:9]. In frequency sweep mode, pin D4 can be used as an external trigger pin, by writing Reg 08h[13] = 0.
Writing to Reg 08h[3:0] selects HMC983LP5E’s internal signals to be multiplexed out on the GPIO pins, as shown in
Table 5. Signals include:
1. The output of the Delta-Sigma Modulator Reg 08h[3:0] = ‘0010’b.
2. GPIO test signals Reg 08h[3:0] = ‘0000’b, which outputs data written to Reg 08h[8:4] to test the GPIO pins.
3. Sweep status flags, when the HMC983LP5E is configured to be in sweep mode Reg 08h[3:0] = ‘1000’b.
Table 5. GPIO Pin Assignment and Output Signals
Reg 08h[3:0]
HMC983LP5E GPIO Pins
D4
D3
D2
D1
D0
0000
gpo_test_out[4]
gpo_test_out[3]
gpo_test_out[2]
gpo_test_out[1]
gpo_test_out[0]
0001
reserved
reserved
reserved
reserved
reserved
0010
DSM_OUT[4]
DSM_OUT[3]
DSM_OUT[2]
DSM_OUT[1]
DSM_OUT[0]
0011
reserved
reserved
reserved
reserved
reserved
0100
reserved
reserved
reserved
reserved
reserved
0101
reserved
reserved
reserved
reserved
reserved
0110
reserved
reserved
reserved
0
0
0111
reserved
reserved
reserved
reserved
reserved
1000
ramp_ready_flag
ramp_start_flag
ramp_stop_flag
ramp_busy_falg
reserved
1001-1111
0
0
0
0
0
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Fractional Mode of Operation
In addition to providing simple integer division ratios, the HMC983LP5E has a sophisticated, configurable 48-bit Delta
Sigma Modulator (DSM), that allows fractional division of the input frequency in ultra fine steps. The DSM’s size can
be configured to 16/24/32/48 bits (Reg 16h[5:0]). HMC983LP5E’s auto-seed mode allows coherent frequency sweeps.
The HMC983LP5E with its counterpart (the HMC984LP4E), together with an external VCO comprise a fully functional
fractional-N synthesizer. In that case, the output frequency of the external VCO is given by:
fvco =
fxtal
f
⋅ Nint + xtal L ⋅ Nfrac = fint + ffrac
R
R⋅2
(Eq 1)
When the HMC983LP5E is being used as frequency divider, the output frequency is given by;
Nint
fvco
N
+ frac
2L
(Eq 2)
Where
f vco is the VCO frequency in Hz;
fxtal
is the crystal oscillator frequency in Hz;
Nint
is the integer part of frequency division ratio (set in Reg 05h[19:0]);
Nfrac
is the fractional part of frequency division ratio (Nfrac[47:18] = Reg 06h[29:0], Nfrac[17:0] = Reg 07h[17:0])
R
is the reference frequency division ratio;
L
is the size of the DSM accumulators (set in Reg 16h[5:0])
Example 1: Calculate the VCO frequency with the following parameters;
fxtal = 50 MHz;
fpfd = 25 MHz
Nint = 25;
Nfrac = 1;
L = 24
Where fPFD is the frequency at the phase detector, thus R = 2. According to (Eq 1), the VCO frequency with the above
parameters will be;
50MHz
50MHz
⋅ 25 +
⋅ 1 = 2500MHz + 1.49Hz
2
2 ⋅ 224
If accumulator width (L) is changed to 48-bit, then the frequency resolution will improve and the fractional resolution
of the VCO frequency will be 88.8178 nano-Hz.
fvco =
Example 2: Set the VCO frequency to 4600.025 MHz using 100 MHz Crystal, R = 2 and L = 16. Compare if L = 32.
For this example the fPFD = 100 MHz/2 = 50 MHz,
The overall division ratio is 4600.025 MHz/50 MHz = 92.0005
The nearest integer would be 92, thus Nint = Reg 05h[19:0] = 92d = 5Ch.
For L = 16, Nfrac = 32.768 or 33d rounded up. Thus Nfrac = 33d or 21h (Reg 06h[29:0] = 0, Reg 07h[17:0] = 21h).
For L = 32, Nfrac = 2147483.648 or 2147484d rounded up. Thus Nfrac = 20C49Ch (Reg 06h[29:0] = 8h, Reg 07h[17:0]
= ‘001100010010011100‘d).
Since Nfrac must be an integer, the actual frequencies in the two cases will have an error of + 177.02 Hz for L = 16 and
only +0.004098 Hz for L = 32.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6
FREQUENCY DIVIDERS & DETECTORS - SMT
fout =
6 - 16
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Phase Noise in Integer and Fractional Modes
In a normal integer frequency divider the in-band phase noise is scaled from the input phase noise by 20Log10(N),
where N is the divider value. In HMC983LP5E fractional mode, the frequency divider is modulated by the Delta Sigma
Modulator to generate output frequencies that are fractional multiple of the input frequency. Delta Sigma Modulator
shapes the quantization noise such that quantization noise density has a high pass shape which peaks at Fs/2,
where Fs is the sampling frequency (the divider output frequency in case of HMC983LP5E). In fractional mode this
quantization noise peak appears at an offset frequency of Fout/2. In the PLL, this peak is attenuated by the loop filter.
However, when the HMC983LP5E is used stand-alone in fractional mode its output will exhibit the quantization noise
as shown in Figure 2 and Figure 3. As a result, it is not possible to achieve the same noise floor in fractional mode as
in integer mode without further filtering.
CW Frequency Sweeper
6
The HMC983LP5E features a built-in frequency sweeper function that supports automatic or externally triggered
sweeps. External triggering can be executed via an external trigger pin D4 or the SPI interface.
HMC983LP5E sweep function can be configured to operate in the following modes:
FREQUENCY DIVIDERS & DETECTORS - SMT
•
6 - 17
•
2-Way sweep mode
•
Repeating alternating positive and negative frequency sweep ramps
•
Frequency increments swept with automatic sequencer
•
Automatic or triggered
•
Symmetric or asymmetric (the positive ramp can have a different slope from that of the negative ramp)
1-Way Sweep Mode
•
Repeating one directional frequency sweeps followed by a reset to the starting frequency
•
Frequency increments swept with automatic sequencer
•
Triggered
User defined sweep mode
•
Manually programmed user defined sweep patterns
•
Triggered
•
Symmetric or asymmetric (the positive ramp can have a different slope from that of the negative ramp)
In all sweep modes, the starting sweep direction can be set to positive (increasing) or negative (decreasing). The
trigger can be applied instantaneously or delayed by a programmable time delay.
HMC983LP5E’s sweep function is illustrated in Figure 24. The HMC983LP5E generates a frequency sweep by
implementing automatic, or triggered in User Defined Mode, discrete miniature frequency increments in time. A
smooth and continuous sweep is then generated, at the output of the VCO, after the stepped signal is filtered by the
loop filter, as shown in Figure 24. The stepped sweep approach enables the frequency synthesizer (comprising of
HMC983LP5E together with its counterpart, the HMC984LP4E) to be in lock for the entire duration of the sweep. This
approach results in a number of advantages over conventional methods including:
•
The ability to generate a linear sweep.
•
The ability to have phase coherence between different sweep ramps, so that the phase profile of each sweep is
identical.
•
The ability to generate user defined sweeps in User Defined Sweep Mode.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Figure 24. HMC983LP5E Sweep Function
It is important to note that the synthesized ramp is subject to normal phase locked loop dynamics. If the loop bandwidth
in use is much wider than the rate of frequency increments then the locking will be fast and the ramp will have a
staircase shape. If the update rate is higher than the loop bandwidth, as is normally the case, the loop will not fully
settle before a new frequency step is received. Hence the swept output will have a lag and will sweep in a near
continuous fashion.
In all sweep modes, ramp_busy flag indicates an active sweep and will stay high between the 1st and nth ramp
increment. ramp_busy may be monitored on pin D1 by setting Reg 08h[3:0] = 8h.
Triggering
In sweep mode, the HMC983LP5E can be triggered via one of two methods
•
SPI trigger by setting Reg 0Eh[12]=1. This triggering method is asynchronous to the reference clock. To enable
SPI trigger write Reg 0Eh[13] = 0.
•
or applying an external trigger on pin D4. Setting Reg 0Eh[13] = 1 and Reg 08h[13] = 0h configures HMC983LP5E’s
pin D4 as external trigger input. External trigger on pin D4 is triggered on the rising edge of the trigger. GPIO
master enable (Reg 01h[4] = 1) is also required.
•
External triggering method can be synchronized with the reference clock, by enabling trigger delay (Reg
0Eh [7] = 1), and programming a trigger delay in Reg 05h[20:0] = number of delayed reference periods.
Writing Reg 05h[20:0] = 1 for example ensures that the trigger is applied at the instant of the rising edge of
the next reference rising edge. To disable trigger delay write Reg 0Eh [7] = 0.
2-Way Sweep Mode
HMC983LP5E’s 2-Way sweep mode is shown in Figure 25. The 2-Way sweep mode can be automatic or triggered. In
automatic 2-way sweep, the trigger is generated internally based on user defined 2-way sweep mode configuration. In
a triggered 2-way sweep, frequency ramps are triggered either by external pin D4, or SPI trigger.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 18
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 19
Figure 25. HMC983LP5E 2-Way Triggered Sweep
Triggered 1-Way Sweeps
HMC983LP5E’s 1-Way sweeps is shown in Figure 26. Unlike 2-Way sweeps, 1-Way sweeps require that the VCO hop
back to the start frequency after the dwell period. Triggered 1-Way sweeps also require a 3rd trigger to start the new
sweep. The 3rd trigger must be timed appropriately to allow the VCO to settle after the large frequency hop back to
the start frequency. Subsequent odd numbered triggers will start each sweep and repeat the process.
Figure 26. HMC983LP5E 1-Way Triggered Sweep
1-Way sweeps are not recommended in auto-sweep mode since in auto-sweep the new sweep will start immediately
after the 2nd trigger, as it does in 2-Way mode.
User Defined Sweep Mode
In User Defined Sweep mode, the HMC983LP5E is able to generate various user-defined sweep patterns by adjusting
the time interval between adjacent frequency increments, which are executed by trigger events. HMC983LP5E’s User
Defined Sweep Mode is shown in Figure 27. In this mode, an external trigger is required for each frequency increment
of the sweep.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Figure 27. HMC983LP5E User Defined Sweep
User defined sweep can function in both 1-Way or 2-Way sweep mode. In 1-Way sweep mode, the n+1 trigger will
cause the ramp to jump to the start frequency, and the n+2 trigger will restart the 1-way sweep.
Detailed Sweeper Configuration
Recommended procedure for configuring HMC983LP5E sweeper in all three modes is shown in Table 6.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 20
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 6. HMC983LP5E Sweeper Configuration Sequence
Steps
1
2
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 21
3
Description
Lock to start
frequency (fo)
Place the DSM
in sweep mode
Configure
sweep mode
Sweeper Modes
2-Way Sweep Mode
User Defined Sweep Mode
1-Way Sweep Mode
•set the integer (Reg 05h) and fractional (Reg 06h and Reg 07h) divider values.
•Optionally, if required the seed (Reg 0Ah and Reg 0Bh) can also be programmed
•Write Reg 0Eh[11] = 1
•Disable single step ramp mode (Reg
0Eh[24] = 0), so that each frequency
increment will be incremented
automatically
•Enable 2-way sweep mode (Disable
1-way sweep mode (Reg 0Eh[25]
= 0))
•To place the HMC983LP5E in
automatic sweep mode write
Reg 0Eh[2:3] = ‘11’. To place the
HMC983LP5E in triggered mode
write Reg 0Eh[2:3] = ‘00’.
•Enable the single step ramp mode
(Reg 0Eh[24] = 1), so that each
frequency increment will require a
trigger
•Enable 1-way sweep mode (Reg
0Eh[25] = 1), or enable 2-Way
sweep mode (Reg 0Eh[25] = 1)
•To place the HMC983LP5E in
triggered mode write Reg 0Eh[2:3] =
‘00’. Automatic User Defined Sweep
mode is not supported.
•Disable single step ramp mode (Reg
0Eh[24] = 0), so that each frequency
increment will be incremented
automatically
•Enable 1-way sweep
0Eh[25] = 1)
mode (Reg
•To place the HMC983LP5E in
triggered mode write Reg 0Eh[2:3] =
‘00’. Automatic 1-Way Sweep mode
is not supported.
4
Program
Sweep
Direction
5
Configure
symmetrical/
asymmetrical
sweep
6
Program
Up Sweep
Parameters
7
Program
Down Sweep
Parameters
(Only if using
asymmetrical
sweep (if Reg
0Eh[22] = 0) in
Step 5)
•Set dwell time (dwell time[47:0] = Reg 06h[47:18], dwell time[17:0] = Reg
07h[17:0])
•Set step size (step size[47:18] = Reg 19h[29:0], step size[17:0] = Reg
1Ah[17:0])
•Set the number of steps in a sweep (number of steps[47:18] = Reg 0Ch[29:0],
number of steps[17:0] = Reg 0Dh[17:0])
Configure and
apply trigger
•To use SPI trigger write Reg 0Eh[13] = 0 to select SPI trigger. SPI trigger is executed by writing to Reg 0Eh[12] = 1.
•To use external trigger on pin D4 write Reg 0Eh[13] = 1 to configure pin D4 as an external trigger. Write Reg 08h[13]
= 0h to configure pin D4 to be an input. Applying master enable to GPIO pins (Reg 01h[4] = 1 ) is required.
•Enable trigger delay (Reg 0Eh[7] = 1), or disable trigger delay (Reg 0Eh[7] = 0).
•If using trigger delay, write delay value to Reg 05h[20:0], where Reg 05h[20:0] = number of delayed reference
periods. Writing Reg 05h[20:0] = 1 for example ensures that the trigger is applied at the instant of the rising edge
of the next reference rising edge.
8
•Reg 0Eh[26] = 1 begin sweep in positive direction, Reg 0Eh[26] = 0 begin sweep in negative direction
•Program ramp mode (symmetrical - Reg 0Eh[22] = 1, asymmetrical - Reg
0Eh[22] = 0). If symmetrical ramp mode is selected (Reg 0Eh[22] = 1), only
Up sweep parameters will be used for both positive and negative sweeps,
and hence down sweep parameters don’t need to be programmed. In
symmetrical ramp mode the positive and negative ramps are identical and
opposite in direction.
•Program Reg 0Eh[22] = 1.
Asymmetrical sweep is not defined
in 1-Way Sweep mode
•Set dwell time(dwell time[47:0] = Reg 10h[29:0], dwell time[17:0] = Reg 11h[17:0])
•Set step size (step size[47:18] = Reg 12h[29:0], step size[17:0] = Reg 13h[17:0])
•Set the number of steps in a sweep (number of steps[47:18] = Reg 14h[29:0], number of steps[17:0] = Reg 15h[17:0])
•Asymmetrical sweep is not defined
in 1-Way Sweep mode
HMC983LP5E sweep parameters are defined in the following way:
fo Initial frequency of the synthesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
ff
Frequency of the synthesizer at the end of the sweep
R
Reference divider value(Reg 02h[13:0])
stepsize
frequency increment step size. In case of symmetric and UP sweeps, stepsize[47:18] = Reg 12h[29:0], stepsize[17:0] = Reg 13h[17:0]). In case of asymmetric sweeps, (downsweep stepsize[47:18] = Reg 12h[29:0], down sweep stepsize[17:0] = Reg 13h[17:0])
∆fstep
Frequency step size =
L
Size of the DSM (set in Reg 16h[5:0])
Tref
Period of the divided reference (fPFD) at the phase detector. Tref =
stepsize ⋅
2L ⋅ R
,
R
fxtal
N
Total number of frequency step increments in a single sweep. N [47:18] = Reg 14h[29:0],
N[17:0] = Reg 15h[17:0]
Total time of one frequency sweep from fo to ff. Tramp = Tref x N
Tramp
Then final frequency ff is given by: ff = fo + (∆fstep x N)
Setting autoseed (Reg 0Eh[8] = 1) ensures that different sweeps have identical phase profile. This is achieved
by loading the seed (seed[47:18] = Reg 0Ah[29:0], seed[17:0] = Reg 0Bh[17:0]) into the phase accumulator at the
beginning of each ramp.
Example: Calculate sweep parameters for an asymmetric 2-Way sweep from f0 = 3000 MHz to ff = 3105 MHz with
positive Tramp ≈ 2 ms, and negative Tramp ≈ 4 ms, and positive dwell time = negative dwell time = 2 µs, with fPD = 50
MHz, and a 48-bit delta-sigma modulator size. Assuming R = 1.
1. Calculate the integer and fractional divider values for initial start frequency f0
•
Start Nint = Reg 05h = 60d
•
Start Nfrac = Reg 06h = Reg 07h = 0d
2. Calculate the number of divided (R = 1) reference periods in the sweep = number of frequency increments N
•
Nup = 2 ms/(1/50 MHz) = 100000
•
Ndown = 4 ms/(1/50 MHz) = 200000
3. Calculate stepsize (size of frequency increments)
•
stepssize up = abs(ff - f0)/Nup = abs(3000 MHz - 3105 MHz)/100000 = 1050 Hz. Then as per Table 6, Reg
12h[29:0] = 0h, Reg 13h[17:0] = 1050d = 41Ah
•
stepsize down = abs(ff - f0)/Ndown = abs(3000 MHz - 3105 MHz)/200000 = 525 Hz Then as per Table 6,
Reg 19h[29:0] = 0h, Reg 1Ah[17:0] = 1050d = 41Ah
Note that it is possible to have a case where the frequency ff cannot be generated exactly. In that case it is
required to approximate the final frequency to ff = fo + (∆fstep x N) ≈ desired final frequency.
4. Calculate number of divided (R = 1) reference periods in required dwell time
•
Up dwell time (Reg 10h[29:0], Reg 11h[17:0]) = down dwell time (Reg 06h[29:0], Reg 07h[17:0]) = dwell
time/ (1/ 50 MHz) = 2 µs/(1/50 MHz) = 100. Then as per Table 6, Reg 10h[29:0] = Reg 06h[29:0] = 0h, and
Reg 11h[17:0] = Reg 07h[17:0] = 100d = 64h.
Then proceed to configure the sweep according to the steps outlined in Table 6.
Serial Port Interface
The HMC983LP5E features a four wire serial port for simple communication with the host controller. Typical serial port
operation can be run with SCK at speeds up to 30 MHz.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6
FREQUENCY DIVIDERS & DETECTORS - SMT
fxtal
6 - 22
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
The details of SPI access for the HMC983LP5E is provided in the following sections. Note that the READ operation
below is always preceded by a WRITE operation to Register 0 to define the register to be queried. Also note that
every READ cycle is also a WRITE cycle in that data sent to the SPI while reading the data will also be stored by the
HMC983LP5E when SENb goes high. If this is not desired then it is suggested to write to Register 0 during the READ
operation so that the status of the device will be unaffected.
Power on Reset and Soft Reset
The HMC983LP5E has a built in Power On Reset (POR) and a serial port accessible Soft Reset (SR). POR is
accomplished when power is cycled for the HMC983LP5E while SR is accomplished via the SPI by writing Reg 00h
= 80h, followed by writing Reg 00h =00h. All chip registers will be reset to default states approximately 250 us after
power up.
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 23
Serial Port WRITE Operation
The host changes the data on the falling edge of SCK and the HMC983LP5E reads the data on the rising edge.
A typical WRITE cycle is shown in Figure 28. It is 32 clock cycles long.
1. The host both asserts SENb (active low Serial Port Enable) and places the MSB of the data on SDI followed
by a rising edge on SCK.
2. HMC983LP5E reads SDI (the MSB) on the 1st rising edge of SCK after SENb.
3. HMC983LP5E registers the data bits, D23:D0, in the next 23 rising edges of SCK (total of 24 data bits).
4. Host places the 5 register address bits, A4:A0, on the next 5 falling edges of SCK (MSB to LSB) while the
HMC983LP5E reads the address bits on the corresponding rising edge of SCK.
5. Host places the 3 chip address bits, CA2:CA0=[110], on the next 3 falling edges of SCK (MSB to LSB). Note
the HMC983LP5E chip address is fixed as “6d” or “110b”.
6. SENb goes from low to high after the 32nd rising edge of SCK. This completes the WRITE cycle.
7. HMC983LP5E also exports data back on the SDO line. For details see the section on READ operation.
Serial Port READ Operation
The SPI can read from the internal registers in the chip. The data is available on SDO pin. This pin itself is tri-stated
when the device is not being addressed. However when the device is active and has been addressed by the SPI
master, the HMC983LP5E controls the SDO pin and exports data on this pin during the next SPI cycle.
HMC983LP5E changes the data to the host on the rising edge of SCK and the host reads the data from HMC983LP5E
on the falling edge.
A typical READ cycle is shown in Figure 28. Read cycle is 32 clock cycles long. To specifically read a register, the
address of that register must be written to dedicated Reg 0h. This requires two full cycles, one to write the
required address, and a 2nd to retrieve the data. A read cycle can then be initiated as follows;
1. The host asserts SENb (active low Serial Port Enable) followed by a rising edge SCK.
2. HMC983LP5E reads SDI (the MSB) on the 1st rising edge of SCK after SENb.
3. HMC983LP5E registers the data bits in the next 23 rising edges of SCK (total of 24 data bits). The LSBs of
the data bits represent the address of the register that is intended to be read.
4. Host places the 5 register address bits on the next 5 falling edges of SCK (MSB to LSB) while the HMC983LP5E
reads the address bits on the corresponding rising edge of SCK. For a read operation this is “00000”.
5. Host places the 3 chip address bits [110] on the next 3 falling edges of SCK (MSB to LSB).
6. SENb goes from low to high after the 32nd rising edge of SCK. This completes the first portion of the READ
cycle.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
7. The host asserts SENb (active low Serial Port Enable) followed by a rising edge SCK.
8. HMC983LP5E places the 24 data bits, 5 address bits, and 3 chip id bits, on the SDO, on each rising edge of
the SCK, commencing with the first rising edge beginning with MSB.
9. The host de-asserts SENb (i.e. sets SENb high) after reading the 32 bits from the SDO output. The 32 bits
consists of 24 data bits, 5 address bits, and the 3 chip id bits. This completes the read cycle.
Note that the data sent to the HMC983LP5E SPI during this portion of the READ operation is stored in the
SPI when SENb is de-asserted. It is recommended that during the second phase of the READ operation that
Reg 00h is addressed with either the same address or the address of another register to be read during the
next cycle.
Figure 28. SPI Timing Diagram
DVDD = 5 V ±10%, GND = 0 V
Table 7. Main SPI Timing Characteristics
Parameter
Conditions
t1
SDI to SCK Setup Time
t2
t3
Min
Typ
Max
Units
8
nsec
SDI to SCK Hold Time
8
nsec
SCK High Duration [1]
10
nsec
t4
SCK Low Duration
10
nsec
t5
SENb Low Duration
20
nsec
t6
SENb High Duration
20
nsec
t7
SCK to SENb [2]
8
nsec
t8
SCK to SDO out
[3]
8
nsec
[1] The SPI is relatively insensitive to the duty cycle of SCK.
[2] SENb must rise after the 32nd falling edge of SCK but before the next rising SCK edge. If SCK is shared amongst several devices this timing
must be respected.
[3] Typical load to SDO is 10 pF, maximum 20 pF
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 24
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Register Map
Table 8. Reg 00h Chip ID, Soft Reset, Read Register
BIT
TYPE
[6:0]
R/W
[7]
[31:8]
NAME
W
DEFLT
DESCRIPTION
Read Register Address
7
0
Address of the register to be read in the next cycle.
R/W
Soft Reset
1
0
Soft Reset. Writing 1 generates soft reset. Resets all the digital and
registers to default states. Writing 0 resumes normal chip operation.
R/W
Chip ID
24
97330h
Part Number, Description. Read reg00h returns chip ID.
Table 9. Reg 01h - Settings Register
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 25
BIT
TYPE
NAME
W
DEFLT
[0]
R/W
VCO Buffer Enable
1
1
Enables VCO input RF buffer.
DESCRIPTION
[1]
R/W
Reserved
1
1
Write 0 to this bit.
[2]
R/W
AUXSPI Enable
1
1
Enables Auxiliary SPI.
[3]
R/W
Sigma Delta Enable
1
1
Enables Sigma Delta Function.
[4]
R/W
GPIO Enable
1
1
Enables output from all GPIO pins.
[5]
R/W
RF Divider Enable
1
1
Enables RF Divider.
[6]
R/W
Output Buffer Enable
1
1
Enables Divider Output Driver.
[7]
R/W
Bias Enable
1
1
Enables bias generator for all blocks.
[8]
R/W
PSCLK to Digital Enable
1
1
Enable Prescaler clock going to digital counters.
[9]
R/W
Unused
1
1
Table 10. Reg 02h R-Divider Register
BIT
TYPE
[13:0]
R/W
NAME
R Divider Ratio
W
DEFLT
14
1h
DESCRIPTION
Local value for reference division ratio.
Auxiliary SPI Registers
The following two registers define the communication through the AUXSPI. If the AUXSPI is enabled (Reg 04h[4] = 0),
writes to AUXSPI are executed via Reg 03h. The auxiliary device address is expected in Reg 04h[2:0]. If HMC983LP5E
is working as a standalone frequency divider the AUXSPI clock is expected on the DNSAT pin, and Reg 04h[15] must
be set to 1. It is recommended to disable AUXSPI when not used.
Table 11. Reg 03h AUX. VCO Data Register
BIT
TYPE
NAME
W
DEFLT
[3:0]
R/W
AUXSPI Register Address
4
0h
[12:4]
R/W
AUXSPI Data
9
000h
DESCRIPTION
4-bit Register address for the auxiliary device SPI.
9-bit long Register Data for the auxiliary device SPI.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 12. Reg 04h - AUX. VCO Settings Register
TYPE
W
DEFLT
R/W
Auxiliary Device Address
NAME
3
000h
[3]
R/W
Divide Clock by 4 for AUXSPI
1
0
[4]
R/W
Start AUXSPI
1
0
[7:5]
R/W
Reserved
3
4h
[9:8]
R/W
Reserved
2
2h
[13:10]
R/W
Reserved
4
8h
[14]
R/W
Reserved
1
0
[15]
R/W
Keep Xtal Gate Open
1
0
[18:16]
R/W
Reserved
3
0h
DESCRIPTION
Chip address used by AUXSPI.
0 = Use XTAL for AUXSPI clock.
1 = Use XTAL divided by 4 for AUXSPI clock.
0 = Start AUXSPI when data is written to Reg03h.
1 = reserved.
When 1, keeps the XTAL gate open to get XTAL from the
companion PFD/CP chip HMC984LP4E.
Table 13. Reg 05h Integer Set-Point, Trigger Delay Register
BIT
TYPE
NAME
W
DEFLT
Integer Division Ratio
[19:0]
R/W
20
200d
DESCRIPTION
Sigma-Delta Modulator integer set point. Specifies the integer
part of the division ratio for the RF Divider in fractional mode or
the integer division ration in integer mode.
Also used as delay counter for hardware ramp trigger (Pin D4) in
ramp mode. This value is valid when Reg 0Eh [11] = 1.
Ramp Trigger Delay
Table 14. Reg 06h Fractional Set-Point, Down Dwell Register (MSB)
BIT
TYPE
NAME
W
DEFLT
Fractional Division Ratio (MSB)
[29:0]
R/W
Down Dwell for Asymmetric
Frequency. Ramp (MSB)
30
0
DESCRIPTION
Most significant 30 bits to specify fractional set point for SigmaDelta Modulator. Total Fractional bits are 48.
Defines the MSB portion of the dwell down time in the
asymmetric frequency sweep mode, valid when Reg 0Eh[11]=1.
Table 15. Reg 07h Fractional Set-Point, Down Dwell Register (LSB)
BIT
TYPE
NAME
W
DEFLT
Fractional Division Ratio (LSB)
[17:0]
R/W
Down Dwell for Asymmetric
Frequency. Ramp (LSB)
18
0
DESCRIPTION
Least significant 18 bits to specify fractional set point for SigmaDelta Modulator. Total Fractional bit are 48.
Defines the LSB portion of the dwell down time in the asymmetric
frequency sweep mode, valid when Reg0E[11]=1.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6
FREQUENCY DIVIDERS & DETECTORS - SMT
BIT
[2:0]
6 - 26
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 16. Reg 08h GPIO Configuration Register
BIT
TYPE
NAME
W
DEFLT
[3:0]
R/W
GPO Output Select
4
0h
[8:4]
R/W
GPO Static Test Value
5
00000b
Static GPIO test signals for output (D4,D3,D2,D1,D0). Writing
these value and reading them back test the GPIO functionality.
Master enable for GPIO Reg 01h[4] = 1 is required..
11111b
Independent GPIO pin enables.
Reg08[13] = 0 - D4 input
Reg08[13] = 1 - D4 output
Reg08[12] = 0, D3 input
Reg08[12] =1, D3 output
Reg08[11] = 0, D2 input
Reg08[11] = 1, D2 output
Reg08[10] = 0, D1 input
Reg08[10] = 1, D1 output
Reg08[9] = 0, D0 input
Reg08[9] = 1, D0 output
Master enable for GPIO Reg 01h[4] = 1 is required.
[13:9]
R/W
GPO Pin Enable
5
FREQUENCY DIVIDERS & DETECTORS - SMT
6
6 - 27
DESCRIPTION
Selects exported output signals to GPIO pins. See Table 5 for
details. Master enable for GPIO Reg 01h[4] = 1 is required..
Table 17. Reg 09h Companion Chip Address Local Register
BIT
TYPE
NAME
W
DEFLT
[2:0]
R/W
Counterpart HMC984LP4E Chip
Address
3
2h
DESCRIPTION
Chip address of the companion chip HMC984LP4E.
Table 18. Reg 0Ah Sigma Delta Modulator Seed MSB Register
BIT
TYPE
[29:0]
R/W
NAME
Seed MSB
W
DEFLT
30
4241h
DESCRIPTION
Most significant bits of the Seed for the 1st accumulator in
Sigma-Delta Modulator.
Table 19. Reg 0Bh Sigma Delta Modulator Seed LSB Register
BIT
[17:0]
TYPE
R/W
NAME
Seed LSB
W
18
DEFLT
10081h
DESCRIPTION
Least significant bits of the Seed for the 1st accumulator in
Sigma-Delta Modulator.
Table 20. Reg 0Ch Ramp NSTEP Down MSB Register
BIT
TYPE
[29:0]
R/W
NAME
Down Ramp Number of Steps
(MSB)
W
DEFLT
30
0h
DESCRIPTION
Most significant bits of the number of steps for the frequency
ramp in down direction in sweep mode.
Table 21. Reg 0Dh Ramp NSTEP Down LSB Register
BIT
TYPE
[17:0]
R/W
NAME
Down Ramp Number of Steps
(LSB)
W
DEFLT
18
0h
DESCRIPTION
Least significant bits of the number of steps for the frequency
ramp in down direction in sweep mode.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 22. Reg 0Eh Sigma Delta Modulator Configuration Register
TYPE
NAME
W
DEFLT
DESCRIPTION
DSM Type.
00 = MASH1 - Reserved
01 = MASH11 - Reserved
10 = MASH111 - Delta Sigma Modulator Mode B
11 - Delta Sigma Modulator Mode A
[1:0]
R/W
SD Modulator Type
2
11b
[2]
R/W
Ramp Auto Repeat Control from
SPI
1
0
Recommended to write 1 to this bit in ramp mode. When this bit
is 1, the ramp will repeat itself if ramp_auto_repeat_on/off_from_
spi is 1 at the end of the each sweep.
[3]
R/W
Ramp Auto Repeat Control from
SPI On/Off
1
0
Ramp will automatically repeat itself if this bit is 1 and bit 2 is
also set to 1.
Delay through the integer signal path to compensate for the
fractional path.
000 = no delay.
110 = 6 clock cycles delay.
111 = Automatic.
[6:4]
R/W
Integer Path Delay
3
111
[7]
R/W
Ramp Start Delay Enable
1
0
Delay the start of sweep as defined in Reg 05h
Reseed when changing the frac setpoint.
[8]
R/W
Autoseed Mode Enable
1
1
[9]
R/W
Reserved
1
0
[10]
R/W
Maintain DSM State Enable
1
0
Maintain DSM state within the same integer boundary.
[11]
R/W
Ramp Mode Enable
1
0
Puts DSM in frequency sweeper (ramp) mode.
[12]
R/W
Ramp Start from SPI
1
0
Start ramp signal from SPI.
[13]
R/W
Start Ramp from Ext. Trigger
1
0
Allow external trigger to manipulate ramp.
[14]
R/W
Bypass All
1
0
Bypass Delta Sigma Modulator. Place synthesizer in Integer
Mode without disabling the DSM.
[18:15]
R/W
CSP Step Size
4
1111b
Cycle Slip Prevention (CSP) step size. In a PLL configuration
with the HMC984LP4E one step is equivalent to one divided
VCO cycle, and step size is the number of VCO cycles.
[19]
R/W
External DSM Sequence Enable
1
0
Use external DSM sequence imported through GPIO Port.
[20]
R/W
Use Falling Edge of DSM Clock
for External Sequence
1
0
Use falling edge of SD clock to get the external sequence.
[21]
R/W
Lock using External Trigger Pin
1
0
Allow external trigger to start locking process. Writing to the
Integer or Fractional Division ratio registers does not have any
effect when this bit is set to 1. PLL will lock only when external
trigger goes high.
[22]
R/W
Symmetrical Ramp Mode
1
1
Use symmetric frequency sweeping for up and down directions
otherwise DN parameters are taken from Registers Reg 0Ch,
Reg 0Dh, Reg 19h and Reg 1Ah for asymmetric mode.
[23]
R/W
Integer Mode Lock Strobe
1
0
Re-lock when integer set-point Reg 06h is updated.
[24]
R/W
Singlestep Ramp Mode Enable
1
0
Single-step the ramp. Each step of the ramp must be popped by
strobe (either SPI or Hardware pin).
[25]
R/W
Single Direction Ramp Mode
Enable
1
0
Single direction mode for ramp (ramp one way, pop to base the
other way).
[26]
R/W
Ramp Start Direction
1
1
Starting direction of ramp. It is only loaded while rampmode = 0.
1 = Positive
0 = Negative
[27]
R/W
Use External Clock for DSM
1
0
1 = Use external clock from GPIO pin to clock DSM.
[28]
R/W
Reserved
1
0
[29]
R/W
Use x16 CSP Step
1
0
1 = Increase the CSP step size given in bits [18:15] by a factor
of 16.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6
FREQUENCY DIVIDERS & DETECTORS - SMT
BIT
6 - 28
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 23. Reg 0Fh VCO Divider Configuration Register
BIT
TYPE
[0]
R/W
[1]
R/W
NAME
W
DEFLT
DESCRIPTION
Increase Divider Pulse width
to DSM
1
0
Increase the width of the clock pulse going to DSM (available
only when division ratio > 64).
Increase Divider Pulsewidth to
PFD
1
1
Increase pulse width (low duration) of the clock going to PFD.
Sets current for divider output buffer. Helps to control voltage
swing for various impedance options.
000 = 5mA
001 = 7.5mA
[4:2]
R/W
Output Buffer Current Select
2
011b
010 = 10mA
011 = 12.5mA
100 = 10mA
6
101 = 12.5mA
110 = 15mA
FREQUENCY DIVIDERS & DETECTORS - SMT
111 = 17.5mA
6 - 29
[5]
R/W
Reset RF Divider
1
0
Resets the RF Divider.
[8:6]
R/W
Divider Resynch Bias Select
3
011b
Bias current setting for divider resync. Default value
recommended.
[11:9]
R/W
RF Buffer Bias Select
3
001b
Bias current setting for input RF buffer. Default value
recommended.
Divider output pulse width control.
000 = 5 VCO cycles.
001 = 13 VCO cycles.
010 = 21 VCO cycles.
[14:12]
R/W
Divider Pulsewidth Select
3
011b
011 = 29 VCO cycles.
100 = 37 VCO cycles.
101 = 45 VCO cycles.
110 = 53 VCO cycles.
111 = 61 VCO cycles.
Table 24. Reg 10h Ramp DWELL Symmetrical or Up MSB Register
BIT
[29:0]
TYPE
R/W
NAME
Symmetric Ramp Dwell (MSB)
W
30
DEFLT
DESCRIPTION
0
Represents MSB’s for ramp dwell time in up and down directions
for symmetric frequency sweep mode. In asymmetric mode it
represents the up dwell time only.
Table 25. Reg 11h Ramp DWELL Symmetrical or Up LSB Register
BIT
[17:0]
TYPE
R/W
NAME
Symmetric Ramp Dwell (LSB)
W
18
DEFLT
DESCRIPTION
0
Represents LSB’s for ramp dwell time in up and down directions
for symmetric frequency sweep mode. In asymmetric mode it
represents the up dwell time only.
Table 26. Reg 12h Ramp Step Size Symmetrical or Up MSB Register
BIT
[29:0]
TYPE
R/W
NAME
Symmetric Ramp Step Size
(MSB)
W
30
DEFLT
0
DESCRIPTION
Represents the MSB for ramp step size in up and down
directions for symmetric frequency sweep mode. In asymmetric
mode it represents the up step size only.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 27. Reg 13h Ramp Step Size Symmetrical or Up LSB Register
BIT
[17:0]
TYPE
R/W
NAME
Symmetric Ramp Step Size
(LSB)
W
DEFLT
DESCRIPTION
0
Represents the LSB for ramp step size in up and down directions
for symmetric frequency sweep mode. In asymmetric mode it
represents the up step size only.
18
Table 28. Reg 14h Ramp NSTEP Symmetrical or Up MSB Register
[29:0]
TYPE
R/W
NAME
Symmetric Ramp Number of
Steps (MSB)
W
DEFLT
30
0
DESCRIPTION
Represents the MSB of the number of steps for the frequency
ramp in up and down directions in symmetric frequency sweep
mode. In asymmetric mode it represents the number of steps in
up direction only.
Table 29. Reg 15h Ramp NSTEP Symmetrical or Up LSB Register
BIT
[17:0]
TYPE
R/W
NAME
W
Symmetric Ramp Number of
Steps (LSB)
DEFLT
18
0
DESCRIPTION
Represents the LSB of the number of steps for the frequency
ramp in up and down directions in symmetric frequency sweep
mode. In asymmetric mode it represents the number of steps in
up direction only.
Table 30. Reg 16h DSM Configuration Register
BIT
[1:0]
[3:2]
TYPE
R/W
R/W
NAME
W
DSM 1st Accumulator Size
DEFLT
2
DSM 2nd Accumulator Size
2
DESCRIPTION
00b
DSM 1st accumulator width.
00 = 48 bits
01 = 32 bits
10 = 24 bits
11 = 16 bits
00b
DSM 2nd accumulator width.
00 = 48 bits
01 = 32 bits
10 = 24 bits
11 = 16 bits
[5:4]
R/W
DSM 3rd Accumulator Size
2
00b
DSM 3rd accumulator width.
00 = 48 bits
01 = 32 bits
10 = 24 bits
11 = 16 bits
[8:6]
R/W
Disable Frac. Register Clock
3
000b
Clock gates for the 3 accumulators (fractional part), 1 disables
the clock.
[11:9]
R/W
Disable Integer Register Clock
3
000b
Clock gates for the 3 accumulators (integer part), 1 disables the
clock.
[12]
R/W
Disable DSM Mode A Clock
1
0
1 = Disable Delta Sigma Modulator Mode A Clock
[13]
R/W
Disable DSM Mode B Clock
1
0
1 = Disable Delta Sigma Modulator Mode B Clock
[14]
R/W
Reserved
1
0
[15]
R/W
Disable Integer Path Clock
1
0
1 = Disables Integer Path Clock
[16]
R/W
Disable Input Buffer Clock
1
0
1 = Disables Input Buffer Clock
[17]
R/W
Disable Output Buffer Clock
1
0
1 = Disables Output Buffer Clock
[18]
R/W
Reserved
1
0
[19]
R/W
Reserved
1
0
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6
FREQUENCY DIVIDERS & DETECTORS - SMT
BIT
6 - 30
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
Table 31. Reg 17h This Register does not exist
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
This Register does not exist
Table 32. Reg 19h Ramp Down Step Size MSB Register
TYPE
[29:0]
R/W
NAME
Ramp Step Down MSB.
W
DEFLT
30
0
DESCRIPTION
Represents MSB’s to define the step size for the ramp in down
direction in ramp mode.
Table 33. Reg 1Ah Ramp Down Step Size LSB Register
BIT
[17:0]
TYPE
R/W
NAME
Ramp Step Down LSB.
W
18
DEFLT
0
DESCRIPTION
Represents LSB’s to define the step size for the ramp in down
direction in ramp mode.
FREQUENCY DIVIDERS & DETECTORS - SMT
6
BIT
6 - 31
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMC983LP5E
v00.0911
DC - 7 GHZ FRACTIONAL-N DIVIDER
AND FREQUENCY SWEEPER
NOTES:
FREQUENCY DIVIDERS & DETECTORS - SMT
6
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
6 - 32