HOLTEK HT46R94

HT46R94
A/D Type 8-Bit MCU with 16´16 High Current LED Driver
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0049E Read and Write Control of the HT1380
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· 4096´15 program memory
fSYS=32768Hz: 2.2V~5.5V
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 192´8 data memory
· PFD for audio frequency generation
· Power down and wake-up functions to reduce
· 8 bidirectional I/O lines
power consumption
· Max. 16´16 LED driver output
· Up to 0.5ms instruction cycle with 8MHz system
· 8 LED shared I/O lines
clock at VDD=5V
· 24 LED shared output
· 8-level subroutine nesting
· External dual edge triggered interrupt input shared
· 8 channel 12-bit resolution A/D converter
with I/O line
· 3 channel 8-bit PWM output shared with I/O lines
· Two 8-bit programmable Timer/Event Counters with
· 1/2 bias 4 common LCD
overflow interrupt
· Bit manipulation instruction
· RC/XTAL and 32768Hz crystal oscillators
· Table read instructions
· Dual clock system offers three operating modes
- Normal mode: Both RC/XTAL and 32768Hz clock
· 63 powerful instructions
· All instructions executed in one or two machine
active
- Slow mode: 32768Hz clock only
- Power-down mode can have periodical wake-up
cycles
· Low voltage reset function
using the watchdog timer overflow
· 44/52-pin QFP package
· Watchdog Timer
General Description
The HT46R94 is an 8-bit high performance RISC architecture microcontroller, the device is designed especially for applications that interface directly to analog
signals, such as those from sensors. The devices include an integrated multi-channel Analog to Digital Converter in addition to two Pulse Width Modulation
outputs. An internal high current LED driver circuit also
provides for easy interfacing to applications which contain LED displays.
The benefits of integrated A/D and PWM functions, in
addition to low power consumption, high performance,
I/O flexibility and low-cost, provides the device with the
versatility to suit a wide range of application possibilities
such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers,
etc.
As is the case with all Holtek microcontroller devices,
the HT46R94 is fully supported by a full suite of
professional hardware and software tools, containing
comprehensive features to ensure user applications are
designed and debugged in as short a time as possible.
The usual Holtek MCU features such as power down
and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applications require a minimum of external components.
Rev. 1.10
1
November 5, 2008
HT46R94
Block Diagram
W a tc h d o g
T im e r
L E D
D r iv e r
O T P
P ro g ra m
M e m o ry
P W M
G e n e ra to r
R A M
D a ta
M e m o ry
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
In te rru p t
C o n tr o lle r
S ta c k
R C /C ry s ta l
O s c illa to r
L o w
V o lta g e
R e s e t
3 2 7 6 8 H z
O s c illa to r
8 - b it
T im e r
I/O
P o rts
P r o g r a m m a b le
F re q u e n c y
G e n e ra to r
8 - b it
T im e r
A /D
C o n v e rte r
Pin Assignment
P A
P A
P A
P A
P A
P A
P A
2 /T
3 /T
4 /P
5 /P
6 /P
O
O
O
O
S C
S C
V D
S C
S C
R E
0 /B
1 /B
M R
M R
W M
W M
W M
O
O
O
O
P A
P A
P A 2 /T
P A 3 /T
P A 4 /P
D
S C
S C
V D
S C
S C
R E
0 /B
1 /B
M R
M R
W M
S
Z
Z
2
1
0
1
0
1
2
4
3
D
S
Z
Z
2
1
3
4
0
1
0
P A 5 /P W M
P A 6 /P W M
P A 7 /P F
P E
P E
P E
V S S
P E
P E
P E
P E
2
D
2
E
6
5
4
1
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1
1
3 3
3 2
3
3 1
0
2
4
3 0
5
H T 4 6 R 9 4
4 4 Q F P -A
6
7
3
2 9
2 8
2 7
8
2 6
9
2 5
1 0
2 4
1 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
V S
V R
P B
P B
P B
P B
V D
P B
P B
P B
P B
P A 7 /P F
P E
P E
P E
V S S
P E
P E
P E
P E
P E
P D 0 /IN
P D
P D
S
E F
0 /A
1 /A
2 /A
3 /A
D B
4 /A
5 /A
6 /A
7 /A
N 0
N 1
N 2
N 3
N 4
N 5
N 6
N 7
P C
P C
P C
P C
V D
P C
P C
P C
P C
V S
P D
2
E
7
T
2
1
6
5
4
1
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
0
1
3 9
2
3 8
3
3 7
3 6
5
3 5
3
4
6
H T 4 6 R 9 4
5 2 Q F P -A
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
V S S
V R E
P B 0
P B 1
P B 2
P B 3
V D D
P B 4
P B 5
P B 6
P B 7
P C 7
P C 6
F
/A
/A
/A
/A
B
/A
/A
/A
/A
/C
/C
N 0
N 1
N 2
N 3
N 4
N 5
N 6
N 7
O M 3
O M 2
P C 5
P C 4
V D D
P C 3
P C 2
P C 1
P C 0
P D 7
P D 6
P D 5
V S S
P D 4
P D 3
7 /C
6 /C
5 /C
4 /C
D C
3
2
1
0
S D
0 /IN
2
/C O M 1
/C O M 0
C
D
O M 3
O M 2
O M 1
O M 0
T
Rev. 1.10
D
November 5, 2008
HT46R94
Pin Description
Pin Name
I/O
Configuration
Option
Description
PA0/BZ
Bidirectional 8-bit input/output port. Each individual pin on this port can be configPA1/BZ
Pull-high,
ured as a wake-up input by a configuration option. Software instructions deterPA2/TMR0
Wake-up,
mine if the pin is a CMOS output or Schmitt Trigger input. A configuration option
PA3/TMR1
BZ/BZ,
I/O
determines if all pins on the port have pull-high resistors. Pins PA0, PA1, PA2,
PA4/PWM0
PWM0~PWM2,
PA3, PA4, PA5, PA6 and PA7 are pin-shared with BZ, BZ, TMR0, TMR1, PWM0,
PA5/PWM1
PFD
PA6/PWM2
PWM1, PWM2 and PFD, respectively.
PA7/PFD
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
I/O
¾
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. PB is pin-shared with the A/D input pins.
The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function is disabled automatically.
PC0~PC3
PC4/COM0
PC5/COM1
PC6/COM2
PC7/COM3
O
¾
8-bit CMOS output port.
PC4~PC7 can be used as COM0~COM3.
PD0/INT
PD1~PD7
I/O
O
¾
8-bit CMOS output port. PD0 is pin-shared with the external interrupt input pin.
PE0~PE7
O
¾
8-bit CMOS output port.
OSC1
OSC2
I
O
OSC3
OSC4
I
O
¾
OSC3 and OSC4 are connected to an external 32768Hz crystal oscillator to implement a system clock and real time clock.
RES
I
¾
Schmitt Trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system
Crystal or RC
clock option is selected, pin OSC2 can be used to measure the system clock at
1/4 frequency.
VREF
A/D Reference voltage input pin.
VDDB
VDDC
¾
¾
PB & PC port positive power supply
VSSD,
VSSE
¾
¾
PD & PE port negative power supply, ground
Note:
1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. As the table applies to the larger package size not all pins may exist on the smaller packages.
Rev. 1.10
3
November 5, 2008
HT46R94
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Operating Voltage
5.5
¾
fSYS=4MHz
2.2
¾
5.5
¾
fSYS=8MHz
3.3
¾
5.5
V
2.7
¾
5.5
V
¾
1
2
mA
¾
2.5
5
mA
No load, fSYS=8MHz,
ADC disable
¾
4
8
mA
No load,
fSYS=32768Hz,
ADC disable
¾
20
40
mA
¾
50
100
mA
¾
3
5
mA
¾
6
10
mA
¾
1
2
mA
¾
2
4
mA
¾
2
4
mA
¾
4
8
mA
¾
¾
1
mA
¾
¾
2
mA
¾
30
50
mA
IDD1
Operating Current
(Crystal OSC, RC OSC)
3V
No load, fSYS=4MHz,
ADC disable
ISTB1
ISTB2
ISTB3
Standby Current
(WDT & RTC* Enabled)
Standby Current
(WDT Disabled, RTC* Enabled)
Standby Current
(WDT Enabled & RTC* Disabled)
V
¾
VAVDD=VDD
Operating Current
(RTC* OSC, RC Off)
Unit
2.2
¾
IDD3
Max.
fSYS=32768Hz
Analog Operating Voltage
Operating Current
(RC OSC, RTC OSC)
Typ.
¾
VAVDD
IDD2
Min.
Conditions
VDD
5V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
No load,
system HALT
No load,
system HALT
No load,
system HALT
ISTB4
Standby Current
(WDT & RTC* Disabled)
ISTB5
Standby Current with 200K (see
note 2) Resistor On for 1/2 VDD
Bias (WDT & RTC Disabled)
3V
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
1.98
2.1
2.22
V
2.98
3.15
3.32
V
3.98
4.2
4.42
V
VLVR
IOL1
Rev. 1.10
Low Voltage Reset
5V
No load,
system HALT
No load,
system HALT
¾
¾
3V
VOL=0.1VDD
4
8
¾
mA
5V
VOL=0.1VDD
10
20
¾
mA
I/O Port Sink Current for PA
4
November 5, 2008
HT46R94
Test Conditions
Symbol
Parameter
IOL2
I/O Port Source Current for PB,
PC
I/O Port Source Current for PD,
PE
IOH3
RPH
Unit
0.6
1.3
¾
mA
5V
VOL=0.1VDD
1.5
3.0
¾
mA
3V
VOL=0.1VDD
12
24
¾
mA
5V
VOL=0.1VDD
30
60
¾
mA
3V
VOH=0.9VDD
-2
-4
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
3V
VOH=0.9VDD
-4
-8
¾
mA
5V
VOH=0.9VDD
-10
-20
¾
mA
3V
VOH=0.9VDD
0.25
0.5
¾
mA
5V
VOH=0.9VDD
0.5
1.0
¾
mA
I/O Port Source Current for PA
IOH2
Max.
VOL=0.1VDD
I/O Port Sink Current for PD, PE
IOH1
Typ.
3V
I/O Port Sink Current for PB, PC
IOL3
Min.
Conditions
VDD
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
2.3
2.5
2.7
V
0
¾
VREF
V
V
Pull-high Resistance
0.5VDD Bias Voltage (see note 3)
5V
VAD
A/D Input Voltage
¾
VREF
A/D Input Reference Voltage
Range
¾
VAVDD=2.7V~5.5V
1.6
¾
VAVDD+
0.1
DNL
A/D Differential Non-Linearity
¾
-2
¾
2
LSB
INL
A/D Integral Non-Linearity
¾
VAVDD=5V,
VREF=VAVDD,
tAD=0.5ms
-4
¾
4
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1.0
mA
¾
1.5
3.0
mA
VBIAS
Note:
¾
¾
5V
1. * RTC OSC in slow mode for test condition.
2. set ²LCDEN²=1, set ²COM0EN²=1, reset ²RSEL²=0 in LCDC (1FH) register for ISTB5 measurement.
3. VBIAS voltage is design guarantee. Not for test.
4. VAVDD is the analog circuit supply voltage which does not have an external pin but is connected to VDD inside
the device.
Rev. 1.10
5
November 5, 2008
HT46R94
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS1
System Clock (RC OSC)
fSYS2
System Clock (RTC OSC)
fTIMER
Timer I/P Frequency (TMR)
tWDTOSC
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
¾
32768
¾
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
With prescaler
(fS/4096)
184
369
737
ms
131
266
532
ms
With prescaler
(fS/4096)
¾
125
¾
ms
Watchdog Oscillator Period
3V
fFSP1
fSP Time-out Period Clock
Source form WDT
5V
tFSP2
fSP Time-out Period Clock
Source form RTC
¾
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Wake-up from HALT
¾
1024
¾
*tSYS
tLVR
Low Voltage Reset Time
¾
¾
0.25
1
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
0.5
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
16
¾
tAD
Note: *tSYS=1/fSYS1 or 1/fSYS2
Rev. 1.10
6
November 5, 2008
HT46R94
System Architecture
A key factor in the high-performance features of the
Holtek microcontrollers is attributed to the internal system architecture. The range of devices take advantage
of the usual features found within RISC microcontrollers
providing increased speed of operation and enhanced
performance. The pipelining scheme is implemented in
such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively
executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically
all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data
path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O and A/D control system with maximum reliability and flexibility.
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
Clocking and Pipelining
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. However, it
must be noted that only the lower 8 bits, known as the
Program Counter Low Register, are directly addressable by user.
When the RC oscillator is used, OSC2 is freed for use as
a T1 phase clock synchronising pin. This T1 phase clock
has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
Program Counter
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
:
5
:
D E L A Y :
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
4
6
F e tc h In s t. 1
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.10
7
November 5, 2008
HT46R94
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
data nor part of the program space, and is neither be
read nor written to. The activated level is indexed by the
Stack Pointer, SP, and can neither be read nor written
to. At a subroutine call or interrupt acknowledge signal,
the contents of the Program Counter are pushed onto
the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the
Program Counter is restored to its previous value from
the stack. After a device reset, the Stack Pointer will
point to the top of the stack.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and can be read nor written to. By transferring data directly into this register, a short program
jump can be executed directly, however, as only this low
byte is available for manipulation, the jumps are limited
to the present page of memory, that is 256 locations.
When such program jumps are executed it should also
be noted that a dummy cycle will be inserted.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
P ro g ra m
T o p o f S ta c k
C o u n te r
S ta c k L e v e l 1
S ta c k L e v e l 2
Stack
S ta c k
P o in te r
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organised into 8 levels and is neither part of the
B o tto m
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l 8
Program Counter Bits
Mode
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Time Base Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
Skip
Program Counter + 2
Loading PCL
PC11
PC10 PC9 PC8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
@[email protected]: PCL bits
#11~#0: Instruction code address bits
S11~S0: Stack register bits
The Program Counter is 12 bits wide, i.e. from b11~b0.
Rev. 1.10
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November 5, 2008
HT46R94
· Location 008H
Arithmetic and Logic Unit - ALU
This internal vector is used by the Timer/Event Counter 0. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter interrupt is enabled and the stack
is not full.
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
· Location 00CH
This internal vector is used by the Timer/Event Counter 1. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter interrupt is enabled and the stack
is not full.
· Location 010H
This internal vector is used by the Time Base interrupt.
If a Time Base interrupt occurs, the program will jump
to this location and begin execution if the time base interrupt is enabled and the stack is not full.
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Location 014H
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
This internal vector is used by the A/D converter.
When an A/D conversion cycle is complete, the program will jump to this location and begin execution if
the A/D interrupt is enabled and the stack is not full.
RLC
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
0 0 0 H
Program Memory
0 0 4 H
The Program Memory is the location where the user code
or program is stored. For this device, the type of memory
is One-Time Programmable, OTP, memory where users
can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications
which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices
are also applicable for use in applications that require low
or medium volume production runs.
0 0 8 H
0 0 C H
0 1 0 H
0 1 4 H
F F F H
Structure
The Program Memory has a capacity of 4K by 15 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by
separate table pointer registers.
E x te rn a l
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 0
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 1
In te rru p t V e c to r
T im e B a s e
In te rru p t V e c to r
A /D C o n v e rte r
In te rru p t V e c to r
1 5 b its
Program Memory Structure
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
· Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device receives a rising or
falling transition, the program will jump to this location
and begin execution if the external interrupt is enabled
and the stack is not full.
Rev. 1.10
In itia lis a tio n
V e c to r
9
November 5, 2008
HT46R94
microcontroller. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H² which refers to the start address of the last page
within the 4K Program Memory. The table pointer is setup
here to have an initial value of ²06H². This will ensure that
the first data read from the data table will be at the Program Memory address ²F06H² or 6 locations after the start
of the last page. Note that the value for the table pointer is
referenced to the first address of the present page if the
²TABRDC [m]² instruction is being used. The high byte of
the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the
²TABRDL [m]² instruction is executed.
register. Any unused bits in this transferred higher order
byte will be read as ²0².
The accompanying diagram illustrates the addressing/data flow of the look-up table:
P ro g ra m C o u n te r
H ig h B y te
P ro g ra m
M e m o ry
T B L P
T B L H
S p e c ifie d b y [m ]
T a b le C o n te n ts H ig h B y te
T a b le C o n te n ts L o w
B y te
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the
tempreg1
tempreg2
db
db
:
:
?
?
; temporary register #1
; temporary register #2
mov
a,06h
; initialise table pointer - note that this address
; is referenced
mov
tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1
;
;
;
;
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²F06H² transferred to
tempreg1 and TBLH
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
:
:
org
F00h
dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Instruction
Table Location Bits
b11
TABRDC [m] PC11
TABRDL [m]
; sets initial address of last page
1
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits
@[email protected]: Table Pointer TBLP bits
The Table address location is 12 bits, i.e. from b11~b0.
Rev. 1.10
10
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HT46R94
dress ²00H². Registers which are common to all
microcontrollers, such as ACC, PCL, etc., have the
same Data Memory address.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
General Purpose Data Memory
All programs require an area of read/write memory
where temporary data can be stored and retrieved for
use later. It is this area of RAM memory that is known as
General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read
and write operations. By using the ²SET [m].i² and ²CLR
[m].i² instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.
0 0
0 1
0 2
0 3
0 4
0 5
0 6
0 7
0 8
0 9
0 A
0 B
0 C
0 D
0 E
0 F
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
1 A
1 B
1 C
1 D
1 E
1 F
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
0 0 H
S p e c ia l P u r p o s e
D a ta M e m o ry
3 F H
4 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
F F H
Data Memory Structure
Note:
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer registers MP0 and
MP1.
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
H
H
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are
8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start
address of the Data Memory for all devices is the ad-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
IA
M
IA
M
R 0
P 0
R 1
P 1
A C
P C
T B
T B
C
L
L P
L H
S T A T U S
IN T C 0
H
H
H
T M R 0
T M R 0 C
H
H
H
H
H
H
T M R 1
T M R 1 C
P A
P A C
P B
P B C
P C
P D
H
H
H
3 F H
Structure
Rev. 1.10
H
H
H
H
H
H
H
P E
P W M
P W M
P W M
IN T C
L C D
M O D
A D
A D
A D
A C
0
1
C
1
2
E
R L
R H
C R
S R
: U n u s e d , re a d a s "0 0 "
Special Purpose Data Memory
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HT46R94
Special Purpose Data Memory
Indirect Addressing Registers - IAR0, IAR1
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Special Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
The IAR0 and IAR1 registers, located at Data Memory
addresses 00H and 02H, are not physically implemented. These special function registers allows what is
known as indirect addressing, which permits data manipulation using Memory Pointers instead of the usual
direct memory addressing method where the actual
memory address is defined. Any actions on the IAR0
and IAR1 registers will result in corresponding
read/write operations to the memory locations specified
by the Memory Pointers MP0 and MP1. Reading the
IAR0 and IAR1 registers indirectly will return a result of
²00H² and writing to the register indirectly will result in
no operation.
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control and
A/D converter operation. The location of these registers
within the Data Memory begins at the address 00H. Any
unused Data Memory locations between these special
function registers and the point where the General Purpose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of 00H.
Memory Pointer - MP0, MP1
Two Memory Pointers, known as MP0 and MP1, are
physically implemented in Data Memory. The Memory
Pointer can be written to and manipulated in the same
way as normal registers providing an easy way of addressing and tracking data. When using any operation
on the indirect addressing register IAR0 or IAR1, it is actually the address specified by the Memory Pointer that
the microcontroller will be directed to.
The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
; setup size of block
block,a
a,offset adres1 ; Accumulator loaded with first RAM address
mp0,a
; setup memory pointer with first RAM address
clr
inc
sdz
jmp
IAR0
mp0
block
loop
loop:
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Rev. 1.10
12
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HT46R94
Accumulator - ACC
Status Register - STATUS
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Look-up Table Registers - TBLP, TBLH
· Z is set if the result of an arithmetic or logical operation
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.10
13
November 5, 2008
HT46R94
PC, PD and PE are output ports only and therefore do
not have control registers.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Setting its output register high which effectively places
its NMOS output transistor in high impedance state. Resetting output register to low will force to output low
state.
Interrupt Control Registers - INTC0, INTC1
Pulse Width Modulator Registers PWM0, PWM1, PWM2
These 8-bit registers, known as INTC0 and INTC1, control the operation of both the external and internal interrupts. By setting various bits within these registers using
standard bit manipulation instructions, the enable/disable function of the external interrupts and each of the
internal interrupts can be independently controlled. A
master interrupt bit within these registers, the EMI bit,
acts like a global enable/disable and is used to set all of
the interrupt enable bits on or off. This bit is cleared
when an interrupt routine is entered to disable further interrupt and is set by executing the RETI² instruction.
The device contains three Pulse Width Modulators.
Each one has its own related independent control register, with the names PWM0, PWM1 and PWM2. The 8-bit
contents of these registers, defines the duty cycle value
for the modulation cycle of the corresponding Pulse
Width Modulator.
A/D Converter Registers - ADRL, ADRH,
ADCR, ACSR
The device contains a 8-channel 12-bit A/D converter.
The correct operation of the A/D requires the use of two
data registers, a control register and a clock source register. A high byte data register known as ADRH, and a
low byte data register known as ADRL. These are the
register locations where the digital value is placed after
the completion of an analog to digital conversion cycle.
The channel selection and configuration of the A/D converter is setup via the control register ADCR while the
A/D clock frequency is defined by the clock source register, ACSR.
Timer/Event Counter Registers - TMR0, TMR0C,
TMR1, TMR1C
The device contains two integrated 8-bit count up Timer/
Event Counters. These have associated registers
known as TMR0 and TMR1, where the timer¢s values
are located. Two associated control registers, known as
TMR0C and TMR1C contain the setup information for
these two timers. Note that all timer registers can be directly written to in order to preload their contents with
fixed data to allow different time intervals to be setup.
Mode Register - MODE
Input/Output Ports and Control Registers
The Mode Register is used to select the Mode of Operation which can be either Normal, Slow or Power-down. It
also contains a bit to control the quick start up function of
the 32768Hz oscillator.
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O and output ports have a designated register correspondingly labeled as PA, PB, PC,
PD and PE. These labeled I/O registers are mapped to
specific addresses within the Data Memory as shown in
the Data Memory table, which are used to transfer the
appropriate output or input data on that port. For the I/O
ports, PA and PB, there is an associated control register
labeled PAC and PBC, also mapped to specific addresses with the Data Memory. The control register
specifies which pins of that port are set as inputs and
which are set as outputs. To setup a pin as an input, the
corresponding bit of the control register must be set
high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are
inputs before reading data from or writing data to the I/O
ports. One flexible feature of these registers is the ability
to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
Rev. 1.10
LCD Control Register - LCDC
The LCDC register is used to setup various functions for
the LCD display. Functions such as 1/2 bias enable for
each COM line, bias resistor and LCD enable are setup
with this register.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of
PA, PB pin fully under user program control, pull-high
options and wake-up options on PA pins, the user is provided with an I/O structure to meet the needs of a wide
range of application possibilities.
The device offers up to 16 bidirectional input/output
lines on ports PA and PB. There are also outputs on
ports PC, PD and PE. These I/O ports are mapped to
the Data Memory with specific addresses as shown in
the Special Purpose Data Memory table. For input operation, these ports are non-latching, which means the in14
November 5, 2008
HT46R94
puts must be ready at the T2 rising edge of instruction
²MOV A,[m]², where m denotes the port address. For
output operation, all the data is latched and remains unchanged until the output latch is rewritten.
come. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
· External Interrupt Input
Pull-high Resistors
The external dual edge triggered interrupt pin INT is
pin-shared with the output pin PD0. The pin can be
configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has been set and the PD0 output is disabled by
setting the LCDEN bit in the LCDC register to zero and
the PD0 bit set high. If the external interrupt enable bit
is not set then the pin can be used as a PD0 CMOS
output pin.
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all pins on Port A, when configured as an input
have the capability of being connected to an internal
pull-high resistor. These pull-high resistors are
selectable via a configuration option and are implemented using a weak PMOS transistor.
· External Timer Clock Input
The external timer pins TMR0 and TMR1 are
pin-shared with the I/O pins PA2 and PA3, respectively. To configure these pins to operate as timer inputs, the corresponding control bits in the timer
control register must be correctly set. For applications
that do not require an external timer input, these pins
can be used as normal I/O pins. Note that if used as
normal I/O pins the timer mode control bits in the timer
control register must select the timer mode, which has
an internal clock source, to prevent the input pin from
interfering with the timer operation.
Port A Wake-up
Each device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port A pins from high to
low. After a HALT instruction forces the microcontroller
into entering a Power Down condition, the device will remain in a low-power state until a Port A pin receives a
high to low going edge. This function is especially suitable for applications that can be woken up via external
switches. Note that each pin on Port A can be selected
individually to have this wake-up feature.
· PFD Output
Each device contains a PFD function whose single
output is pin-shared with PA7. The output function of
this pin is chosen via a configuration option and remains fixed after the device is programmed. Note that
the corresponding bit of the port control register,
PAC.7, must setup the pin as an output to enable the
PFD output. If the PAC port control register has setup
the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if
the PFD configuration option has been selected.
I/O Port Control Registers
As PA and PB are I/O ports, they each have a port control register, known as PAC and PBC, to control the input/output configuration. With these control registers,
each CMOS output or input on these ports with or without pull-high resistor structures can be reconfigured dynamically under configuration option. Each pin of the I/O
ports is directly mapped to a bit in its associated port
control register. For the I/O pin to function as an input,
the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the
corresponding bit of the control register is written as a
²0², the I/O pin will be setup as a CMOS output. If the pin
is currently setup as an output, instructions can still be
used to read the output register. However, it should be
noted that the program will in fact only read the status of
the output data latch and not the actual logic status of
the output pin.
· PWM Outputs
The devices contain three PWM outputs PWM0,
PWM1 and PWM2 are pin shared with pins PA4, PA5
and PA6, respectively. The PWM output functions are
chosen via configuration options and remain fixed after the device is programmed. Note that the corresponding bit or bits of the port control register, PAC,
must setup the pin as an output to enable the PWM
output. If the PAC port control register has setup the
pin as an input, then the pin will function as a normal
logic input with the usual pull-high option, even if the
PWM configuration option has been selected.
· A/D Inputs
The device has 8 A/D converter inputs. All of these analog inputs are pin-shared with I/O pins on Port B. If
these pins are to be used as A/D inputs and not as
normal I/O pins then the corresponding bits in the A/D
Converter Control Register, ADCR, must be properly
set. There are no configuration options associated
with the A/D function. If used as I/O pins, then full
pull-high resistor configuration options remain, however if used as A/D inputs then any pull-high resistor
options associated with these pins will be automatically disconnected.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be over-
Rev. 1.10
15
November 5, 2008
HT46R94
I/O Pin Structures
registers, PAC and PBC, are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated port data
registers, PA and PB, are first programmed. Selecting
which pins are inputs and which are outputs can be
achieved byte-wide by loading the correct values into
the appropriate port control register or by programming
individual bits in the port control register using the ²SET
[m].i² and ²CLR [m].i² instructions. Note that when using
these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in
the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output
ports.
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied as
a guide only to assist with the functional understanding
of the I/O pins.
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data
(except PC) and port control registers will be set high.
This means that all of the PC, PD and PE output pins will
be in a output floating condition. Also all the PA and PB
I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether
pull-high options have been selected. If the port control
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
V
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
D D
P u ll- H ig h
O p tio n
C o n tr o l B it
Q
D
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
C K
W r ite D a ta R e g is te r
S
Q
M
P F D , P W M
o r B Z /B Z
M
R e a d D a ta R e g is te r
S y s te m
P A
P A
P A
P A
P A
P A
P A
P A
D a ta B it
Q
D
U
U
0 /B
1 /B
2 /T
3 /T
4 /P
5 /P
6 /P
7 /P
Z
Z
M R
M R
W M
W M
W M
F D
1
0
0
1
2
X
P F D , P W M o r
B Z /B Z O p tio n
X
W a k e - u p ( P A o n ly )
W a k e - u p O p tio n
T M R 0 fo r P A 2 o n ly
T M R 1 fo r P A 3 o n ly
PA Input/Output Ports
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
V
D D
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P B
P B
P B
P B
P B
P B
P B
P B
D a ta B it
Q
D
C K
S
Q
0 /A
1 /A
2 /A
3 /A
4 /A
5 /A
6 /A
7 /A
N 0
N 1
N 2
N 3
N 4
N 5
N 6
N 7
L C D E N
M
R e a d D a ta R e g is te r
P C R 2
P C R 1
P C R 0
T o A /D
U
X
A n a lo g
In p u t
S e le c to r
C o n v e rte r
A C S 2 ~ A C S 0
PB Input/Output Ports
Rev. 1.10
16
November 5, 2008
HT46R94
V
D D
D a ta B it
Q
D
D a ta B u s
W r ite D a ta R e g is te r
C K
Q
R
P C 0 ~ P C 3
C h ip R e s e t
R e a d D a ta R e g is te r
L C D E N
PC0~PC3 Output Ports
V
D D
D a ta B it
D a ta B u s
W r ite D a ta R e g is te r
Q
D
C K
Q
R
P C
P C
P C
P C
C h ip R e s e t
L C D E N
R e a d D a ta R e g is te r
4 /C
5 /C
6 /C
7 /C
O M
O M
O M
O M
0
1
2
3
L C D E N
C O M 0 E N ~ C O M 3 E N
V D D
E N
V
D D
/2
C M O S T r a n s m is s io n G a te
S in g le s h a r e d b ia s
c ir c u it fo r a ll C O M p in s
PC4~PC7 Output Ports
V
D D
L C D E N
P D 0 /IN T
D a ta B it
D a ta B u s
Q
D
W r ite D a ta R e g is te r
C K
Q
S
C h ip R e s e t
R e a d D a ta R e g is te r
IN T In p u t
PD0 Input/Output Port
V
D D
L C D E N
P D 1 ~ P D 7
P E 0 ~ P E 7
D a ta B it
D a ta B u s
W r ite D a ta R e g is te r
Q
D
C K
S
Q
C h ip R e s e t
R e a d D a ta R e g is te r
PD1~PD7, PE Output Ports
Rev. 1.10
17
November 5, 2008
HT46R94
1/2 Bias LCD Control
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
As the device may be conveniently used for driving LCD
panels, pins PC4~PC7 and other I/O ports can be used
together to implement 1/2 bias LCD timing signals.
COM0~3 can be sourced from the PC4~7 pins while the
SEGMENTS can be sourced from other I/O ports. The
internal 1/2 bias circuit is enabled via a combination of
the LCDEN and COM0EN~COM3EN bits in the LCDC
register. The RSEL bit in the LCDC register selects the
bias circuit resistor values which should be chosen according to the actual LCD panel used and to minimise
current consumption. Note that there is only one bias
circuit which is shared by all the COM outputs.
LCD Driver Function
The device contains circuitry to control an external LCD.
This function is controlled using the LCDC register.
LCD Driver Operation
When the LCDEN bit in the LCDC register is set high
and PB is configured as an output, ports PB, PC, PD
and PE become CMOS outputs, but have lower
sink/source capabilities making them suitable for LCD
segment driving. Following a power-on reset, port PB
will be setup as an input port, while PC is setup as a
PMOS output port while PD and PE are setup as NMOS
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
LCDC Register
1/2 Bias
LCDEN COM3EN COM2EN COM1EN COM0EN On/Off
T 4
C lo c k
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
0
x
x
x
x
Off
1
0
0
0
0
Off
1
0
0
0
1
On
:
:
:
:
:
:
:
:
:
:
ON
1
1
1
1
1
ON
Read/Write Timing
1/2 Bias Circuit Control
output ports, making them suitable for LED driving.
However at this time, as the LCDEN bit is low, the PC,
PD and PE outputs will be in an open-drain high-impedance condition. To setup ports PB~PE as CMOS outputs, the LCDEN bit must be set high. It is important to
note that PB and PC have a lower sink ability (IOL2) while
PD and PE have a lower driving ability (IOH3). The D.C.
Characteristics provide for further information.
The following steps can be used to implement LCD
timing:
· Select the bias resistor by setting RSEL=0 or 1
· Set LCDEN=1
· Use software to generate the VDD, VSS, VDD/2 volt-
ages by changing COM pins PC4~7 to output high,
output low and input respectively.
· Generate the segment timing using other I/O ports
with outputs equal to either VSS or VDD.
b 7
R S E L
L C D E N
C O M 3 E N
C O M 2 E N
C O M 1 E N
b 0
C O M 0 E N
L C D C
R e g is te r
1 /2 B ia s C O M 0 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
1 /2 B ia s C O M 1 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
1 /2 B ia s C O M 2 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
1 /2 B ia s C O M 3 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
L C D e n a b le /d is a b le C o n tr o l
1 : e n a b le
0 : d is a b le
S e le c t r e s is to r fo r R ty p e L C D b ia s c u r r e n t
1 : 2 x 5 0 k W ( 1 / 2 b ia s ) , I B IA S = 5 0 m A a t V D D = 5 V
0 : 2 x 1 0 0 k W ( 1 / 2 b ia s ) , I B IA S = 2 5 m A a t V D D = 5 V
N o t im p le m e n te d , r e a d a s " 0 "
LCD Control Register
Rev. 1.10
18
November 5, 2008
HT46R94
Timer/Event Counters
ditioned by the timer control register bits
P1SC0~P1SC2 or P0SC0~ P0SC2.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The device contains two 8-bit
count up timers. With three different operating modes,
the timers can be configured to operate as a general
timer, an external event counter or as a Pulse Width
Measurement device. The provision of a prescaler in the
input clock circuitry of each Timer/Event Counter gives
added range to the timer.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on an external timer pin, TMR0 or TMR1 depending
upon which timer is used. Depending upon the condition
of the T0E or T1E bit, each high to low, or low to high
transition on the external timer pin will increment the
counter by one.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register
retrieves the contents of the Timer/Event Counter. The
second type of associated register is the timer control
register which defines the timer options and determines
how the timer is to be used. The devices can have the
timer clock configured to come from the internal clock
source. In addition, the timer clock source can also be
configured to come from an external timer pin.
Timer Register - TMR0, TMR1
The timer register are special function register location
within the special purpose Data Memory where the actual timer value is stored. These registers have the
names TMR0 and TMR1. The value in the timer registers increases by one each time an internal clock pulse
is received or an external transition occurs on the external timer pin. The timer will count from the initial value
loaded by the preload register to the full count value of
FFH at which point the timer overflows and an internal
interrupt signal generated. The timer value will then be
reset with the initial preload register value and continue
counting. To achieve a maximum full range count of FFH
the preload register must first be cleared to 00H. It
should be noted that after power-on the preload register
will be in an unknown condition. Note that if the
Timer/Event Counter is not running and data is written to
its preload register, this data will be immediately written
into the actual counter. However, if the counter is enabled and counting, any new data written into the
preload register during this period will remain in the
preload register and will only be written into the actual
counter the next time an overflow occurs.
Configuring the Timer/Event Counter Input Clock
Source
The internal timer¢s clock can originate from various
sources, depending upon which timer is chosen. For
Timer/Event Counter 0 the clock source is chosen via a
configuration option while for Timer/Event Counter 1 the
clock source is chosen using the T1S bit in the TMR1C
register. The internal clock input timer source is used
when the timer is in the timer mode or in the pulse width
measurement mode. The clock timer source is also first
divided by a prescaler, the division ratio of which is con-
9 - B it C o u n te r
W D T T im e - o u t
D a ta B u s
fS
/4
R T C O S C
W D T O S C
Y S
M
U
X
fS
P 0 S C 2 ~ P 0 S C 0
(1 /2 ~
1 /2 5 6 )
fS /1 6
fS
fS
P r e s c a le r
¸ 1 6
/4
Y S
M
P
U
f IN
X
T 0 M 1
C o n fig u r a tio n
O p tio n
C o n fig u r a tio n O p tio n
8 - B it T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
T
T 0 M 0
8 - B it T im e r /E v e n t
C o u n te r 0 (T M R 0 )
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T M R 0
R e lo a d
T 0 E
O v e r flo w
to In te rru p t
T 0 O N
8-bit Timer/Event Counter 0 Structure
D a ta B u s
P 1 S C 2 ~ P 1 S C 0
fS
Y S
R T C O S C
M
U
fS 1
X
T 1 S
T im e r /E v e n t C o u n te r 1
P r e lo a d R e g is te r
f IN
P r e s c a le r
T 1
T 1 M 0
T 0 M 0
T im e r /E v e n t C o u n te r
(T M R 1 )
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T M R 1
R e lo a d
T 1 E
T 1 O N
O v e r flo w
to In te rru p t
¸ 2
P F D
8-bit Timer/Event Counter 1 Structure
Rev. 1.10
19
November 5, 2008
HT46R94
b 7
b 0
T 0 M 1 T 0 M 0
T 0 O N
T 0 E
P 0 S C 2 P 0 S C 1 P 0 S C 0
T M R 0 C
R e g is te r
T im e r P r e s c a le r R a te
P 0 S C 2 P 0 S C 1
P 0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
S e le c t
S C 0
T im e r
0
1 :2
1
1 :4
0
1 :8
1
1 :1
0
1 :3
1
1 :6
1 :1
0
1 :2
1
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
R a te
6
2
4
2 8
5 6
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r 0 C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g
T 0 M 1
T
0
0
1
1
M o d e S e le c t
0 M 0
n o m o d
0
e v e n t c
1
tim e r m
0
p u ls e w
1
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
b 7
T 1 M 1 T 1 M 0
b 0
T 1 S
T 1 O N
T 1 E
P 1 S C 2
P 1 S C 1
P 1 S C 0
T M R 1 C
R e g is te r
T im e r P r e s c a le r R a te
P 1 S C 2
P 1 S C 1 P 1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
S e le c t
S C 0
0
1
0
1
0
1
0
1
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
T im e r
1 :2
1 :4
1 :8
1 :1
1 :3
1 :6
1 :1
1 :2
6
R a te
2
4
2 8
5 6
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r 1 C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
T M R 1 T im e r /E v e n t C o u n te r in te r n a l c lo c k s o u r c e
1 : 3 2 7 6 8 H z
0 : fS Y S
O p e r a tin g M o d e S e
T 1 M 1
T 1 M 0
0
n o
0
0
e v
1
1
tim
0
1
p u
1
le c t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
Rev. 1.10
20
November 5, 2008
HT46R94
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 2
T im e r + 1
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
Timer Control Register - TMR0C, TMR1C
In this mode, a choice of internal clocks can be used as
the Timer/Event Counter clock, depending upon which
Timer/Event Counter is being used. However, this clock
source is further divided by a prescaler, the value of
which is determined by the Prescaler Rate Select bits,
which are bits 0~2 in the respective Timer Control Register. After the other bits in the Timer Control Register
have been setup, the enable bit, which is bit 4 of the
Timer Control Register, can be set high to enable the
Timer/Event Counter to run. Each time an internal clock
cycle occurs, the Timer/Event Counter increments by
one. When it is full and overflows, an interrupt signal is
generated and the Timer/Event Counter will reload the
value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in
the Interrupt Control Register, is reset to zero.
The flexible features of the Holtek microcontroller Timer/
Event Counters enable them to operate in three different
modes, the options of which are determined by the contents of their respective control register. The device contains two timer control registers known as TMR0C and
TMR1C. It is the timer control register together with its
corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can
be used, it is essential that the appropriate timer control
register is fully programmed with the right data to ensure
its correct operation, a process that is normally carried
out during program initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
or the Pulse Width Measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
pair T0M1/T0M0 or T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer
Control Register and known as T0ON or T1ON, depending upon which timer is used, provides the basic on/off
control of the respective timer. Setting the bit high allows
the counter to run, clearing the bit stops the counter. The
Timer/Event Counters also contains a prescaler function, with bits 0~2 of the associated Timer Control Register determining the division ratio of the input clock. The
prescaler bit settings have no effect if an external clock
source is used. If the timer is in the Event Count or Pulse
Width Measurement mode, the active transition edge
level type is selected by the logic level of bit 3 of the
Timer Control Register which is known as T0E or T1E,
depending upon which timer is used.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pins, can be recorded by the Timer/Event Counters. To operate in this
mode, the Operating Mode Select bit pair in the appropriate Timer Control Register must be set to the correct
value as shown.
Bit7 Bit6
Control Register Operating Mode
Select Bits for the Event Counter Mode
0
1
In this mode the external timer pins are used as the
Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the
appropriate Timer Control Register have been setup,
the enable bit, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to
run. If the Active Edge Select bit, which is bit 3 of the appropriate Timer Control Register, is low, the
Timer/EventCounter will increment each time the associated external timer pin receives a low to high transition. If the Active Edge Select bit is high, the
Timer/Event Counter will increment each time the external timer pin receives a high to low transition. When it is
full and overflows, an interrupt signal is generated and
the Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the asso-
Configuring the Timer Mode
In this mode, the Timer/Event Counters can be utilised
to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, the Operating Mode Select bit pair in
the appropriate Timer Control Register must be set to
the correct value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Rev. 1.10
Bit7 Bit6
1
0
21
November 5, 2008
HT46R94
Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when
the external timer pin returns to its original low level. As
before, the enable bit will be automatically reset to zero
and the Timer/Event Counter will stop counting. It is important to note that in the Pulse Width Measurement
Mode, the enable bit is automatically reset to zero when
the external control signal on the external timer pin returns to its original level, whereas in the other two
modes the enable bit can only be reset to zero under
program control.
ciated Timer/Event Counter Interrupt Enable bit in the
Interrupt Control Register, is reset to zero.
As the external timer pins are shared with I/O pins, to
ensure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
the microcontroller is in the Power Down Mode, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input pin. As a result
when the timer overflows it will generate a timer interrupt
and corresponding wake-up source.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
until the enable bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made.
Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counters can be utilised
to measure the width of external pulses applied to the
external timer pins. To operate in this mode, the Operating Mode Select bit pair in the appropriate Timer Control Register must be set to the correct value as shown.
It should be noted that in this mode the Timer/Event
Counters are controlled by logical transitions on the external timer pins and not by the logic level. When the
Timer/Event Counter is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register is reset to zero.
Bit7 Bit6
Control Register Operating Mode
Select Bits for the Pulse Width
Measurement Mode
1
1
In this mode, a choice of internal clocks can be used as
the Timer/Event Counter clock, depending upon which
Timer/Event Counter is being used. However this clock
source is further divided by a prescaler, the value of
which is determined by the Prescaler Rate Select bits,
which are bits 0~2 in the respective Timer Control Register. After the other bits in the appropriate Timer Control Register have been setup, the enable bit, which is bit
4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the
external timer pin.
As the external timer pins are shared with I/O pins, to
ensure that the pins are configured to operate as pulse
width measurement pins, two things have to happen.
The first is to ensure that the Operating Mode Select bits
in the appropriate Timer Control Register place the related Timer/Event Counter in the Pulse Width Measurement Mode. The second is to ensure that the port control
register configures the related timer pin as an input.
If the Active Edge Select bit, which is bit 3 of the Timer
Control Register, is low, once a high to low transition has
been received on the related external timer pin, the
Timer/Event Counter will start counting until the external
timer pin returns to its original high level. At this point the
enable bit will be automatically reset to zero and the
Timer/Event Counter will stop counting. If the Active
Programmable Frequency Divider - PFD
The PFD output is pin-shared with the I/O pin PA7. The
PFD function is selected via configuration option, however, if not selected, the pin can operate as a normal I/O
pin. The timer overflow signal from Timer/Event Counter
1 is the clock source for the PFD circuit. The output fre-
E x te r n a l T im e r
P in In p u t
T 0 O N o r T 1 O N
( w ith T 0 E o r T 1 E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
Rev. 1.10
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November 5, 2008
HT46R94
Programming Considerations
quency is controlled by loading the required values into
the timer registers and programming the prescaler bits
to give the required division ratio. The counter, driven by
one of the internal clocks which is divided by the
prescaler value, will begin to count-up from this preload
register value until full, at which point an overflow signal
is generated, causing the PFD output to change state.
The counter will then be automatically reloaded with the
preload register value and continue counting-up.
When configured to run in the timer mode, one of the internal clocks is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width
measurement mode, one of the internal system clocks is
also used as the timer clock source but the timer will
only run when the correct logic condition appears on the
external timer input pin. As this is an external event and
not synchronised with the internal timer clock, the
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result, there may be
small differences in measured values requiring programmers to take this into account during programming.
The same applies if the timer is configured to be in the
event counting mode, which again is an external event
and not synchronised with the internal system or timer
clock.
For the PFD output to function, it is essential that the
corresponding bit of the Port A control register PAC bit 7
is setup as an output. If setup as an input the PFD output
will not function, however, the pin can still be used as a
normal input pin. The PFD output will only be activated if
bit PA7 is set high. This output data bit is used as the
on/off control bit for the PFD output. Note that the PFD
output will be low if the PA7 output data bit is cleared to
zero.
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very precise values of frequency can be generated.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error,
this should be taken into account by the programmer.
Care must be taken to ensure that the timers are properly initialised before using them for the first time. The
associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt
associated with the timer will remain inactive. The edge
select, timer mode and clock source control bits in timer
control register must also be correctly set to ensure the
timer is properly configured for the required application.
It is also important to ensure that an initial value is first
loaded into the timer registers before the timer is
switched on; this is because after power-on the initial
values of the timer registers are unknown. After the
timer has been initialised the timer can be turned on and
off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the
timer on, should only be executed after the timer mode
bits have been properly setup. Setting the timer enable
bit high together with a mode bit modification, may lead
to improper timer operation if executed as a single timer
control register byte write instruction.
Prescaler
Bits P1SC0~P1SC2 and P0SC0~P0SC2 of the TMR1C
and TMR0C register can be used to define the
pre-scaling stages of the internal clock source for the
Timer/Event Counters. In the Event Counter Mode the
prescaler has no effect.
I/O Interfacing
The Timer/Event Counters, when configured to run in
the Event Counter or Pulse Width Measurement Mode,
require the use of the external PA2/TMR0 or PA3/TMR1
pin for correct operation. As these pins are shared pins
they must be configured correctly to ensure they are
setup for use as Timer/Event Counter inputs and not as
normal I/O pins. This is implemented by ensuring that
the mode select bits in the Timer/Event Counter control
register, select either the Event Counter or Pulse Width
Measurement Mode. Additionally the Port Control Register PAC bit 2 or bit 3 must be set high to ensure that the
pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is
used as a Timer/Event Counter input.
T im e r O v e r flo w
P F D
C lo c k
P A 3 D a ta
P F D
O u tp u t a t P A 3
PFD Output Control
Rev. 1.10
23
November 5, 2008
HT46R94
Timer Program Example
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a
Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
This program example shows how the Timer/Event
Counter 0 registers are setup, along with how the interrupts are enabled and managed. Note how the
Timer/Event Counter 0 is turned on, by setting bit 4 of
the TMR0C as an independent instruction. The Timer/
Event Counter 0 can be turned off in a similar way by
clearing the same bit. This example program sets the
Timer/Event Counter 0 to be in the timer mode, which
uses the internal system clock as the clock source.
org 04h
; external interrupt vector
reti
org 08h
; Timer/Event Counter 0 interrupt vector
jmp tmrint0
; jump here when Timer/Event Counter 0 overflows
:
org 20h
; main program
;internal Timer/Event Counter 0 interrupt routine
tmrint0:
:
; Timer/Event Counter 0 main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,09bh
; setup Timer preload value
mov tmr0,a;
mov a,081h
; setup Timer control register
mov tmr0c,a
; timer mode and prescaler set to /4
; setup interrupt register
mov a,005h
; enable Master and Timer/Event Counter 0 interrupt
mov intc0,a
set tmr0c.4
; start Timer/Event Counter 0 - note mode bits must be previously setup
Pulse Width Modulator
All devices contain three Pulse Width Modulation,
PWM, outputs, known as PWM0, PWM1 and PWM2.
Useful for such applications such as motor speed control, the PWM function provides an output with a fixed
frequency but with a duty cycle tht can be varied by setting particular values into the corresponding PWM
registers.
Channels
PWM
Mode
Output
Pins
Register
Name
3
6+2 or
7+1
PA4
PA5
PA6
PWM0
PWM1
PWM2
Rev. 1.10
PWM Overview
The PWM outputs are selected via configuration options. Three registers, located in the RAM Data Memory
are assigned to the Pulse Width Modulator and are
known as PWM0, PWM1 and PWM2. It is in these register that the 8-bit value, which represents the overall duty
cycle of one modulation cycle of the output waveform,
should be placed. To increase the PWM modulation frequency, each modulation cycle is modulated into two or
four individual modulation sub-sections, known as the
7+1 mode or the 6+2 mode respectively. The device can
choose which mode to use by selecting the appropriate
configuration option. Note that it is only necessary to
24
November 5, 2008
HT46R94
DC value. The second group which consists of bit0~bit1
is known as the AC value. In the 6+2 PWM mode, the
duty cycle value of each of the four modulation
sub-cycles is shown in the following table.
write the required modulation value into the corresponding PWM0, PWM1 or PWM2 register as the subdivision
of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. The PWM clock source is the system clock fSYS.
Parameter
This method of dividing the original modulation cycle into
a further 2 or 4 sub-cycles enables the generation of
higher PWM frequencies, which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the
system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256. However,
when in the 7+1 mode of operation, the PWM modulation
frequency will be fSYS/128, while the PWM modulation
frequency for the 6+2 mode of operation will be fSYS/64.
Modulation cycle i
(i=0~3)
i³AC
The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into
4 individual modulation cycles, numbered from 0~3 and
how the AC value is related to the PWM value.
7+1 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM
register, has 256 clock periods. However, in the 7+1
PWM mode, each PWM cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as ²i² in the table. Each one of these
two sub-cycles contains 128 clock cycles. In this mode, a
modulation frequency increase of two is achieved. The
8-bit PWM register value, which represents the overall
duty cycle of the PWM waveform, is divided into two
groups. The first group which consists of bit1~bit7 is denoted here as the DC value. The second group which
consists of bit0 is known as the AC value. In the 7+1
PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table.
Each full PWM cycle, as it is controlled by an 8-bit PWM,
PWM0 or PWM1 register, has 256 clock periods. However, in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as
modulation cycle 0~modulation cycle 3, denoted as ²i²
in the table. Each one of these four sub-cycles contains
64 clock cycles. In this mode, a modulation frequency
increase by a factor of four is achieved. The 8-bit PWM
register value, which represents the overall duty cycle of
the PWM waveform, is divided into two groups. The first
group which consists of bit2~bit7 is denoted here as the
Y S
i<AC
DC
(Duty Cycle)
DC+1
64
DC
64
6+2 Mode Modulation Cycle Values
6+2 PWM Mode
fS
AC (0~3)
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
6+2 PWM Mode
b 7
b 0
P W M 0 , P W M 1 R e g is te r
A C
v a lu e
D C v a lu e
6+2 Pulse Width Modulation Mode Registers
Rev. 1.10
25
November 5, 2008
HT46R94
Parameter
i<AC
Modulation cycle i
(i=0~1)
be selected. A ²0² must also be written to the corresponding bit in the I/O port control register, PAC.4,
PAC.5 or PAC.6, to ensure that the corresponding
PWM0, PWM1 or PWM2 output pin is setup as an output. After these two initial steps have been carried out,
and of course after the required PWM value has been
written into the PWM0, PWM1 or PWM2 register, writing a ²1² to the corresponding PA.4, PA.5 or PA.6 bit in
the PA output data register will enable the PWM data to
appear on the pin. Writing a ²0² to the bit will disable the
PWM output function and force the output low. In this
way, the Port A data output register bits, PA.4, PA.5 and
PA.6, can be used as an on/off control for the PWM
function. Note that if the configuration options have selected the PWM function, but a ²1² has been written to
its corresponding bit in the PAC control register to configure the pin as an input, then the pin can still function
as a normal input line, with pull-high resistor options.
DC
(Duty Cycle)
DC+1
128
DC
128
AC (0~1)
i³AC
7+1 Mode Modulation Cycle Values
The following diagram illustrates the waveforms associated with the 7+1 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into
2 individual modulation cycles, numbered 0 and 1 and
how the AC value is related to the PWM value.
PWM Output Control
PWM
Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fSYS/64
fSYS/256
(PWM register
value)/256
PWM Programming Example
The following sample program shows how the PWM
outputs are setup and controlled. Before use the corresponding PWM output configuration options must first
be selected.
The PWM0 output is shared with pin PA4, the PWM1
output is shared with PA5 and the PWM2 output is
shared with PA6. To operate as a PWM output and not
as I/O pins, the correct PWM configuration option must
mov
mov
clr
set
:
:
clr
a,64h
pwm0,a
pac.4
pa.4
:
:
pa.4
fS
Y S
; setup PWM0 value of 100 decimal which is 64H
; setup pin PA4 as an output
; pa.4=1; enable the PWM output
; disable the PWM output - PA4 will remain low
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
7+1 PWM Mode
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
7+1 Pulse Width Modulation Mode Register
Rev. 1.10
26
November 5, 2008
HT46R94
Analog to Digital Converter
The need to interface to real world analog signals is a
common requirement for many electronic systems.
However, to properly process these signals by a
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the
need for external components is reduced significantly
with the corresponding follow-on benefits of lower costs
and reduced component space requirements.
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11 D10 D9
D8
D7
D6
D5
D4
A/D Data Registers
A/D Converter Control Register - ADCR
To control the function and operation of the A/D converter, a control register known as ADCR is provided.
This 8-bit register defines functions such as the selection of which analog channel is connected to the internal
A/D converter, which pins are used as analog inputs and
which are used as normal I/Os as well as controlling the
start function and monitoring the A/D converter end of
conversion status.
A/D Overview
The device contains a 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals
and convert these signals directly into a 12-bit digital
value.
Input Channels Conversion Bits
Register
Input Pins
A/D Converter Data Registers - ADRL, ADRH
One section of this register contains the bits
ACS2~ACS0 which define the channel number. As each
of the devices contains only one actual analog to digital
converter circuit, each of the individual 8 analog inputs
must be routed to the converter. It is the function of the
ACS2~ACS0 bits in the ADCR register to determine
which analog channel is actually connected to the internal A/D converter.
As the device contains a 12-bit A/D converter, it requires
two data registers to store its conversion value, a high
byte register, known as ADRH, and a low byte register,
known as ADRL. After the conversion process takes
place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value.
Only the high byte register, ADRH, utilises its full 8-bit
contents. The low byte register utilises only 4 bits of its
8-bit contents as it contains only the lowest bit of the
12-bit converted value.
The ADCR control register also contains the
PCR2~PCR0 bits which determine which pins on Port B
are used as analog inputs for the A/D converter and
which pins are to be used as normal I/O pins. If the 3-bit
address on PCR2~PCR0 has a value of ²111², then all
eight pins, namely AN0~AN7 will all be set as analog inputs. Note that if the PCR2~PCR0 bits are all set to zero,
then all the Port B pins will be setup as normal I/Os and
the internal A/D converter circuitry will be powered off to
reduce the power consumption.
8
12
PB0~PB7
The accompanying diagram shows the overall internal
structure of the A/D converter, together with its associated registers.
In the following tables, D0~D11 are the A/D conversion
data result bits.
C lo c k D iv id e
R a tio
A D C
fS
S o u rc e
Y S
A C S R
¸ N
V
P B 0 /A N 0
P B 1 /A N 1
R E F
A /D
r e fe r e n c e v o lta g e
A D R L
A D C
A D R H
P B 7 /A N 7
P C R 0 ~ P C R 2
P in C o n fig u r a tio n
B its
A D C S 0 ~ A D C S 2
C h a n n e l S e le c t
B its
S T A R T
R e g is te r
E O C B
A /D D a ta
R e g is te r s
A D C R
R e g is te r
S ta r t B it E n d o f
C o n v e r s io n B it
A/D Converter Structure
Rev. 1.10
27
November 5, 2008
HT46R94
b 7
S T A R T E O C B
P C R 2
P C R 1
P C R 0
A C S 2
A C S 1
b 0
A C S 0
A D C R
R e g is te r
S e le c t A /D
A
A C S 2
0
0
0
0
1
1
1
1
c h a n n
C S 1 A
0
0
1
1
0
0
1
1
e l
C S 0
0
1
0
1
0
1
0
1
P o rt B A /D
P
P C R 2
0
0
0
0
1
1
1
1
c h a n n e l c o n fig u r a tio n
C R 1 P C R 0
P o rt B A
0
0
P B 0 e n a
1
0
P B 0 ~ P B
0
1
1
1
P B 0 ~ P B
0
0
P B 0 ~ P B
1
0
P B 0 ~ P B
0
1
P B 0 ~ P B
1
1
P B 0 ~ P B
A N
A N
A N
A N
A N
A N
A N
A N
7
6
5
4
3
2
1
0
s
/D
b
1
2
3
4
5
7
c h a n n
le d a s A
e n a b le
e n a b le
e n a b le
e n a b le
e n a b le
e n a b le
e ls
N 0
d a
d a
d a
d a
d a
d a
- a ll o ff
s A
s A
s A
s A
s A
s A
N 0
N 0
N 0
N 0
N 0
N 0
~ A
~ A
~ A
~ A
~ A
~ A
N 1
N 2
N 3
N 4
N 5
N 7
E n d o f A /D c o n v e r s io n fla g
1 : n o t e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n w a itin g o r in p r o g r e s s
0 : e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n e n d e d
S ta r t th e A /D c o n v e r s io n
0 ® 1 ® 0 : S ta rt
0 ® 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
A/D Converter Control Register
provided. One means of turning off the A/D converter
circuitry is to ensure that the PCR0~PCR2 bits in the
ADCR register are cleared to zero. Another method is to
use the ADONB bit in the ACSR register, which if set
high will also turn off the A/D internal circuitry. Both
power off methods are independent and have overriding
control over the other.
The START bit in the ADCR register is used to start and
reset the A/D converter. When the microcontroller sets
this bit from low to high and then low again, an analog to
digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR register will be set to a ²1²
and the analog to digital converter will be reset. It is the
START bit that is used to control the overall on/off operation of the internal analog to digital converter.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is complete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detecting the end of an A/D conversion cycle.
ADONB Bit
A/D Circuits
0
X
Off
>0
0
On
>0
1
Off
A/D Power Control
It should be noted that the power supply to the A/D converter is supplied via the VDD pin. However the lowest
operating voltage of the analog circuitry is higher than
that of the digital circuitry and therefore the analog circuits will fail to operate at the lower end of the VDD
specification. The DC Characteristics therefore specify
a separate operating voltage specification for the analog
circuitry.
A/D Converter Clock Source Register - ACSR
A/D Converter Power Control
The clock source for the A/D converter, which originates
from the system clock fSYS, is first divided by a division
ratio, the value of which is determined by the ADCS1
and ADCS0 bits in the ACSR register.
As an integrated circuit function within the device, the
A/D converter will naturally consume a limited amount of
power. However to provide users with a means of on/off
control to reduce power consumption, two methods are
Rev. 1.10
PCR Bits
28
November 5, 2008
HT46R94
b 7
T E S T
b 0
A D C S 2 A D C S 1 A D C S 0
A D O N B
A C S R
R e g is te r
S e le c t A /D c o n v e r te r c lo c k s o u r
A D C S 2 A D C S 1 A D C S 0
: s y
0
0
0
: s y
1
0
0
: s y
0
0
1
: u n
1
0
1
: s y
0
1
0
: s y
1
1
0
0
1
1
: s y
1
1
1
: u n
c e
s te
s te
s te
d e
s te
s te
s te
d e
m
m
m
fin
m
m
m
fin
c lo
c lo
c lo
e d
c lo
c lo
c lo
e d
c k /2
c k /8
c k /3 2
c k
c k /4
c k /1 6
N o t im p le m e n te d , r e a d a s " 0 "
A /D O n /O ff c o n tro l
1 : o ff
0 : o n
F o r te s t m o d e u s e o n ly
A/D Converter Clock Source Register
A/D Clock Period (tAD)
fSYS
ADCS2, ADCS1,
ADCS0=000
(fSYS/2)
ADCS2, ADCS1,
ADCS0=001
(fSYS/8)
ADCS2, ADCS1,
ADCS0=010
(fSYS/32)
ADCS2, ADCS1,
ADCS0=011
1MHz
2ms
8ms
32ms
Undefined
2MHz
1ms
4ms
16ms
Undefined
4MHz
500ns*
2ms
8ms
Undefined
8MHz
250ns*
1ms
4ms
Undefined
A/D Clock Period Examples
the pull-high resistors will be automatically disconnected.
Note that it is not necessary to first setup the A/D pin as
an input in the PBC port control register to enable the A/D
input as when the PCR2~PCR0 bits enable an A/D input,
the status of the port control register will be overridden.
The A/D reference voltage is supplied on an individual
VREF pin and can be connected to an external reference
voltage source. Appropriate measures should be taken to
ensure that the VREF voltage does not exceed the VDD
voltage level and that it remains as stable and noise free
as possible.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS1 and ADCS0, there are
some limitations on the maximum A/D clock source speed
that can be selected. As the minimum value of permissible
A/D clock period, tAD, is 0.5ms, care must be taken for system clock speeds in excess of 4MHz. For system clock
speeds in excess of 4MHz, the ADCS1 and ADCS0 bits
should not be set to ²00². Doing so will give A/D clock periods that are less than the minimum A/D clock period which
may result in inaccurate A/D conversion values. Refer to
the accompanying table for examples, where values
marked with an asterisk * show where, depending upon
the device, special care must be taken, as the values may
be less than the specified minimum A/D Clock Period.
Initialising the A/D Converter
The internal A/D converter must be in a special way.
Each time the Port B A/D channel selection bits are modified by the program, the A/D converter must be
re-initialised. If the A/D converter is not initialised after the
channel selection bits are changed, the EOCB flag may
have an undefined value, which may produce a false end
of conversion signal. To initialise the A/D converter after
the channel selection bits have changed, then, within a
time frame of one to ten instruction cycles, the START bit
in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB
flag is correctly set to a high condition.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the
I/O pins on Port B. Bits PCR2~PCR0 in the ADCR register, not configuration options, determine whether the input pins are setup as normal Port B input/output pins or
whether they are setup as analog inputs. In this way, pins
can be changed under program control to change their
function from normal I/O operation to analog inputs and
vice versa. Pull-high resistors, which are setup through
configuration options, apply to the input pins only when
they are used as normal I/O pins, if setup as A/D inputs
Rev. 1.10
29
November 5, 2008
HT46R94
P C R 2 ~
P C R 0
0 0 0 B
1 0 1 B
1 0 0 B
0 0 0 B
A D O N B
tO
A D C
m o d u le O N
N 2 S T
o ff
o n
A /D s a m p lin g tim e
tA D C S
S T A R T
o n
o ff
A /D s a m p lin g tim e
tA D C S
E O C B
A C S 2 ~
A C S 0
x x x B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e p o r t c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
tA D C
A /D c o n v e r s io n tim e
N o te :
x x x B
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
tA D C
A /D c o n v e r s io n tim e
A /D c lo c k m u s t b e fs y s , fS Y S /2 , fs y s /4 , fs y s /8 , fS Y S /1 6 o r fS
tA D C S = 4 tA D
tA D C = tA D C S + n * tA D ; n = b it c o u n t o f A D C r e s o lu tio n
Y S
/3 2
A/D Conversion Timing
can be polled. The conversion process is complete
when this bit goes low. When this occurs the A/D data
registers ADRL and ADRH can be read to obtain the
conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur.
Summary of A/D Conversion Steps
The following summarises the individual steps that
should be executed in order to implement an A/D conversion process.
· Step 1
Select the required A/D conversion clock by correctly
programming bits ADCS1 and ADCS0 in the ACSR
register.
Note:
· Step 2
Enable the A/D by clearing the ADONB bit in the
ACSR register.
The accompanying timing diagram shows graphically
the various stages involved in an analog to digital conversion process and its associated timing.
· Step 3
Select which channel is to be connected to the internal
A/D converter by correctly programming the
ACS2~ACS0 bits which are also contained in the
ADCR register.
The setting up and operation of the A/D converter function is fully under the control of the application program as
there are no configuration options associated with the
A/D converter. After an A/D conversion process has been
initiated by the application program, the microcontroller
internal hardware will begin to carry out the conversion,
during which time the program can continue with other
functions. The time taken for the A/D conversion is 16tAD
where tAD is equal to the A/D clock period.
· Step 4
Select which pins on Port B are to be used as A/D inputs and configure them as A/D input pins by correctly
programming the PCR0~PCR2 bits in the ADCR register. Note that this step can be combined with Step 2
into a single ADCR register programming operation.
· Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D
converter interrupt function is active. The master interrupt control bit, EMI, in the INTC interrupt control register must be set to ²1² and the A/D converter interrupt
bit, EADI, in the INTC register must also be set to ²1².
Programming Considerations
When programming, special attention must be given to
the A/D channel selection bits in the ADCR register. If
these bits are all cleared to zero no external pins will be
selected for use as A/D input pins allowing the pins to be
used as normal I/O pins. When this happens the power
supplied to the internal A/D circuitry will be turned off resulting in a reduction of supply current. This ability to reduce power by turning off the internal A/D function by
clearing the A/D channel selection bits may be an important consideration in battery powered applications. The
A/D can also be turned off by using the ADONB bit int he
ACSR register.
· Step 6
The analog to digital conversion process can now be
initialised by setting the START bit in the ADCR register from ²0² to ²1² and then to ²0² again. Note that this
bit should have been originally set to ²0².
· Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register
Rev. 1.10
When checking for the end of the conversion
process, if the method of polling the EOCB bit in
the ADCR register is used, the interrupt enable
step above can be omitted.
30
November 5, 2008
HT46R94
Another important programming consideration is that when the A/D channel selection bits change value, the A/D converter must be . This is achieved by pulsing the START bit in the ADCR register immediately after the channel selection
bits have changed state. The exception to this is where the channel selection bits are all cleared, in which case the A/D
converter is not required to be re-initialised.
A/D Programming Example
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as
; the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3
; as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D
; converter
:
:
; As the Port B channel bits have changed the
; following START
; signal (0-1-0) must be issued within 10
; instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end
; of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRL
; read low byte conversion result value
mov
adrl_buffer,a
; save result to user defined register
mov
a,ADRH
; read high byte conversion result value
mov
adrh_buffer,a
; save result to user defined register
:
jmp
start_conversion
; start next A/D conversion
Example: using the interrupt method to detect the end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as
; the A/D clock
mov
a,00100000B
mov
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3
; as A/D inputs
; and select AN0 to be connected to the A/D
; As the Port B channel bits have changed the
; following START signal(0-1-0) must be issued
; within 10 instruction cycles
:
Start_conversion:
clr
set
clr
clr
set
set
Rev. 1.10
START
START
START
ADF
EADI
EMI
:
:
:
;
;
;
;
;
reset A/D
start A/D
clear ADC interrupt request flag
enable ADC interrupt
enable global interrupt
31
November 5, 2008
HT46R94
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRL
mov
adrl_buffer,a
mov
a,ADRH
mov
adrh_buffer,a
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
; save ACC to user defined memory
; save STATUS to user defined memory
;
;
;
;
read
save
read
save
low byte conversion result value
result to user defined register
high byte conversion result value
result to user defined register
; restore STATUS from user defined memory
; restore ACC from user defined memory
A/D Transfer Function
Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except for the
digitised zero value, the subsequent digitised values will
change at a point 0.5 LSB below where they would
change without the offset, and the last full scale digitised
value will change at a point 1.5 LSB below the VDD level.
As the device contain a 12-bit A/D converter, its
full-scale converted digitised value is equal to FFFH.
Since the full-scale analog input value is equal to the
VDD voltage, this gives a single bit analog input value of
VDD/4096. The diagram show the ideal transfer function
between the analog input value and the digitised output
value for the A/D converter.
1 .5 L S B
F F F H
F F E H
F F D H
A /D C o n v e r s io n
R e s u lt
0 .5 L S B
0 3 H
0 2 H
0 1 H
0
1
2
3
4 0 9 3 4 0 9 4
4 0 9 5 4 0 9 6
(
V R E F
)
4 0 9 6
A n a lo g In p u t V o lta g e
Ideal A/D Transfer Function
Rev. 1.10
32
November 5, 2008
HT46R94
Operation Mode
The device can operate in three different modes which
are known as Normal, Slow and Power Down. To support these different modes two system clocks are required, an RC or Crystal external system oscillator
connected to the OSC1 and OSC2 pins and and a
32768 external Crystal oscillator connected to the
OSC3 and OSC4 pins. Both system clocks must be connected for correct operation.
will naturally cause the microcontroller to consume less
power; this is known as the Slow Mode. In this mode the
RC or Crystal oscillator will be turned off. Selecting the
higher frequency RC or Crystal oscillator by setting the
MODS bit to zero will place the microcontroller in the
Normal Mode. The other mode, known as the
Power-down Mode can only be entered when a HALT
instruction is executed. Note that in all modes the
32768Hz oscillator continues to run.
Mode Selection
If the 32768Hz oscillator is chosen as the system clock,
then the WDT clock source configuration option must
also select the 32768Hz oscillator as its clock source,
otherwise unpredictable system operation may occur.
The choice of which system clock is used is made using
the MODS bit in the MODE register and can be either an
RC/XTAL oscillator or a 32768Hz RTC. Selecting the
slower 32768Hz oscillator by setting the MODS bit high
Mode
System Clock
HALT Instruction
MODS
RC/XTAL Oscillator
32768Hz
Normal
RC/XTAL oscillator
Not Executed
0
On
On
Slow
32768Hz
Not Executed
1
Off
On
Power Down
HALT
Executed
x
Off
On
Operation Mode
b 7
b 0
M O D S
Q O S C
M O D E R e g is te r
S y s te m C lo c k S e le c t
1 : 3 2 7 6 8 H z s y s te m c lo c k
0 : R C /C r y s ta l s y s te m c lo c k
N o t im p le m e n te d , r e a d a s " 0 "
3 2 7 6 8 H z O s c illa to r Q u ic k S ta r t
1 : s lo w s ta r t
0 : q u ic k s ta r t
N o t im p le m e n te d , r e a d a s " 0 "
Operation Mode Register ¾ MODE
Rev. 1.10
33
November 5, 2008
HT46R94
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter, Time Base or A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension
of the main program allowing the microcontroller to direct attention to their respective needs. Each device in
this series contains a single external interrupt and several internal interrupts functions. The external interrupt
is controlled by the action of the external INT pin, while
the internal interrupts are controlled by the Timer/Event
Counter overflow, Time Base overflow interrupt and the
A/D converter interrupt.
b 7
Interrupt Registers
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the INTC0 and
INTC1 registers, which are located in the Data Memory.
By controlling the appropriate enable bits in this register
each individual interrupt can be enabled or disabled.
Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global
enable flag if cleared to zero will disable all interrupts.
b 0
T 1 F
T 0 F
E IF
E T 1 I
E T 0 I
E E I
E M I
IN T C 0 R e g is te
M a s te r in te r r u p t g lo b a l e n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 0 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
F o r te s t m o d e u s e d o n ly
M u s t b e w r itte n a s " 0 " ; o th e r w is e m a y r e s u lt in u n p r e d ic ta b le o p e r a tio n
Interrupt Control 0 Registers
b 7
b 0
A D F
T B F
E A D I E T B I
IN T C 1 R e g is te r
T im e B a s e in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
A /D C o n v e r te r in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
T im e B a s e in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
A /D c o n v e r te r in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Control 1 Registers
Rev. 1.10
34
November 5, 2008
HT46R94
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
T im e B a s e
In te r r u p t R e q u e s t F la g T B F
E T B I
A /D C o n v e rte r
In te r r u p t R e q u e s t F la g A D F
E A D I
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure
Interrupt Operation
Interrupt Priority
A Timer/Event Counter overflow, a Time Base overflow,
an end of A/D conversion or the external interrupt line
being pulled low will all generate an interrupt request by
setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the
Program Counter, which stores the address of the next
instruction to be executed, will be transferred onto the
stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its
next instruction from this interrupt vector. The instruction
at this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Interrupt Source
Priority
04H
1
Timer/Event Counter 0 Overflow
08H
2
Timer/Event Counter 1 Overflow
0CH
3
Time Base Overflow
10H
4
A/D Converter Conversion End
14H
5
Interrupt Priority
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the INTC0 and
INTC1 registers can prevent simultaneous occurrences.
The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI, must
first be set. An actual external interrupt will take place
when the external interrupt request flag, EIF in INTC0. As
the external interrupt is a dual edge triggered type, the
EIF flag will be set when either a high to low or low to high
transition appears on the INT line. The external interrupt
pin is pin-shared with the output pin PD0 and can only be
configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has
been set and the PD0 output is disabled by setting the
LCDEN bit in the LCDC register to zero and the PD0 bit
set high. If the external interrupt enable bit is not set then
the pin can be used as a PD0 CMOS output pin. When
the interrupt is enabled, the stack is not full and a high to
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Rev. 1.10
Vector
External Interrupt
35
November 5, 2008
HT46R94
A/D Interrupt
low transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location
04H, will take place. When the interrupt is serviced, the
external interrupt request flag, EIF; bit 4 of INTC0 will be
automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
For an A/D interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding interrupt enable bit,
EADI, must be first set. An actual A/D interrupt will take
place when the A/D converter request flag, ADF in the
INTC1 register is set, a situation that will occur when an
A/D conversion process has completed. When the interrupt is enabled, the stack is not full and an A/D conversion process finishes execution, a subroutine call to the
A/D interrupt vector at location 14H, will take place.
When the interrupt is serviced, the A/D interrupt request
flag, ADF, will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI , and the corresponding timer
interrupt enable bit, ET0I and ET1I in the INTC0 register
must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter interrupt request flag, T0F or T1F in INTC0, is set, a situation
that will occur when the relevant Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter overflow occurs, a
subroutine call to the timer interrupt vector at location
08H will take place for Timer/Event Counter 0 and a subroutine call to 0CH will take place for Timer/Event Counter 1. When the interrupt is serviced, the timer interrupt
request flag, T0F or T1F, will be automatically reset and
the EMI bit will be automatically cleared to disable other
interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC0 or INTC1 register until the corresponding interrupt is serviced or until the request flag is
cleared by a software instruction.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
Time Base Interrupt
For a Time Base interrupt to occur, the global interrupt
enable bit, EMI, in the INTC0 register, and the Time
Base interrupt enable bit, ETBI, in the INTC1 register
must first be set. An actual Time Base interrupt will take
place when the Time Base request flag, TBF in INTC1 is
set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full,
and a Time Base overflow occurs, a subroutine call to
the Time Base vector location at 10H will take place.
When the interrupt is serviced, the Time Base interrupt
request flag, TBF, will be automatically reset and the
EMI bit will be automatically cleared to disable other interrupts.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Only the Program Counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which may corrupt the
desired control sequence, then the contents should be
saved in advance.
T B 0 ~ T B 2
fS
Y S
/4
W D T O s c illa to r
R T C
O s c illa to r
C lo c k S o u r c e
C o n fig u r a tio n
O p tio n
fS
¸
1 6
8 - S ta g e P r e s c a le r
(1 /2 ~ 1 /2 5 6 )
T im e B a s e In te r r u p t
(fS /3 2 ~ fS /4 0 9 6 )
T im e B a s e C lo c k S o u r c e S e le c t
Time Base Interrupt
Rev. 1.10
36
November 5, 2008
HT46R94
Reset and Initialisation
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
0 .9 V
R E S
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the is running. One example of this is where after
power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In
such a case, known as a normal operation reset, some
of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high.
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset
operations result in different register conditions being
setup.
V D D
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
0 .0 1 m F
V D D
1 0 0 k W
R E S
Reset Functions
1 0 k W
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
0 .1 m F
· Power-on Reset
Enhanced Reset Circuit
V S S
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
Rev. 1.10
D D
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
D D
D D
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
RES Reset Timing Chart
37
November 5, 2008
HT46R94
· Low Voltage Reset - LVR
Reset Initial Conditions
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be selected via configuration options.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
TO PDF
L V R
tR
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
S T D
S S T T im e - o u t
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
In te rn a l R e s e t
Low Voltage Reset Timing Chart
Item
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will
be cleared
Input/Output Ports I/O ports will be setup as inputs
Stack Pointer
· Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
Stack Pointer will point to the top
of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure
reliable continuation of normal program execution after
a reset occurs, it is important to know what condition the
microcontroller is in after a particular reset occurs. The
accompanying table describes how each type of reset
affects each of the microcontroller internal registers.
W D T T im e - o u t
tS
Condition After RESET
S T
S S T T im e - o u t
WDT Time-out Reset during Power Down
Timing Chart
Rev. 1.10
38
November 5, 2008
HT46R94
Reset (Power-on)
RES or LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1000
0000 1000
0000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
0000 0000
0000 0000
0000 0000
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM2
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
INTC1
--00 --00
--00 --00
--00 --00
--uu --uu
LCDC
--00 0000
--00 0000
--00 0000
--uu uuuu
MODE
---0 ---0
---0 ---0
---0 ---0
---u ---u
ADRL
xxxx ----
xxxx ----
xxxx ----
uuuu ----
Register
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
10--
10--
10--
1u-- -uuu
-000
-000
-000
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.10
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November 5, 2008
HT46R94
Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application requirements. Three types of system clocks can be selected
while various clock source options for the Watchdog
Timer are provided for maximum flexibility.
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
CL
12MHz
TBD
TBD
TBD
The Three methods of generating the system clock are:
8MHz
TBD
TBD
TBD
· External crystal/resonator oscillator
4MHz
TBD
TBD
TBD
· External RC oscillator
1MHz
TBD
TBD
TBD
· External 32768Hz oscillator
Note:
The choice of External crystal/resonator or RC system
oscillator is made via a configuration option while the selection of the 32768Hz oscillator is made using the
MODS bit in the MODE register. The 32768Hz Oscillator
must always be connected along with a choice of either
RC or crystal/resonator for correct operation.
1. C1 and C2 values are for guidance only.
2. CL is the crystal manufacturer specified
load capacitor value.
Crystal Recommended Capacitor Values
Resonator C1 and C2 Values
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
Resonator Frequency
C1
C2
3.58MHz
TBD
TBD
External Crystal/Resonator Oscillator
1MHz
TBD
TBD
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
resonator types, to ensure oscillation and accurate fre-
455kHz
TBD
TBD
C 1
O S C 1
R f
R p
C a
C b
C 2
O S C 2
Note:
C1 and C2 values are for guidance only.
Resonator Recommended Capacitor Values
External RC Oscillator
Using the external system RC oscillator requires that a
resistor, with a value between 24kW and 1MW, is connected between OSC1 and VDD, and a capacitor is connected to ground. Although this is a cost effective
oscillator configuration, the oscillation frequency can
vary with VDD, temperature and process variations and
is therefore not suitable for applications where timing is
critical or where accurate oscillator frequencies are required. For the value of the external resistor ROSC refer
to the Holtek website for typical RC Oscillator vs. Temperature and VDD characteristics graphics Here only
the OSC1 pin is used, which is shared with I/O pin PA6,
leaving pin PA5 free for use as a normal I/O pin. Note
that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown
on the diagram does not influence the frequency of oscillation.
In te r n a l
O s c illa to r
C ir c u it
T o in te r n a l
c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
External Crystal/Ceramic Oscillator
quency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
V
D D
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Ca
Cb
Rf
11pF~13pF
13pF~15pF
470kW
4 7 0 p F
O S C 1
R
O S C
Oscillator Internal Component Values
fS
Y S
/4 N M O S O p e n D r a in
O S C 2
External RC Oscillator
Rev. 1.10
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November 5, 2008
HT46R94
External RTC Oscillator
RTC Oscillator C1 and C2 Values
When the microcontroller enters the Power Down Mode,
the system clock is switched off to stop microcontroller
activity and to conserve power. However, in many
microcontroller applications it may be necessary to keep
some internal functions such as timers operational even
when the microcontroller is in the Power Down Mode. To
do this, a 32768Hz oscillator, also known as the Real
Time Clock or RTC oscillator, is provided. To implement
C 1
3 2 7 6 8 H z
32768Hz
Note:
R p
R f
O S C 4
C1
C2
CL
TBD
TBD
TBD
1. C1 and C2 values are for guidance only.
2. CL is the crystal manufacturer specified
load capacitor value.
32768 Hz Crystal Recommended Capacitor Values
When the system enters the Power Down Mode, the
32768Hz oscillator will keep running and if it is selected
as the Timer and Watchdog Timer source clock, will also
keep these functions operational.
O S C 3
C a
C b
C 2
Crystal Frequency
During power up there is a time delay associated with
the RTC oscillator, waiting for it to start up. The QOSC
bit in the MODE register, is provided to give a quick
start-up function and can be used to minimise this delay.
During a power up condition, this bit will be cleared to 0
which will initiate the RTC oscillator quick start-up function. However, as there is additional power consumption
associated with this quick start-up function, to reduce
power consumption after start up takes place, it is recommended that the application program should set the
QOSC bit high about 2 seconds after power on. It should
be noted that, no matter what condition the QOSC bit is
set to, the RTC oscillator will always function normally,
only there is more power consumption associated with
the quick start-up function.
T o in te r n a l
c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 3 /O S C 4 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Internal RC Oscillator + External RTC Oscillator
this clock, the OSC3 and OSC4 pins should be connected to a 32768Hz crystal. However, for some crystals, to ensure oscillation and accurate frequency
generation, it may be necessary to add two small value
external capacitors, C1 and C2. The exact values of C1
and C2 should be selected in consultation with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not
required but in some cases may be needed to assist
with oscillation start up. The MODS bit in the MODE register is used to select whether the external 32768Hz oscillator or the External Crystal/External RC is used as
the system oscillator. Using the slower 32768Hz oscillator as the system oscillator will of course use less power
and is known as the Slow Mode.
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 65ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Ca
Cb
Rf
TBD
TBD
TBD
RTC Oscillator Internal Component Values
Rev. 1.10
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November 5, 2008
HT46R94
Power Down Mode and Wake-up
Power Down Mode
Wake-up
All of the microcontrollers have the ability to enter a
Power Down Mode. When the device enters this mode,
the normal operating current, will be reduced to an extremely low standby current level. This occurs because
when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the
device maintains its present internal condition, it can be
woken up at a later stage and continue running, without
requiring a full reset. This feature is extremely important
in application areas where the MCU must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on Port A
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin
· The Data Memory contents and registers will maintain
their present condition.
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
internal oscillator. The WDT will stop if its clock source
originates from the system clock.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased current consumption. Care must also be taken with the
loads, which are connected to I/O pins, which are setup
as outputs. These should be placed in a condition in
which minimum current is drawn or connected only to
external circuits that do not draw current, such as other
CMOS inputs. Also note that additional standby current
will also be required if the configuration options have enabled the Watchdog Timer internal oscillator.
Rev. 1.10
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
42
November 5, 2008
HT46R94
Watchdog Timer
of this instruction will have no effect, only the execution of
a ²CLR WDT2² instruction will clear the WDT. Similarly
after the ²CLR WDT2² instruction has been executed,
only a successive ²CLR WDT1² instruction can clear the
Watchdog Timer.
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such
as electrical noise. It operates by providing a device reset
when the WDT counter overflows. The WDT clock is supplied by one of three sources selected by configuration
option: its own self contained dedicated internal WDT oscillator, fSYS/4 or the RTC oscillator. Note that if the WDT
configuration option has been disabled, then any instruction relating to its operation will result in no operation.
Buzzer
Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides a means of
producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external
circuits that require a precise frequency generator. The
BZ and BZ pins form a complimentary pair, and are
pin-shared with I/O pins, PA0 and PA1. A configuration
option is used to select from one of three buzzer options.
The first option is for both pins PA0 and PA1 to be used
as normal I/Os, the second option is for both pins to be
configured as BZ and BZ buzzer pins, the third option
selects only the PA0 pin to be used as a BZ buzzer pin
with the PA1 pin retaining its normal I/O pin function.
Note that the BZ pin is the inverse of the BZ pin which together generate a differential output which can supply
more power to connected interfaces such as buzzers.
In the device, all Watchdog Timer options, such as enable/disable, WDT clock source and clear instruction
type all selected through configuration options. There
are no internal registers associated with the WDT in the
Cost-Effective A/D Type MCU series. One of the WDT
clock sources is an internal oscillator which has an approximate period of 65ms at a supply voltage of 5V. However, it should be noted that this specified internal clock
period can vary with VDD, temperature and process
variations. Watchdog Timer time-out value is of 214/fS to
221/fS.
If the fSYS/4 clock is used as the WDT clock source, it
should be noted that when the system enters the Power
Down Mode, then the instruction clock is stopped and
the WDT will lose its protecting purposes. For systems
that operate in noisy environments, using the internal
WDT oscillator is strongly recommended.
The buzzer is driven by the internal clock source, fS,
whch is then passed through a divider, the division ratio
of which is selected by configuration options to provide a
range of buzzer frequencies from fS/2 to fS/24. The clock
source that generates fS, which in turn controls the
buzzer frequency, can originate from three different
sources, the RTC oscillator, the WDT oscillator or the
System oscillator/4, the choice of which is determined
by the fS clock source configuration option. It is important to note that if the RTC oscillator is selected as the
system clock, then fS and correspondingly the buzzer,
will also have the RTC oscillator as its clock source.
Note that the buzzer frequency is controlled by configuration options, which select both the source clock for the
internal clock fS and the internal division ratio. There are
no internal registers associated with the buzzer frequency.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instructions and the third is via a ²HALT² instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use the
two commands ²CLR WDT1² and ²CLR WDT2². For the
first option, a simple execution of ²CLR WDT² will clear
the WDT while for the second option, both ²CLR WDT1²
and ²CLR WDT2² must both be executed to successfully
clear the WDT. Note that for this second option, if ²CLR
WDT1² is used to clear the WDT, successive executions
fS
R T C
Y S
/4
O S C
O p tio n
S e le c t
fS
¸
If the configuration options have selected both pins PA0
and PA1 to function as a BZ and BZ complementary pair
of buzzer outputs, then for correct buzzer operation it is
essential that both pins must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register
to zero. The PA0 data bit in the PA data register must
also be set high to enable the buzzer outputs, if set low,
8 - S ta g e P r e s c a le r
1 6
W D T O S C
P 0 S C 2 ~ P 0 S C 0
8 -to -1 M U X
9 - B it C o u n te r
W D T T im e - o u t
Watchdog Timer
Rev. 1.10
43
November 5, 2008
HT46R94
both pins PA0 and PA1 will remain low. In this way the single bit PA0 of the PA register can be used as an on/off control
for both the BZ and BZ buzzer pin outputs. Note that the PA1 data bit in the PA register has no control over the BZ
buzzer pin PA1.
PA0/PA1 Pin Function Control
PAC Register
PAC0
PAC Register
PAC1
PA Data Register
PA0
PA Data Register
PA1
Output
Function
0
0
1
x
PA0=BZ
PA1=BZ
0
0
0
x
PA0=²0²
PA1=²0²
0
1
1
x
PA0=BZ
PA1=input line
0
1
0
x
PA0=²0²
PA1=input line
1
0
x
D
PA0=input line
PA1=D
1
1
x
x
PA0=input line
PA1=input line
Note:
²x² stands for don¢t care
²D² stands for Data ²0² or ²1²
Note that no matter what configuration option is chosen
for the buzzer, if the port control register has setup the
pin to function as an input, then this will override the configuration option selection and force the pin to always
behave as an input pin. This arrangement enables the
pin to be used as both a buzzer pin and as an input pin,
so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by
the application program by programming the appropriate port control register bit.
If configuration options have selected that only the PA0
pin is to function as a BZ buzzer pin, then the PA1 pin
can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be setup as an output
by setting bit PAC0 of the PAC port control register to
zero. The PA0 data bit in the PA data register must also
be set high to enable the buzzer output, if set low pin
PA0 will remain low. In this way the PA0 bit can be used
as an on/off control for the BZ buzzer pin PA0. If the
PAC0 bit of the PAC port control register is set high, then
pin PA0 can still be used as an input even though the
configuration option has configured it as a BZ buzzer
output.
In te r n a l C lo c k S o u r c e
P A 0 D a ta
B Z O u tp u t a t P A 0
P A 1 D a ta
B Z O u tp u t a t P A 1
Buzzer Output Pin Control
Note
The above drawing shows the situation where both pins PA0 and PA1 are selected by configuration option to
be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup as output. The data setup on pin PA1 has no effect on the buzzer outputs.
Rev. 1.10
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November 5, 2008
HT46R94
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later as the application software has no control over the configuration options. All options must
be defined for proper system function, the details of which are shown in the table.
No.
Options
I/O Options
1
PA0~PA7: wake-up enable or disable - bit option
2
PA pull-high enable or disable - By port
Oscillator Option
3
System oscillator: Crystal or RC
PWM Options
4
PA4~PA6: PWM0~PWM2 function selection
5
PWM mode: 6+2 or 7+1 mode selection
Timer Options
6
Timer/Event Counter 0 clock sources: fSYS/4 or fSP
PFD Options
7
PA7: normal I/O or PFD output
Buzzer Options
8
Buzzer function: single BZ enable, both BZ and BZ or both disable
9
Buzzer frequency: fS/2, fS/4, fS/8, fS/16
Time Base Options
10
Time base time-out period: fS/25, fS/26, fS/27, fS/28, fS/29, fS/210, fS/211, fS/212
Watchdog Options
11
Watchdog Timer clock source: WDT oscillator, RTC oscillator or fSYS/4
12
Watchdog Timer function: enable or disable
13
CLRWDT instructions: 1 or 2 instructions
LVR Options
14
LVR function: enable or disable
15
LVR voltage: 2.1V, 3.15V or 4.2V
Lock Options
16
Lock All
17
Partial Lock
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Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
0 .1 m F
V S S
O S C
C ir c u it
P
0 /B
1 /B
M R
M R
W M
W M
W M
/P F
Z
Z
1
0
0
1
D
2
P B 0 /A N 0 ~ P B 7 /A N 7
P
P C
P C
P C
P C
O S C 1
O S C 2
S e e O s c illa to r
S e c tio n
3 2 7 6 8 H z
C ir c u it
P A
P A
P A
P A
P A
P A
P A
2 /T
3 /T
4 /P
5 /P
6 /P
A 7
C 0
4 /C
5 /C
6 /C
7 /C
~ P
O
O
O
O
C 3
M 0
M 1
M 2
M 3
P D 0 /IN T
P D 1 ~ P D 7
O S C 3
O S C 4 á
P E 0 ~ P E 7
S e e O s c illa to r
S e c tio n
H T 4 6 R 9 4
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.10
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
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Package Information
44-pin QFP (10mm´10mm) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
Rev. 1.10
1 1
Dimensions in mm
Min.
Nom.
Max.
A
13
¾
13.4
B
9.9
¾
10.1
C
13
¾
13.4
D
9.9
¾
10.1
E
¾
0.8
¾
F
¾
0.3
¾
G
1.9
¾
2.2
H
¾
¾
2.7
I
0.25
¾
0.5
J
0.73
¾
0.93
K
0.1
¾
0.2
L
¾
0.1
¾
a
0°
¾
7°
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HT46R94
52-pin QFP (14mm´14mm) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
A
Rev. 1.10
1 3
Dimensions in mm
Min.
Nom.
Max.
17.3
¾
17.5
B
13.9
¾
14.1
C
17.3
¾
17.5
D
13.9
¾
14.1
E
¾
1
¾
F
¾
0.4
¾
G
2.5
¾
3.1
H
¾
¾
3.4
I
¾
0.1
¾
J
0.73
¾
1.03
K
0.1
¾
0.2
a
0°
¾
7°
61
November 5, 2008
HT46R94
Holtek Semiconductor Inc. (Headquarters)
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Tel: 886-3-563-1999
Fax: 886-3-563-1189
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http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
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November 5, 2008