HT82V863R CCD Digital Signal Processor Features General Description • Input: Supports Ye, Mg, Cy, G colour filters for NTSC/PAL, 270K/320K/410K/470K CCD sensors The HT82V863R is a single chip digital image processor for Ye, Cy, Mg and G colour CCD video camera systems. It receives CFA patterns from colour CCDs and generates NTSC/PAL CVBS signals using internal video encoders and the 10-bit DAC. In addition, it also provides an AE/AWB algorithm, timing generation module together with other circuitry. • Output: NTSC/PAL Analog CVBS • Automatic CCD Defect compensation Up to 50 bad pixels and 4 consequential bad pixels correction • Automatic Back Light compensation • Programmable False Colour suppression The device contains a microcontroller in which an OTP ROM is integrated internally to implement the basic camera functions such as the AE/AWB algorithm. The video camera system consists of a CDS/AGC/ADC IC (HT82V842A), DSP IC (HT82V863R), Vertical Driver IC (HT82V805) and CCD sensors. It also provides a proprietary function to eliminate so called “line crawl” and automatic CCD defect compensation function to correct up to 30 bad pixels and 4 consequential bad pixels. • Programmable High Light suppression • Programmable Sharpness enhancement • Programmable Colour Saturation and Hue function • Programmable Contrast and Brightness function • Programmable GAMMA curve • Integrate a 96-step CCD timing generator • Support AE/AWB algorithm function • Support OSD function • Integrate a 2-D DNR function • Integrate the digital WDR • Integrate the digital Line Lock function to reduce colour rolling • Integrate a NTSC/PAL video encoder • Integrate a 10-bit DAC • Support CCIR656 digital out • Integrate a one-channel 6-bit ADC • Integrate OTP ROM with ISP function for multiple programming codes • Support Mirror function • Support a master I2C interface for external EEPROM to store parameters • Support a slave I2C interface for communication with an external host • Embedded LVR and POR circuits • Embedded 3.3V-to-1.8V regulator • Single 3.3V power supply • 64/80-LQFP package Rev. 1.00 1 September 30, 2011 HT82V863R Block Diagram Rev. 1.00 2 September 30, 2011 HT82V863R Pin Assignment VIDEO AVDD AVSS OP_INP OP_OUT ADC_IN PVDD33 GPIO6_OHS GPIO5_PREF PVSS AFE_CK AFE_DO GPIO0_CSN RST_N XOUT XIN 64 63 62 61 60 59 58 5756 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 HT82V863R 8 41 64 LQFP-A 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 1718 19 2021 2223 2425 26 2728 29303132 AFE_DIN9 AFE_DIN8 AFE_DIN7 AFE_DIN6 PVDD33 AFE_DIN5 AFE_DIN4 AFE_DIN3 AFE_DIN2 AFE_DIN1 AFE_DIN0 PVSS PVDD33 AFE_OBP AFE_PBLK AFE_ADCLP VREF BIAS COMP FSA AVDD AVSS PVDDREG DVDD18 DVSS PVSS PVDD65 GPIO1_SSCL GPIO2_SSDA PVDD33 GPIO3_MSCL GPIO4_MSDA PCLK_O PVSS VD_V1 VD_V2 VD_V3 VD_V4 VD_VSG1 VD_VSG2 VD_VSUB PVDD33 CCD_RG CCD_H1 CCD_H2 PVSS AFE_SHP AFE_SHD AVDD AVSS OP_INP OP_OUT ADC_IN GPIO7 CCIR_D7 CCIR_D6 PVDD33 GPIO6_OHS GPIO5_PREF PVSS AFE_CK AFE_DO GPOI0_CSN RST_N CCIR_D5 CCIR_D4 XOUT XIN CCIR_D3 CCIR_D2 CCIR_D1 CCIR_D0 PVSS AFE_DIN9 AFE_DIN8 AFE_DIN7 AFE_DIN6 PVDD33 AFE_DIN5 AFE_DIN4 AFE_DIN3 AFE_DIN2 AFE_DIN1 AFE_DIN0 PVDD33 AFE_OBP AFE_PBLK AFE_ADCLP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 6463 62 61 60 59 58 57 56 55 7 54 8 53 9 52 HT82V863R 10 51 80 LQFP-A 11 40 12 49 13 48 14 47 15 46 45 16 44 17 43 18 42 19 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3738 39 40 1 2 3 4 5 6 VIDEO VREF BIAS COMP FSA AVDD AVSS PLL_VCO AVSS PVDDREG DVDD18 DVSS CCIR_CLK PVSS PVDD65 GPIO1_SSCL GPIO2_SSDA PVDD33 GPIO3_MSCL GPIO4_MSDA GPIO11 GPIO10 GPIO9 GPIO8 PCLK_O PVSS VD_V1 VD_V2 VD_V3 VD_V4 VD_VSG1 VD_VSG2 VD_VSUB PVDD33 CCD_RG CCD_H1 CCD_H2 PVSS AFE_SHP AFE_SHD Rev. 1.00 3 September 30, 2011 HT82V863R Pin Description Pin Name DIR TYP PUL Description mA CCIR_D3 O — — 4 CCIR656 Encoder Data Output bit 3 CCIR_D2 O — — 4 CCIR656 Encoder Data Output bit 2 CCIR_D1 O — — 4 CCIR656 Encoder Data Output bit 1 CCIR_D0 O — — 4 CCIR656 Encoder Data Output bit 0 PVSS — P — — Pad ground pin I — — — CCD Data input bit 9 AFE_DIN9 AFE_DIN8 I — — — CCD Data input bit 8 AFE_DIN7 I — — — CCD Data input bit 7 CCD Data input bit 6 AFE_DIN6 I — — — — P — — 3.3V pad power pin AFE_DIN5 I — — — CCD Data input bit 5 AFE_DIN4 I — — — CCD Data input bit 4 PVDD33 AFE_DIN3 I — — — CCD Data input bit 3 AFE_DIN2 I — — — CCD Data input bit 2 AFE_DIN1 I — — — CCD Data input bit 1 AFE_DIN0 I — — — CCD Data input bit 0 PVSS — P — — Pad ground pin PVDD33 — P — — 3.3V pad power pin AFE_OBP O — — 4 Clamp pulse output for optical black function AFE_PBLK O — — 4 Blanking pulse output for AFE AFE_ADCLP O — — 4 Clamp pulse output for AFE AFE_SHD O — — 4 Sample hold pulse output for data AFE_SHP O — — 4 Sample hold pulse output for reference PVSS — P — — Pad ground pin CCD_H2 O — — 12 Horizontal shift register Clock 2 for CCD CCD_H1 O — — 12 Horizontal shift register Clock 1 for CCD CCD_RG O — — 12 Reset pulse output for CCD PVDD33 — P — — 3.3V pad power pin VD_VSUB O — — 4 CCD substrate bias pulse output for Vertical Driver VD_VSG2 O — — 4 Readout pulse 2 for Vertical Driver VD_VSG1 O — — 4 Readout pulse 1 for Vertical Driver VD_V4 O — — 4 Vertical shift register clock 4 for Vertical Driver VD_V3 O — — 4 Vertical shift register clock 3 for Vertical Driver VD_V2 O — — 4 Vertical shift register clock 2 for Vertical Driver Vertical shift register clock 1 for Vertical Driver VD_V1 O — — 4 PVSS — P — — Pad ground pin PCLK_O O — — 12 Pixel Clock Output GPIO8 B — U 4 GPIO [8] or PWM [3] output GPIO9 B — U 4 GPIO [9] or UART Receiver data input, RXD. GPIO10 B — U 4 GPIO [10] GPIO11 B — U 4 GPIO [11] GPIO4_MSDA B — U 4 GPIO [4] or Master mode I2C Data Input/Output GPIO3_MSCL B — U 4 GPIO [3] or Master mode I2C Clock Output PVDD33 — P — — 3.3V pad power pin GPIO2_SSDA B — U 4 GPIO [2] or Slave mode I2C Data Input/Output GPIO1_SSCL B — U 4 GPIO [1] or Slaver mode I2C Clock Input Rev. 1.00 4 September 30, 2011 HT82V863R Pin Name DIR TYP PUL Description mA PVDD65 — P — — 6.5V pad power pin PVSS — P — — Pad ground pin CCIR_CLK O — — 12 CCIR656 Encoder Clock Output DVSS — P — — Digital ground pin DVDD18 — P — — 1.8V digital power pin PVDDREG — P — — 3.3V regulator power pin AVSS — P — — OP, DAC and Regulator Ground pin. PLL_VCO AO — — — PLL VCO Output AVSS — P — — OP, DAC and Regulator Ground pin AVDD — P — — 3.3V OP and DAC Power pin FSA AO — — — DAC Full-Scale Adjust Control COMP AO — — — DAC Compensation pin BIAS AO — — — DAC Current Source Bias Pin VREF AI — — — DAC Bandgap Reference Voltage Output VIDEO AO — — — DAC VIDEO Output AVDD — P — — 3.3V OP and DAC Power pin AVSS — P — — OP and DAC Ground pin OP_INP AI — — — OP Buffer Positive Input OP_OUT AO — — — OP Buffer Output ADC_IN AI — — — A/D Converter Analog Input GPIO7 B — U — GPIO [7] or 27MHz Clock input CCIR_D7 O — — 4 CCIR656 Encoder Data Output bit 7 CCIR_D6 O — — 4 CCIR656 Encoder Data Output bit 6 PVDD33 — P — — 3.3V pad power pin GPIO6_OHS B — U 4 GPIO [6] or PWM [2] output or UART Transmitter data output, TXD, or Digital Video HSYNC Output. GPIO5_PREF B — U 4 GPIO [5] or PWM [1] output or Power Line Reference Clock Input PVSS — P — — Pad ground pin AFE_CK O — — 4 SPI Clock Output for AFE AFE_DO O — — 4 SPI Data Output for AFE GPIO0_CSN B — U 4 GPIO[0] or PWM[0] output or UART Transmitter data output, TXD, or SPI Chip Enable Output for AFE RST_N I S — — System Reset, Active Low CCIR_D5 O — — 4 CCIR656 Encoder Data Output bit 5 CCIR_D4 O — — 4 CCIR656 Encoder Data Output bit 4 XOUT O — — — Oscillator output XIN I — — — Oscillator input for MCLK Note: DIR: pin direction, B: bi-directional, O: output, AI: Analog input, AO: Analog output, TYP: pin type T: tri-state, OD: open-drain, S: Schmitt trigger, P: Power pin I: input PUL: pin internal pull up/down 75Ω resistor U: pull-up, Rev. 1.00 D: pull-down, mA: pin driving current capability 5 September 30, 2011 HT82V863R Absolute Maximum Ratings Output Voltage Vout.............................-0.3V~VCC+0.3V Power Supply Voltage VCC......................... -0.3V~4.3V Storage Temperature TSTG....................... -40°C~150°C Input Voltage VIN. ..............................-0.3V~VCC+0.3V Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Recommended Operating Conditions Symbol Parameter Min. Typ. Max. Unit V VCC Power supply 3.0 3.3 3.6 VIN Input voltage 0 — VCC V TOP Operating temperature -20 25 70 °C fCK Input clock frequency — 28.7 — MHz D.C. Characteristics Condition Min. Typ. Max. Unit VIL Symbol Input low voltage Parameter — — — 0.8 V VIH Input high voltage — 2.0 — — V VOL Output low voltage — — — 0.4 V VOH Output high voltage — 2.4 — — V IDD Operating current — — 80 — mA VT− Schmitt trigger input low voltage — 0.8 1.1 — V VT+ Schmitt trigger input high voltage — — 1.6 2.0 V RI Input pull-up/pull-down resistance — 75 — Ω VIL=0V or VIH=Vcc A.C. Characteristics Clock Characteristics Min. Typ. Max. Unit tCK Symbol Oscillator Clock Frequency Parameter -500ppm 28.7 +500ppm MHz DCK Oscillator Clock Duty Cycle 45 50 55 % Min. Typ. Max. Unit — 1 — ms Reset Characteristics Symbol tRST_N Rev. 1.00 Parameter External System Reset pulse width 6 September 30, 2011 HT82V863R CCD Input Interface Timing Symbol Test Condition Parameter VDD Conditions Min. Typ. Max. Unit fS Conversion Frequency 3.0V — 0.5 — 20 MHz tCYC Clock Cycle Time 3.0V — 50 — — ns tR Clock Rising Time 3.0V — — — 2 ns tF Clock Falling Time 3.0V — — — 2 ns tL Clock Low Period 3.0V — 23 — — ns tH Clock High Period 3.0V — 23 — — ns tWR SHR Pulse Width 3.0V — 11 — — ns tWD SHD Pulse Widh 3.0V — 11 — — ns tDR SHR Sampling Aperture 3.0V — — — 4 ns tDD SHD Sampling Aperture 3.0V — — — 4 ns tPSUP Data Pulse Setup 3.0V — 2 — — ns tHOLD Data Pulse Hold 3.0V — 5 — — ns tSP Sampling Pulse Non-overlay 3.0V — 1 — — ns tSUPE Enable Pulse Setup 3.0V — 10 — — ns tHOLDE Enable Pulse Hold 3.0V — 10 — — ns tSUPOC OUTCK Setup 3.0V — 0 — — ns — tHOLDC OUTCK Hold 3.0V 10 — — ns tDLD 3-state Disable Delay 3.0V Active→High-Z — 20 — ns tDLE 3-state Disable Delay 3.0V High-Z→Active — 20 — ns tOL ADC Output Data Delay 3.0V — 18 — ns — Note: Normally, the AFE ASIC registers are set to ignore OUTCK, and only use ADCK. Rev. 1.00 7 September 30, 2011 HT82V863R TV Encoder Output Interface Timing NTSC Vertical Timing Equalizing Pulse and Sync Pulse Interval Timing Table equalizing pulse and sync pulse interval timing. Symbol p Characteristics(μs) Duration of equalizing pulse q Duration of field-synchronizing pulse r Interval between field-synchronizing pulse s Build-up timing (10 to 90%) Rev. 1.00 8 NTSC PAL 2.3±0.1 2.35±0.1 27.1 27.3 4.7±0.1 4.7±0.2 ≤0.25 0.2±0.1 September 30, 2011 HT82V863R Details of Line Synchronizing Signal Table Details of line synchronizing signal. Symbol Characteristics (μs) NTSC PAL 4.7±0.1 4.7±0.2 Build-up time of the line-blanking pulse ≤0.48 0.3±0.1 Build-up time of the line-synchronizing pulse ≤0.25 0.2±0.1 d Synchronizing pulse e f b Line-blanking interval 9.2~10.3 12±0.2 c Front porch 1.27~2.22 1.5±0.3 g Start of sub-carrier burst h Duration of sub-carrier burst H Nominal line period 4.71~5.71 5.6±0.1 2.23~3.11(9±1 cycles) 2.25±0.23(10±1 cycles) 63.5555 64 CCIR656 Encoder Interface Timing The CCIR656 Encoder connects to the digital component video signals using 525 lines for NTSC systems or 625 lines for PAL systems. The data stream is a sequence of 8-bit bytes, transmitted at a rate of 27 MBbyte/s. The video pixel data horizontal scan lines are delimited in the stream using 4-byte long SAV (Start of Active Video) and EAV (End of Active Video) code sequences. Individual pixels in a line are coded in YCbCr “4:2:2” format. After an SAV code (4 bytes) is sent, the first 8 bits of Cb (chroma U) data are sent and then 8-bit data of Y (luma), followed by 8-bit data of Cr (chroma V) for the next pixel and then 8 bits of Y. TV System PAL (625 lines) NTSC (525 lines) V-digital field blanking Field 1 Field 2 Start (V=1) Line 624 Line 1 Finish (V=0) Line 23 Line 10 Start (V=1) Line 311 Line 264 Finish (V=0) Line 336 Line 273 F-digital field identification Field 1 F=0 Line 1 Line 4 Field 2 F=1 Line 313 Line 266 Video DatField-Blanking Definition Rev. 1.00 9 September 30, 2011 HT82V863R Horizontal Timing One Scan Line Parallel Interface Data SPI Interface Timing Symbol Parameter Conditions Min. Max. Units fSK SK Clock Frequency — 0 250 kHz fSKH SK High Time — 1 — μs fSKL SK Low Time — 1 — μs tCS Minimum CS Low Time — 1 — μs tCSS CS Setup Time — 0.2 — μs tDH DO Hold Time — 70 — ns tDIS DI Setup Time — 0.4 — μs tCSH CS Hold Time — 0 — ns tDIH DI Hold Time — 0.4 — μs tPD Output Delay — — 2 μs tSV CS to Status Valid — — 1 μs tDF CS to DO in Hi-Z — 0.4 μs tWP Write Cycle Time — 15 ms Rev. 1.00 CS=VIL — 10 September 30, 2011 HT82V863R I2C Interface Timing Byte Write Timing Page Write Timing Current Read Timing Random Read Timing Sequential Read Timing Rev. 1.00 11 September 30, 2011 HT82V863R Symbol Parameter Remark Standard Mode* VCC=5V±10% Min. Max. Min. Max. Unit fSK Clock Frequency — — 100 — 400 kHz tHIGH Clock High Time — 4000 — 600 — ns tLOW Clock Low Time — 4700 — 1200 — ns tR SDA and SCL Rise Time Note — 1000 — 300 ns tF SDA and SCL Fall Time Note — 300 — 300 ns tHD:STA START Condition Hold Time After this period the first clock pulse is generated 4000 — 600 — ns tSU:STA START Condition Setup Time Only relevant for repeated START condition 4000 — 600 — ns tHD:DAT Data Iuput Hold Time — 0 — 0 — ns tSU:DAT Data Iuput Setup Time — 200 — 100 — ns tSU:STO STOP Condition Setup Time — 4000 — 600 — ns tAA Output Valid from Clock — — 3500 — 900 ns 4700 — 1200 — ns — 100 — 50 ns — 5 — 5 ms tBUF Bus Free Time Time in which the bus must be free before a new transmission can start tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time tWR Write Cycle Time — A/D Converter Interface Timing Rev. 1.00 12 September 30, 2011 HT82V863R Functional Description A/D Converter The device provides a 6-bit A/D Converter. CCD Interface OSD Generator The CCD interface is used to capture the image and receive the CMYG CFA CCD raw data and the control signals generated from the analog front-end module. Then the CCD raw data together with the control signals will be correctly manipulated such as for black clamp operation, bad pixel compensation, etc. The processed raw data and control signals will be eventually sent to the Colour Image Processor to perform further image signal manipulations. The device can generate up to 4 lines with a maximum of 16 characters, each of which can be up to 16×16 font size. The scaling factor can be up to 8 times on both the horizontal direction and vertical direction. Back Light Compensation – BLC The Back Light Compensation will provide perfect exposure for an object in front of very strong back light, no matter whether the main object is moving toward the center, upper, lower, left, right part or any location in the screen. The HT82V863R device provides a smart adaptive BLC algorithm to perform compensation, followed by the exposure level, with a fast speed so that no matter where on the screen the main object is moving to, it always provides a clear picture. Colour Image Processor The heart of the surveillance camera is the Colour Image Processor in which the raw data derived from the CCD interface is processed. In addition to the colour mosaic interpolation, several colour image processor main functions include the edge extraction and enhancement, colour correction, auto exposure support and white balance, colour space transform, gamma correction and false colour suppression. DWDR Timing Generator Digital WDR is a proprietary algorithm to provide clear images even under back light circumstances where there are both very bright and very dark areas simultaneously in the view of the camera. In short, DWDR allows the viewer to see details in both areas. This is a programmable 96-step precision timing generator embedded with a DLL to perform timing fine tuning and to generate all the CCD data related control timings. CCIR656 Encoder TV Encoder The CCIR656 Encoder accepts the data stream derived from the Colour Image Processor and converts the data into ITU_R BT656 digital output signals. This provides a 10-bit YCbCr digital input interface to accept the data stream sent from the Colour Image Processor (or equivalent circuitry) and to convert the data into the NTSC or PAL TV composite signal or Y/C signal. I2C Interface Line Lock The device integrates an OTP ROM for firmware storage. The firmware can be easily programmed into the OTP ROM using the In-System Programming function and the I2C interface. A Line-Lock function is available on most CCTV cameras and is used to prevent picture colour rolling on the monitor, which results from the difference between the surveillance camera exposure frequency and the AC power line frequency. Colour rolling will cause a vital picture information loss and will be irritating for the viewer. Rev. 1.00 Programming Considerations All configurations in this device are displayed in a user interface window as part of the relevant development tool system. Therefore, the detailed configuration and definitions are not mentioned in this document. Refer to the corresponding user’s manual for more detailed configuration information. 13 September 30, 2011 HT82V863R System Application Diagram 1 Rev. 1.00 14 September 30, 2011 HT82V863R Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 64-pin LQFP (7mm×7mm) Outline Dimensions Symbol Min. Nom. Max. A 0.350 ― 0.358 B 0.272 ― 0.280 C 0.350 ― 0.358 D 0.272 ― 0.280 E ― 0.016 ― F 0.005 ― 0.009 G 0.053 ― 0.057 H ― ― 0.063 I 0.002 ― 0.006 J 0.018 ― 0.030 K 0.004 ― 0.008 α 0° ― 7° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A 8.90 ― 9.10 B 6.90 ― 7.10 C 8.90 ― 9.10 D 6.90 ― 7.10 E ― 0.40 ― F 0.13 ― 0.23 G 1.35 ― 1.45 H ― ― 1.60 I 0.05 ― 0.15 J 0.45 ― 0.75 K 0.09 ― 0.20 α 0° ― 7° 15 September 30, 2011 HT82V863R 80-pin LQFP (10mm×10mm) Outline Dimensions Symbol Nom. Max. A 0.469 ― 0.476 B 0.390 ― 0.398 C 0.469 ― 0.476 D 0.390 ― 0.398 E ― 0.016 ― F ― 0.006 ― G 0.053 ― 0.057 H ― ― 0.063 I ― 0.004 ― J 0.018 ― 0.030 K 0.004 ― 0.008 α 0° ― 7° Symbol Rev. 1.00 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 11.90 ― 12.10 B 9.90 ― 10.10 C 11.90 ― 12.10 D 9.90 ― 10.10 E ― 0.40 ― F ― 0.16 ― G 1.35 ― 1.45 H ― ― 1.60 I ― 0.10 ― J 0.45 ― 0.75 K 0.10 ― 0.20 α 0° ― 7° 16 September 30, 2011 HT82V863R Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright© 2011 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 17 September 30, 2011