[AK7719] AK7719 Low Power DSP for Voice and Audio Processing GENERAL DESCRIPTION The AK7719 is a highly integrated digital signal processor (DSP) with four digital interface ports. AKM’s DSP core is optimized for both narrowband and wideband voice processing, as well as full bandwidth digital audio processing. An integrated clock generator for the DSP master clock eliminates the need for external clocks. The RAM-based DSP can be programmed for user requirements. The AK7719 is housed in a 25-pin CSP package. It is a very low power device, suitable for mobile applications. FEATURES □ Embedded DSP - Flexible programming with built-in program and data memories - Hardware accelerator - Word length: 24-bits (Data RAM 24-bit floating point) - Multiplier 20 x 20 Æ 40-bits (double precision available) - Divider 20 / 20 Æ 20-bits - ALU: 44-bit arithmetic operation (with 4-bit overflow margin) 24-bit floating point arithmetic and logic operation - Program RAM: 4096w x 36-bits - Coefficient RAM: 2048w x 20-bits - Data RAM: 2048w x 24-bits (24-bit floating point) - Offset Register: 32w x 15-bits - Delay RAM: 16384w x 24-bits(24-bit floating point) - 5625 steps at 16kHz sampling rate, 1875 steps at 48kHz sampling rate - Internal clock generator □ Audio Interface Format - 24-bit Left justified, I2S, - 16/24bit linear, 8-bit A-law, 8-bit µ-law PCM - Sampling rate 8kHz ~ 48kHz - Up/Down Sampling rate converter for Port#2 (8kHz → 16kHz) □ μC I/F: I2C-Compatible, SPI □ Operational, Sleep, Power down □ Power Supply VDD (DSP Core): 1.2V ±0.1V TVDD (PCM I/F): 1.6V ~ 3.6V Operating Temperature Range: -20°C ~ 85°C □ □ Package: 25-Pin WL-CSP (2.62mm x2.93mm, 0.5mm pitch) □ Power Consumption: 6.2mA (7.5mW) typ. (Narrowband Hands Free mode operation) MS1351-E-00-PB 2012/01 1 [AK7719] ■ Block Diagram VSS PDN TVDD VDD TEST SYNC1 PCM BCLK1 Interface1 (Port#1) SDIN1 SDOUT1 AKM DSP Core DIN1 PCM Interface2 DOUT2 BCLK2 (Port#2) SDOUT2 SDIN2 DIN2 DOUT1 SYNC2 PCM DOUT4/GP1 SYNC3/JX1 SDOUT3/GP0 (Port#4) SDOUT4/GP1 SDIN4 JX0 BCLK3/JX0 SDIN3 DIN4 JX1 Interface4 PCM Interface3 (Port#3) WDT/CRC DIN3 DOUT3/GP0 STO/RDY RDY I2C Control Interface CGU (CLK Gen Unit) SCLK/CAD0 SI/CAD1 DSPCLK CSN/SCL Memory SO/SDA Figure 1. Block Diagram MS1351-E-00-PB 2012/01 2 [AK7719] ■ Ordering Guide -20 ∼ +85°C 25-pin CSP (0.5mm pitch) Black type Evaluation board for AK7719 AK7719ECB AKD7719 ■ Pin Layout Top View 5 5 4 4 3 3 2 INDEX MARK 2 1 A B C D Bottom View 1 E E BCLK1 D C 5 PDN SDIN1 SDOUT1 4 VDD BCLK3/ JX0 SDIN3 3 VSS SYNC3/ JX1 TEST STO/ RDY BCLK2 2 TVDD I2C SDIN4 SDOU4/ GP1 SDIN2 1 SI/CAD1 SCLK/ CAD0 CSN/ SCL A B C B A SYNC1 SDOUT3/ SYNC2 GP0 SO/ SDA SDOUT2 D E TOP View MS1351-E-00-PB 2012/01 3 [AK7719] PIN/FUNCTION NO A4 A2 A3 Pin Name VDD TVDD VSS A5 PDN D3 STO RDY E5 SYNC1 D5 BCLK1 B5 C5 E4 E3 E2 E1 I/O Function - Core Power Supply Pin 1.2V - I/O power Supply Pin 1.6∼3.6V - Ground Pin 0V P Power-Down Mode Pin I “H”: Power-up, “L”: Power-down, reset the control register. The AK7719 must be reset once upon power-up. Status Output Pin (Active High) (STRDY bit = “0”) O Data Write Ready output pin for control I/F (STRDY bit = “1”) Frame Sync 1 pin I Serial Data Clock 1 Pin I AK7719 goes into standby state when BCLK1 is not present. I Serial Data Input 1 Pin O Serial Data Output 1 Pin SDIN1 SDOUT1 SYNC2 O Frame Sync 1 pin BCLK2 O Serial Data Clock 2 Pin SDIN2 I Serial Data Input 2 Pin SDOUT2 O Serial Data Output 2 Pin SYNC3 Frame Sync 3 pin (SELPT bit = “1”) B3 I Conditional Jump 1 Pin (SELPT bit = “0”) JX1 BCLK3 Serial Data Clock 3 Pin (SELPT bit = “1”) B4 I JX0 Conditional Jump 0 Pin (SELPT bit = “0”) C4 SDIN3 I Serial Data Input 3 Pin SDOUT3 Serial Data Output 3 Pin (SELDO3 bit = “0”) D4 O GP0 DSP Programmable output 0 Pin (SELDO3 bit = “1”) C2 SDIN4 I Serial Data Input 4 Pin Serial Data Output 4 Pin (SELDO4 bit = “0”) SDOUT4 D2 O GP1 DSP Programmable output 1 Pin (SELDO4 bit = “1”) B2 I2C I Control Interface Mode Select Pin “H”: I2C, “L”: SPI Serial Clock Input pin SPI (I2C pin = “L”) SCLK B1 I CAD0 Slave Address 0 Input pin I2C (I2C pin = “H”) Chip select pin SPI (I2C pin = “L”) CSN C1 I SCL Control Interface clock input pin I2C (I2C pin = “H”) SPI (I2C pin = “L”) SO O Serial data output pin D1 SDA I/O Control Interface input/output acknowledge pin I2C (I2C pin = “H”) Serial data input pin SPI (I2C pin = “L”) SI A1 I CAD1 Slave Address 1 Input pin I2C(I2C pin = “H”) C3 TEST I Test pin (pull-down resistor) must be connected to VSS. Note 1. All input pins must not be allowed to float. Note 2. I2C and CAD0/1 pins must be fixed to “L” (VSS) or “H” (TVDD). MS1351-E-00-PB 2012/01 4 [AK7719] DSP Block Diagram Pointer CP0, CP1 DP0, DP1 Data RAM Coefficient RAM Delay RAM 16384w x 24-Bit 2048w x 24-Bit 2048w x 20-Bit Offset Reg 32w x 15-Bit DLP0, DLP1 CBUS(20-Bit) DBUS(24-Bit) MPX20 Micon I/F MPX20 X Control PRAM DEC Y Serial I/F 4096w x 36-Bit Multiply 20 x 20 → 40-Bit PC Stack: 5 levels(max) 24-Bit 40-Bit TMP 12 x 24-Bit PTMP(LIFO) 6 x 24-Bit MUL DBUS 2 x 16/24-Bit DIN4 2 x 16/24-Bit DIN3 2 x 16/24-Bit DIN2 2 x 16/24-Bit DIN1 ALU 2 x 16/24-Bit DOUT4 44-Bit 2 x 16/24-Bit DOUT3 2 x 16/24-Bit DOUT2 2 x 16/24-Bit DOUT1 SHIFT 44-Bit 40-Bit A B Overflow Margin: 4-Bit 40-Bit DR0 ∼ 3 40-Bit Accelerator Over Flow Data Generator Division 20÷20→20 Peak Detector MS1351-E-00-PB 2012/01 5 [AK7719] ■ Handling of Unused Pins Unused I/O pins must be connected appropriately: Pin Name STO/RDY, SDOUT3/GPO, SDOUT4/GP1 SYNC1, BCLK1, SDIN1, SDIN2, SDIN3, SDIN4, SYNC3/JX1, BCLK3/JX0, TEST Setting Leave Open Connect to VSS. ■ Pin States in Power-down Mode The table below shows pin states when the PDN pin= “L”. NO Pin Name I/O Pin state Low STO D3 O RDY C5 SDOUT1 O SDIN2 data output E4 SYNC2 O SYNC1 data output E3 BCLK2 O BCLK1 data output E1 SDOUT2 O SDIN1 data output SDIN4 data output SDOUT3 D4 O GP0 SDIN3 data output SDOUT4 D2 O GP1 SO O Low level (I2C pin = “L”: SPI) D1 SDA I/O Hi-z (I2C pin = “H” :I2C) ABSOLUTE MAXIMUM RATINGS (VSS=0V; All voltages are with respect to ground.) Parameter Symbol min Power Supply Voltage (DSP Core) VDD −0.3 Power Supply Voltage (Digital I/O) TVDD −0.3 Input Current (except for power supply pins) IIN Input Voltage VIND −0.3 Operating Ambient Temperature Ta −20 Storage Temperature Tstg −65 max 1.6 4.1 ±10 TVDD+0.3 85 150 Unit V V mA V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATION CONDITION (VSS=0V; All voltages are with respect to ground.) Parameter Symbol min typ max Unit Supply Voltage Range (DSP core) VDD 1.1 1.2 1.3 V Supply Voltage Range (I/Os) TVDD 1.6 1.8 3.6 V Note 3. The power-up sequence with VDD and TVDD is not critical. The PDN pin should be held “L” when power is supplied. The PDN pin is allowed to be “H” after all power supplies are applied and settled. Note 4. The external pull-up resistors at the SDA and SCL pins should be connected to TVDD voltage or less. WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet. MS1351-E-00-PB 2012/01 6 [AK7719] ELECTRIC CHARACTERISTICS DC CHARACTERISTICS (Ta=-20ºC~85ºC; VDD=1.2V, TVDD =1.6V~3.6V; VSS =0V) Parameter Symbol min High level input voltage VIH 70%TVDD Low level input voltage VIL VOH TVDD-0.2 High level inptu voltage Iout=-200μA (Note 5) VOL Low level input voltage Iout= 200μA (Note 5) SDA low level output TVDD ≥ 2.0V VOL voltage Iout=3mA TVDD < 2.0V Input leak current Note 5. Except for the SDA pin. Iin typ max 0.2 Unit V V V V 0.4 V 20%TVDD ±10 V μA 30%TVDD POWER CONSUMPTION (Ta=25ºC; VDD=1.2V; TVDD=1.8V; VSS =0V, fin=1 KHz, fs=8kHz 16 bit (FS bits=0h, LAW bits = 0h, DIF bit = 2h, DSP running with programmed connecting DIN1 with DOUT2 and DIN2 with DOUT1. Parameter min typ max Unit Power Supplies: Power-Up (PDN pin = “H”) DSP-Operational State All Circuit Power-up VDD 1.7 mA VDD=1.2V TVDD=1.8V (Note 6) TVDD 0.02 mA Power Consumption 2.1 mW All Circuit Power-up VDD 20 mA VDD=1.3V TVDD=3.6V (Note 6) TVDD 2.0 mA Power Consumption 33.2 mW Power-Down state (PDN pin = “L”), (Note 7) VDD 2.4 8 μA TVDD 0.2 1 μA Note 6. The current of VDD, TVDD changes depending on the system frequency and contents of the DSP program. Note 7. All digital input pins are fixed to TVDD or VSS. MS1351-E-00-PB 2012/01 7 [AK7719] SWITCHING CHARACTERISTICS ■ System Clock (Ta= -20ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V) CL=20pF (except SDA pin) or 400pF (SDA pin); unless otherwise specified Parameter Symbol min typ max Unit Normal Operation mode: SYNC1/3, BCLK1/BCLK3 Input Timing SYNC1/3 Input Timing SYNC1/3 frequency fs 8 48 kHz BCLK1 Input Timing (Note 8, Note 9) fBCLK 64 BCLK1/3 Pulse width Low BCLK1/3 Pulse width High tBCKL tBCKH 0.4 x tBCLK 3072 kHz ns ns 0.4x tBCLK Note 8. SYNC1 and BCLK1 or SYNC3 and BCLK3 should be synchronized and their sampling rates (fs) should be stable Note 9. Required fBCLK: ≥ 2 (Data length set by LAW bit) x SYNC2 frequency ■ Reset and Standby (Ta= -20ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V) Parameter Symbol min typ PDN (Note 10) tPDN 600 Note 10. The AK7719 can be reset by bringing the PDN pin = “L” upon power-up. max Unit ns ■ Serial Data Interface (Ta= -20ºC ~ 85ºC, TVDD= 1.6V ~ 3.6V, VSS=0V, CL=20pF) Parameter Symbols SDIN1, SDIN3, SDIN4, SDOUT1, SDOUT3, SDOUT4 Delay Time from BCLK1 “↑” to SYNC1 “↑” (Note 11) tBSYD Delay Time from SYNC1 “↓” to BCLK1 “↑” tSYBD Serial Data Input Latch Setup Time tB1IDS Serial Data Input Latch Hold Time tB1IDH Delay Time from SYNC1 to Serial Data Output tSY1OD Delay Time from BCLK1 “↓” to Serial Data Output (Note 12) tB1OD SDIN2, SDOUT2 SYNC2 Duty cycle Serial Data Input Latch Setup Time tB2IDS Serial Data Input Latch Hold Time tB2IDH Delay Time from SYNC2 to Serial Data Outputs tSY2OD Delay Time from BCLK2 “↓”to Serial Data Output (Note 13) tB2OD SDINn → SDOUTn (n=1, 2, 3) Delay time from SDINn to SDOUTn Output tIOD Note 11. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “↓” Note 12. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “↑”. Note 13. When the polarity of BCLK2 is inverted, delay time is from BCLK2 “↑”. MS1351-E-00-PB min typ max Unit 40 40 ns ns ns ns ns ns 40 40 % ns ns ns ns 60 ns 20 100 40 40 50 40 40 2012/01 8 [AK7719] ■ Timing Diagram 1/fs ts=1/fs 1/fs SYNC1/3 VIH VIL 1/fBCLK 1/fBCLK tBCLK=1/fBCLK VIH BCLK1/3 VIL Figure 2. System Clock PDN tPDN VIL Figure 3. Power-down MS1351-E-00-PB 2012/01 9 [AK7719] VIH VIL SYNC1/3 tBSYD tSYBD VIH VIL BCLK1/3 tB1IDS tB1IDH VIH VIL SDIN1/3/4 tSY1OD tB1OD SDOUT1/3/4 50%TVDD tIOD VIH VIL SDIN2/4/3 Figure 4. Serial Data Interface (Port#1, 3, 4) SYNC2 50%TVDD BCLK2 50%TVDD tB2IDS tB2IDH VIH VIL SDIN2 tSY2OD tB2OD SDOUT2 50%TVDD tIOD VIH VIL SDIN1 Figure 5. Serial Data Interface (Port#2) MS1351-E-00-PB 2012/01 10 [AK7719] ■ μP Interface (SPI Mode) (Ta= -20ºC ~ 85ºC, VDD=1.2V; TVDD=1.6~3.6V, VSS =0V; CL=20pF) Parameter Symbol μP Interface Timing (SPI mode) SCLK Fall Time tSF SCLK Rise Time tSR SCLK Frequency fSCLK SCLK Low Level Width tSCLKL SCLK High Level Width tSCLKH CSN High Level Width tWRQH From CSN “↑” to PDN “↑” tRST1 From PDN “↑” to CSN “↓” tIRRQ tWSC From SCLK “↓” to CSN “↑” From SCLK “↑” to CSN “↑” tSCW SI Latch Setup Time tSIS SI Latch Hold Time tSIH AK7719 → μP Delay Time from SCLK “↓”to SO Output tSOS Hold Time from SCLK “↑” to SO Output (Note 14) tSOH Note 14. Except when input the eighth bit of the command code. min typ max Unit 30 30 4.0 ns ns MHz ns ns ns ns μs ns ns ns ns 100 ns ns 120 120 500 600 100 500 800 100 100 100 tSR tSF VIH SCLK VIL tSCLKL tSCLKH 1/fSCLK 1/fSCLK VIH PDN VIL VIH CSN VIL tRST1 tIRRQ Figure 6. μP Interface 1 (SPI) MS1351-E-00-PB 2012/01 11 [AK7719] VIH CSN tWRQH VIL VIH SI VIL tSIH tSIS VIH SCLK VIL tWSC tSCW tWSC tSCW Figure 7. μP Interface 2 (SPI) VIH SCLK VIL VIH SO VIL tSOH tSOS Figure 8. μP Interface 3 (SPI) MS1351-E-00-PB 2012/01 12 CONFIDENTIAL [AK7719] ■ I²CBUS Interface (Ta=-20ºC~85ºC, VDD=1.2V, VDD=1.6~3.6V, VSS =0V, CL=20pF) Parameter Symbol min I²C Timing SCL clock frequency fSCL 30 Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time tHD:STA 0.6 (prior to first Clock pulse) Clock Low Time 1.3 tLOW Clock High Time 0.6 tHIGH Setup Time for Repeated Start Condition 0.6 tSU:STA SDA Hold Time from SCL Falling 0 tHD:DAT SDA Setup Time from SCL Rising 0.1 tSU: DAT Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition 0.6 tSU:STO Pulse Width of Spike Noise Suppressed tSP 0 by Input Filter Capacitive load on bus Cb 2 Note 15. I C-bus is a trademark of NXP B.V. typ max Unit 400 kHz μs μs μs μs μs μs μs μs μs μs 0.9 0.3 0.3 50 ns 400 pF VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start Figure 9. I2C Bus Interface MS1351-E-00-PB 2012/01 13 CONFIDENTIAL [AK7719] PACKAGE 25pin CSP (Unit: mm) 25 -φ0.285 ± Top View φ 0.05 M C 0.03 φ 0.15 M C A (0.040) A B 3 7719 2.62±0.03 4 5 B 1 E A D C B 0.5 1 2 XXXX A 0.565±0.059 0.385±0.029 0.5 2.93±0.03 0.075 C 0.180±0.03 C ■ Material & Lead Finish Package: Epoxy, Halogen (bromine and chlorine) free Solder ball material: SnAgCu MS1351-E-00-PB 2012/01 14 CONFIDENTIAL [AK7719] MARKING 7719 XXXX 1 A XXXX: Date code (4 digit) REVISION HISTORY Date (YY/MM/DD) 12/01/12 Revision 00 Reason First Edition Page MS1351-E-00-PB Contents 2012/01 15 CONFIDENTIAL [AK7719] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. 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As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Thank you for your access to AKM product information. More detail product information is available, please contact our sales office or authorized distributors. MS1351-E-00-PB 2012/01 16