DD-00429 ARINC 429 MICROPROCESSOR INTERFACE FEATURES DESCRIPTION two ARINC 429 Transmit channels (Tx0 and Tx1) and can transmit data independently. The transmit data rate can also be programmed independently. There are two 32 x 32 bit FIFOs for each of the transmitters that send out data. DDC's DD-00429 provides a complete and flexible interface between a microprocessor and an ARINC 429 data bus. The DD00429 interfaces to a processor through a 128 x 32 bit static RAM as well as four 32 x 32 receive FIFOs and two 32 x 32 transmit FIFOs. The DD-00429 can be easily interfaced to 8- or 16-bit processors via a buffered shared RAM configuration. The DD-00429 has the capability of programming three general purpose interrupts as well as generating an interrupt based on an error condition. The general purpose interrupts can be programmed to trigger other external hardware. They can either be LEVEL or PULSE triggered. The DD-00429, when configured with two DD-03282 Transceivers, supports four ARINC 429 Receive channels (Rx0, Rx1, Rx2 and Rx3) each receiving data independently. The receive data rates (high or low speed) for channel Rx0 and Rx1 can be programmed independently from Rx2 and Rx3. The DD-00429 can decode and sort data based on the ARINC 429 Label and SDI bits via the Data Match Processor and store it in RAM and/or FIFOs via the Data Store Processor. The features built into the DD-00429 enable the user to off-load the host processor and use that processing time to implement operations other than just polling the ARINC 429 Bus. The decoding and sorting of data allows the user to gather data much quicker than past designs. If the user requires a microprocessor in the avionics box, this device will facilitate a clean and quick design. The DD-00429, when configured with two DD-03182 Line Drivers, supports ARINC 429 RECEIVE 0 A1OUT B1OUT DD-03182 LINE DRIVER WRAPAROUND ARINC 429 Rx0 LOGIC WRAPAROUND ARINC 429 Rx1 LOGIC WRAPAROUND ARINC 429 Rx2 LOGIC WRAPAROUND ARINC 429 Rx3 LOGIC ARINC 429 RECEIVE 1 ARINC 429 RECEIVE 2 ARINC 429 RECEIVE 3 A2OUT B2OUT DD-03182 LINE DRIVER • Four ARINC 429 Receive Channels, (configured with DD-03282 Transceivers) • 128 x 32 Shared RAM Interface • Label and Destination Decoding and Sorting • Two ARINC 429 Transmit Channels (configured with DD-03182 Line Drivers) • Two 32 x 32 Transmit FIFO's • Interfaces Easily to 8- or 16-Bit Microprocessor • Built-in Fault Detection Circuitry • Free “C” Library Software • Application Note AN/A-6 “FAQ’s” 128 X 16 STATIC RAM DMT RAM 128 X 32 STATIC RAM Rx RAM CTRL DATA ADDR CTRL DATA ADDR Rx0 FIFO 32 WORDS Rx DATA DMP DATA DATA MATCH PROCESSOR DATA ADDR ADDR DATA Rx3 FIFO 32 WORDS ADDR 2 DATA ARINC 429 Tx0 LOGIC Tx FIFO 32 WORDS ARINC 429 Tx1 LOGIC Tx FIFO 32 WORDS DATA 2 INTERRUPT CONTROLLER 3 IRQ CPU INTERFACE 16 DATA 12 ADDR MICROPROCESSOR OR CPU DD-03282 TRANSCEIVER (2) FIGURE 1. CHIP SET BLOCK DIAGRAM © 1998, 1999 Data Device Corporation Rx2 FIFO 32 WORDS ADDR DATA ARINC 429 TRANSMIT 0 ARINC 429 TRANSMIT 1 DD-03182 LINE DRIVER (2) Rx1 FIFO 32 WORDS DATA STORE PROCESSOR DD-00429VP ASIC CONTROL TABLE 1. DD-00429 ABSOLUTE MAXIMUM RATINGS (Tc = +25°C Unless Otherwise Specified) PARAMETER MIN MAX UNITS DC Supply Voltage -0.3 7.0 Vdc Signal Input Voltage (logic Inputs) -0.3 Vdd+0.3 Vdc Signal Input Voltage (ARINC 429 Inputs -29 +29 Vdc Storage Temperature -65 150 °C Operating Temperature -55 125 °C Lead Temperature (soldering) 280 (for 3 sec) °C Body Temperature (soldering) 210 ( for 30 sec) °C TABLE 2. DD-00429 SPECIFICATIONS (Tc = +25°C Unless Otherwise Specified ) PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage Vdd 4.5 5.5 Vdc DC Supply Current Idd 50 mA Device operation @ 16 MHz, Typical Idd = 30 mA @ 5.0V. Input Logic Voltage Low Vil 0.8 Vdc Note: CLK input has hysteresis of 2.0 V max ↑ positive going, 1.0 V min ↓ negative going. Input Logic Voltage High Vih 2.0 Input Logic Current Low Iil -1.5 -0.2 mA -350 +350 nA -350 +350 nA 0.5 Vdc LOGIC INPUTS/OUTPUTS Input Logic Current High Iih Output Voltage Logic Low Vol Output Voltage Logic High Voh Vdd-0.5 Output Leakage Current Hi Z Ioz -500 dc Input pins with internal pull-up resistor, Intel/Moto, Pol .Sel, 8/16 Zero Wait, Master Reset. All other inputs and I/O pins. Vdc +500 ARINC 429 LINE INPUTS - SEE DD-03282 DATA SHEET ARINC 429 LINE OUTPUTS - SEE DD-03182 DATA SHEET 2 nA For all D0 - D15 and Dtack, Ready and IRQ outputs. ARINC 429 RECEIVERS the incoming ARINC 429 data contains a 00 in its S/D bit pair. The DD-00429 supports four ARINC 429 inputs, designated Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The architecture of each of the four receiver circuits is identical and each receives data independently. ARINC 429 data is directly received into the DD-03282 ARINC 429 transceiver. Input protection, in accordance with the ARINC 429 specification, is provided along with voltage level translation from +5 V bipolar, nonreturn-to-zero data to conventional, +5 V logic levels. 3) Receive Channel Number: Bits 12 and 13 of each DMT entry are compared to the number of the channel which received the ARINC 429 data. A Data Match has occurred when all of the previous conditions are satisfied; the data will then be stored in a RAM location whose address equals the matching DMT entry minus 200 hex. Bit 11 of each DMT entry, when set, will cause the incoming ARINC 429 data to be stored in the corresponding receive channel FIFO (as well as the Rx RAM) when the data match conditions are met. Receive Data Rates can be programmed for channels 0 and 1 independently of channels 2 and 3 via bits 2 and 3 of ARINC Control Register 2. The receiver circuitry will successfully decode an incoming ARINC 429 data stream as long as the data rate is within ±5% of the nominal rate as determined by the Hi Speed/Low Speed Bit and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock inputs may be tied to the 1 MHz receive clock output or may be connected to another clock source. The ARINC CLK input should nominally be 10 times (for High-Speed Mode) or 80 times (for Low-Speed mode) the desired ARINC Data Rate. ARINC CLK 0 is used by channels Rx0 and Rx1 while ARINC CLK 1 is used by channels Rx2 and Rx3. Bits 14 and 15 of each DMT entry provide the ability to cause one of three general purpose interrupts upon a data match condition. If set to “00” then no interrupt will occur upon a data match condition (more information on interrupts is described later). ARINC 429 TRANSMITTER(S) The DD-00429 supports two ARINC 429 transmitters. Each of these channels transmits data independently and are designated Tx0 and Tx1. The transmit output of the DD-00429 is a TTL encoded digital data stream which can be connected directly to DDC’s DD-03182 ARINC 429 line driver. Filtering and Sorting Rx Data: The receiver circuitry converts the serial data stream into a 32-bit-wide parallel data word. The 32-bit word is processed internally by a Data Match Processor (DMP). It compares the incoming data to a table of data initialized by the processor. This determines what incoming data is to be saved, where it is going to be saved, and if any interrupts are to be generated. The table of data is stored in a 128 word x 16 bit Data Match Table (DMT) RAM. When a match between the received ARINC 429 data and the criteria stored in a DMT entry is found, the received data, the storage address and modes, and interrupt parameters are passed to the Data Store Processor (DSP). The storage address in the Receive RAM is the address of the first matching DMT entry minus 200 hex. Transmit data rates can be programmed for Channels 0 and 1 independently. The transmit data rate is determined by the HighSpeed/Low-Speed Bit for each of the Tx channels in ARINC Control Register 2 and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two, 1 MHz ARINC clock inputs may be tied to the 1 MHz clock output or they may be connected to another clock source to achieve transmit data rates other than 100 kHz or 12.5 kHz. The transmit clock input should be 10 times (for High-Speed Mode) or 80 times (for Low-Speed mode) the desired ARINC transmit data rate. There are three requirements that must be met in order to match incoming ARINC 429 data to each DMT entry: Transmit FIFOs: Each transmitter channel is provided with an output FIFO which is 32 words deep by 32 bits wide. When writing data to the Tx FIFO, the associated Disable Txn bit in ARINC Control Register 1 can be set to a logic zero until the FIFO is loaded with the desired data. Upon setting the Disable Txn low the transmit channel will send the 32-bit message words with appropriate interword gaps on the ARINC 429 output. A status bit indicating that the FIFO is empty is supplied for each transmitter in the ARINC Status Register. 1) System Address Label: Bits 0-7 of the DMT are compared to the System Address Label (SAL) of the incoming ARINC 429 data word. If the DMT SAL entry is zero then the SAL of the incoming data word is ignored (or considered a match). 2) Source/Destination Bits: Bits 8 and 9 of each DMT entry are compared to the Source/Destination (S/D) bits of the incoming ARINC 429 data word. If these bits match, or if Bit 10 of the DMT entry is set to a 1, then the S/D bit comparison is considered a match. It is also possible, through DMP Control Register 1, to enable “All Call Mode” as defined in the ARINC 429 specification. When enabled for a particular receive channel, the S/D bits will be considered a match when Wraparound testing can be performed from Tx0 to Rx0 and Rx1 and from Tx1 to Rx2 and Rx3. The data received on Rx1 and Rx3 in wraparound test mode is inverted. Wraparound testing is enabled by setting the appropriate bits in ARINC Control Register 1. The parity of the transmitted word can be altered to even parity (instead of the usual odd parity) by setting the asso- 3 ERROR INTERRUPT OPERATION ciated Txn Parity bit in the ARINC Control Register 2. This is useful to verify proper operation of the parity check circuitry for each of the receive circuits during wraparound test mode. When an error condition occurs, the ERROR output pin goes low to indicate the presence of an error. The error pin will go high again when the Error Status Register is clear. Each of these bits is cleared by either reading the Error Status Register or removing the error condition. PROCESSOR INTERFACE The processor interface allows for the use of either an 8- or 16-bit data bus. Intel or Motorola control signal formats can also be used. GENERAL PURPOSE INTERRUPTS INTERRUPT OPERATIONAL MODES The three general purpose interrupt outputs can be used for multilevel interrupts or to trigger other external hardware for various conditions. Each condition can be mapped to any one of the three general purpose interrupts or disabled (by mapping to IRQ0 which does not exist). Each interrupt output can be programmed to be either a LEVEL interrupt or PULSE interrupt via The DD-00429 provides four interrupt outputs. Three of these interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose programmable interrupts. The fourth interrupt is an Error interrupt output which is specifically used to provide indications of various error conditions and is nonmaskable. TABLE 3. DD-00429VP (144-PIN TQFP) ASIC PINOUTS PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DESCRIPTION +5V D11 D12 D13 D14 D15 EN RX1 EN RX0 SELECT RX RDY1 RX RDY0 GND POL SEL A1 POL SEL A0 INT/ MOT 8/16 +5V GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CS0 CS1 CS2 BIST R3 (N/C) GND +5V GND PIN NO. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DESCRIPTION PIN NO. +5V XTAL1 (N/C) XTAL2 TSB2 (N/C) TSB3 (N/C) TSA0 (N/C) TSA1 (N/C) TSA2 (N/C) TSA3 (N/C) TMA0 (N/C) TMA1 (N/C) TMA2 (N/C) TMA3 (N/C) TMA4 (N/C) TMA5 (N/C) TMA6 (N/C) TMA7 (N/C) TSB0 (N/C) TSB1 (N/C) +5V GND TMB4 (N/C) TMB5 (N/C) TMB6 (N/C) TMB7 (N/C) ZERO WAIT MODE READY RD or DS WR or RD/WR DTACK ERROR MASTER RESET +5V BIST TOA (N/C) BIST TOB (N/C) GND 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 4 DESCRIPTION +5V OSC CLK OUT BIST DMT (N/C) BIST RAM 7 (N/C) BIST RAM 24 (N/C) D0 D1 D2 D3 D4 D5 D6 D7 GND +5V GND +5V D8 D9 D10 D11 D12 D13 D14 D15 (GND) (GND) IRQ3 IRQ2 IRQ1 RESET RC ARINC CLK OUT ARINC CLK 1 ARINC CLK 0 BIST R2 (N/C) GND PIN NO. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 DESCRIPTION +5V RESET 1 CW STRB1 EN TX1 OUT TX1 EMPTY LD TX1 HI LD TX1 LOW +5V GND +5V CHIP CLK EN RX3 EN RX2 RX RDY3 RX RDY2 +5V GND RESET 0 CW STRB 0 EN TX0 OUT TX0 EMPTY LD TX0 HI LD TX0 LOW GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 GND Zero Wait Mode Operation: When Zero Wait Mode is enabled by not grounding the ZERO WAIT pin, the host microprocessor may read data from the DD-00429 shared memory resources (DMT and Rx RAM) without using the READY or DTACK signals to insert wait states into the microprocessor cycle. This is accomplished by an additional “dummy read” of the desired address. This dummy read causes the DD-00429 to fetch the data from the source and place it in a latch. The data can then be read from the latch (word-by-word or byte-by-byte) by reading the same addresses. Thus for a 32-bit read in 8-bit mode, the microprocessor would perform a total of five read operations. The first read would be the dummy read; subsequent reads would transfer the data. IRQ Control Register 2. When programmed for pulse interrupt mode, the associated interrupt pin will go low for 1 µS and return high again. When programmed for LEVEL interrupt mode, the interrupt will remain until the associated IRQ Status Register is read, thus clearing the associated bits in each interrupt register. Each of the individual interrupt registers can be masked by setting their corresponding bit in IRQ Control Register 1. It should be noted that the masking function only prevents the associated IRQ pin from becoming active. When the mask bit is cleared, an interrupt can occur in LEVEL IRQ mode if one or more interrupt conditions occurred during the time when the mask was set. If the user needs to ensure the interrupt will not occur upon clearing the mask bit, the CPU should be programmed to read the associated interrupt status register immediately prior to clearing the IRQ mask bit. TABLE 4. DD-00429FP (160-PIN PQFP) ASIC PINOUTS PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DESCRIPTION +5V D11 D12 D13 D14 D15 EN RX1 EN RX0 SELECT RX RDY1 RX RDY0 GND POL SEL A1 POL SEL A0 INT/ MOT 8/16 +5V TX0 A TX0 B TX1 A TX1 B GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CS0 CS1 CS2 BIST R3 (N/C) GND +5V GND PIN NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DESCRIPTION PIN NO. +5V XTAL1 (N/C) XTAL2 TSB2 (N/C) TSB3 (N/C) TSA0 (N/C) TSA1 (N/C) TSA2 (N/C) TSA3 (N/C) TMA0 (N/C) TMA1 (N/C) TMA2 (N/C) TMA3 (N/C) TMA4 (N/C) TMA5 (N/C) TMA6 (N/C) TMA7 (N/C) TSB0 (N/C) TSB1 (N/C) +5V GND TMB0 (N/C) TMB1 (N/C) TMB2 (N/C) TMB3 (N/C) TMB4 (N/C) TMB5 (N/C) TMB6 (N/C) TMB7 (N/C) ZERO WAIT MODE READY RD or DS WR or RD/ WR DTACK ERROR MASTER RESET +5V BIST TOA (N/C) BIST TOB (N/C) GND 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 5 DESCRIPTION +5V OSC CLK OUT BIST T1A (N/C) BIST T1B (N/C) BIST DMT (N/C) BIST RAM7 (N/C) BIST RAM24 (N/C) D0 D1 D2 D3 D4 D5 D6 D7 GND +5V GND +5V D8 D9 D10 D11 D12 D13 D14 D15 (GND) (GND) IRQ3 1RQ2 1RQ1 RESET RC ARINC CLK OUT ARINC CLK 1 ARINC CLK 0 BIST R0 (N/C) BIST R1 (N/C) BIST R2 (N/C) GND PIN NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 DESCRIPTION +5V RESET 1 CW STRB1 EN TX1 OUT TX1 B IN TX1 A IN TX1 EMPTY LD TX1 H1 LD TX1 LOW +5V GND +5V CHIP CLK EN RX3 EN RX2 RX RDY 3 RX RDY 2 +5V GND RESET 0 CW STRB0 EN TX0 OUT TX0B IN TX0A IN TX0 EMPTY LOAD TX0 HI LD TX0 LOW GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 GND .866 ±0.004 (22.00 ±0.1) .787 ±0.004 (20.00 ±0.1) .866 ±0.004 (22.00 ±0.1) +0.02 DD-00429VP .008 –0.01 (0.22 ±0.05) .787 ±0.004 (20.00 ±0.1) .0197 (0.50) PIN 1 .055 ±0.002 (1.40 ±0.05) .059 ±0.004 (1.50 ±0.1) .024 ±0.006 (0.60 ±0.15) .004 ±0.002 (0.1 ±0.05) DIMENSIONS IN INCHES (MILLIMETERS). FIGURE 2. DD-00429VP MECHANICAL OUTLINE (144-PIN TQFP) 1.102 ±0.004 (27.99 ±0.1 ) 39 EQ. SP. @ 0.0256 = 0.998 (0.65 = 25.36) (TOL. NONCUM) PIN NO. 1 INDEX PIN NUMBERS FOR REF. ONLY 1 121 160 120 1 39 EQ. SP. @ 0.0256 = 0.998 (0.65 = 25.36) (TOL. NONCUM) 1.102 ±0.004 (27.99 ±0.1 ) DD-00429FP 1 0.012 ±0.003 (0.3 ±0.08 ) (TYP) 0.0256 (.65) (TYP) 40 81 41 80 SEE DETAIL "A" DETAIL "A" NTS 0.146 +0.008 (3.71) -0.000 0.133 (3.38) (REF) 0.013 +0.000 (0.33) -0.003 0.016 (0.41) (MIN) (TYP) 0.007 ±0.002 (0.18) (TYP) 0.077(1.96) (TYP) 1.256 ±0.01 (31.9) (TYP) 0.031(.79) (TYP) Notes: 1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN ±0.010 (±0.25). 2. DIMENSIONS IN INCHES (MILLIMETERS). FIGURE 3. DD-00429FP ASIC MECHANICAL OUTLINE (160-PIN PQFP) 6 ORDERING INFORMATION Chip Set: DD-00429XP - X00 Temperature Range: 2 = -40 - +85°C 9 = -55 - +85°C (FP Package only) ASIC Package Type: P = Plastic Lead Type: F = Quad Flat Pack V = 144-Pin TQFP Note: The DD-03182 AND DD-03282 are required to complete the ARINC 429 Interface (see additional ordering information). The DD-00429 is only the Microprocessor Interface/RAM/FIFO and Interrupt Controller. ADDITIONAL ORDERING INFORMATION DD-03282XX-XX0 – ARINC 429 Transceiver DD-03182XX-XXX – ARINC 429 Line Driver Options: 0 = With resistors and fuses 1 = With resistors, no fuses* Screening: 0 = Standard DDC Procedures 2 = Burn-in Temperature Range: 1 = -55 to +125°C (ceramic only) 2 = -40 to +85°C 9 = -55 to +85°C (GP package only) Package Style/Type: DC = 16-pin ceramic DIP GP = 16-pin plastic SOIC PP = 28-pin plastic PLCC VP = 14-Pin plastic SOIC Screening: 0 = Standard DDC Procedures 2 = Burn-in (DC package only) Temperature Range: 1 = -55 to +125° C (DC package only) 2 = -40 to +85° C 9 = -55 to +85°C (GP package only) ASIC Package Style/Type: DC = 40-pin ceramic DIP PP = 44-pin plastic PLCC GP = 44-pin plastic PQFP *VP version only. 7 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7402 Headquarters - Tel: (631) 567-5600 ext. 7402, Fax: (631) 567-7358 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089 Sweden - Tel: +46-(0)8-54490044, Fax +46-(0)8-7550570 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com RM ® I FI REG U ST ERED DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 C-04/00-0 PRINTED IN THE U.S.A. 8