HP HCPL-3120

H
2.0 Amp Output Current IGBT
Gate Drive Optocoupler
Technical Data
HCPL-3120
Features
• 2.0 A Minimum Peak Output
Current
• 15 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1500 V
• 0.5 V Maximum Low Level
Output Voltage (VOL)
Eliminates Need for
Negative Gate Drive
• ICC = 5 mA Maximum Supply
Current
• Under Voltage Lock-Out
Protection (UVLO) with
Hysteresis
• Wide Operating VCC Range:
15 to 30 Volts
• 500 ns Maximum Switching
Speeds
• Industrial Temperature
Range: -40°C to 100°C
• Safety Approval
UL Recognized - 2500 V rms
for 1 minute per UL1577
CSA Approval
VDE 0884 Approved with
VIORM = 630 V peak
(Option 060 only)
• Industrial Inverters
• Switch Mode Power Supplies
(SMPS)
Description
The HCPL-3120 consists of a
GaAsP LED optically coupled to
an integrated circuit with a power
output stage. This optocoupler is
ideally suited for driving power
IGBTs and MOSFETs used in
Functional Diagram
N/C
1
8
VCC
ANODE
2
7
VO
CATHODE
3
6
VO
N/C
4
5
VEE
• Isolated IGBT/MOSFET
Gate Drive
• AC and Brushless DC Motor
Drives
SHIELD
TRUTH TABLE
LED
Applications
motor control inverter applications. The high operating voltage
range of the output stage provides the drive voltages required
by gate controlled devices. The
voltage and current supplied by
this optocoupler makes it ideally
suited for directly driving IGBTs
with ratings up to 1200 V/100 A.
For IGBTs with higher ratings,
the HCPL-3120 can be used to
drive a discrete power stage
which drives the IGBT gate.
VCC - VEE
VCC - VEE
“POSITIVE GOING” “NEGATIVE GOING”
(i.e., TURN-ON)
(i.e., TURN-OFF)
VO
OFF
0 - 30 V
0 - 30 V
LOW
ON
0 - 11 V
0 - 9.5 V
LOW
ON
11 - 13.5 V
9.5 - 12 V
TRANSITION
ON
13.5 - 30 V
12 - 30 V
HIGH
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.
1-182
5965-4779E
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-3120#XXX
No Option = Standard DIP Package, 50 per tube.
060 = VDE 0884 VIORM = 630 V peak Option, 50 per tube.
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.
Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.
9.40 (0.370)
9.90 (0.390)
Package Outline Drawings
Standard DIP Package
8
7
6
5
OPTION CODE*
HP 3120Z
DATE CODE
YYWW
PIN ONE
1
2
3
0.20 (0.008)
0.33 (0.013)
6.10 (0.240)
6.60 (0.260)
7.36 (0.290)
7.88 (0.310)
5° TYP.
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
4.70 (0.185) MAX.
PIN ONE
0.51 (0.020) MIN.
2.92 (0.115) MIN.
0.76 (0.030)
1.40 (0.055)
DIMENSIONS IN MILLIMETERS AND (INCHES).
PIN DIAGRAM
*MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION
060 V
1 VDD1
DD2 8
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
2.28 (0.090)
2.80 (0.110)
2
VIN+
VOUT+ 7
3
VIN–
VOUT– 6
4
GND1 GND2 5
Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
1.194 (0.047)
5
4.826 TYP.
(0.190)
HP 3120Z
6.350 ± 0.25
(0.250 ± 0.010)
YYWW
1
MOLDED
2
3
9.398 (0.370)
9.906 (0.390)
4
1.194 (0.047)
1.778 (0.070)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
4.19 MAX.
(0.165)
1.080 ± 0.320
(0.043 ± 0.013)
2.540
(0.100)
BSC
0.381 (0.015)
0.635 (0.025)
0.635 ± 0.130
(0.025 ± 0.005)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
1-183
TEMPERATURE – °C
Reflow Temperature Profile
260
240
220
200
180
160
The HCPL-3120 has been
approved by the following
organizations:
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
Regulatory Information
0
1
2
3
4
5
6
7
8
9
10
11
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
12
TIME – MINUTES
VDE (Option 060 Only)
Approved under VDE 0884/06.92
with VIORM = 630 V peak.
MAXIMUM SOLDER REFLOW THERMAL PROFILE
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
VDE 0884 Insulation Characteristics (Option 060 Only)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge <5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec,
Partial discharge <5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage tini = 10 sec)
Safety Limiting Values–Maximum Values Allowed in the Event
of a Failure, Also See Figure 37, Thermal Derating Curve.
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Unit
VIORM
I-IV
I-III
55/100/21
2
630
Vpeak
VPR
1181
Vpeak
VPR
945
Vpeak
VIOTM
6000
Vpeak
TS
IS, INPUT
PS, OUTPUT
RS
175
230
600
≥ 109
°C
mA
mW
Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884) for a
detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-184
Insulation and Safety Related Specifications
Parameter
Symbol Value Units
Conditions
Minimum External Air
L(101)
7.1
mm
Measured from input terminals to output terminals,
Gap (External
shortest distance through air.
Clearance)
Minimum External
L(102)
7.4
mm
Measured from input terminals to output terminals,
Tracking (External
shortest distance path along body.
Creepage)
Minimum Internal Plastic
0.08
mm
Insulation thickness between emitter and detector;
Gap (Internal Clearance)
also known as distance through insulation.
Tracking Resistance
CTI
200
Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current
Peak Transient Input Current
(<1 µs pulse width, 300 pps)
Reverse Input Voltage
“High” Peak Output Current
“Low” Peak Output Current
Supply Voltage
Output Voltage
Output Power Dissipation
Total Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
TS
TA
IF(AVG)
IF(TRAN)
VR
IOH(PEAK)
IOL(PEAK)
(VCC - VEE)
VO
PO
PT
Min.
-55.
-40
Max.
125
100
25
Units
°C
°C
mA
Note
1.0
A
5
Volts
2.5
A
2.5
A
0
35
Volts
0
VCC
Volts
250
mW
295
mW
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings section
1
2
2
3
4
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
Symbol
(VCC - VEE)
IF(ON)
VF(OFF)
TA
Min.
15
7
-3.0
-40
Max.
30
16
0.8
100
Units
Volts
mA
V
°C
1-185
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter
High Level
Output Current
Symbol
IOH
Low Level
Output Current
IOL
High Level Output
VOH
Voltage
Low Level Output
VOL
Voltage
High Level Supply
ICCH
Current
Low Level Supply
ICCL
Current
Threshold Input
IFLH
Current Low to High
Threshold Input
Voltage High to Low
VFHL
Input Forward
VF
Voltage
Temperature
∆VF /∆TA
Coefficient
of Forward Voltage
Input Reverse
BVR
Breakdown Voltage
Input Capacitance
CIN
UVLO Threshold
VUVLO+
VUVLO–
UVLO Hysteresis
UVLOHYS
Min.
Typ.* Max. Units
0.5
1.5
A
2.0
A
0.5
2.0
A
2.0
A
(VCC - 4) (VCC - 3)
V
0.8
1.2
0.1
0.5
V
2.0
5.0
mA
2.0
5.0
mA
2.3
5.0
mA
1.8
V
V
1.5
-1.6
11.0
9.5
13.5
12.0
* All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
1-186
IO = 100 mA
Output Open,
IF = 7 to 16 mA
Output Open,
VF = -3.0 to +0.8 V
IO = 0 mA,
VO > 5 V
IF = 10 mA
Fig.
2, 3,
17
5, 6,
18
1, 3,
19
4, 6,
20
7, 8
9, 15,
21
16
mV/°C IF = 10 mA
5
60
12.3
10.7
1.6
Test Conditions
VO = (VCC - 4 V)
VO = (VCC - 15 V)
VO = (VEE + 2.5 V)
VO = (VEE + 15V)
IO = -100 mA
V
Ir = 10 µA
pF
V
f = 1 MHz, VF = 0 V
VO > 5 V, IF = 10 mA
22, 36
Note
5
2
5
2
6, 7
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter
Symbol
Min.
Propagation Delay
tPLH
0.10
Time to High
Output Level
Propagation Delay
tPHL
0.10
Time to Low
Output Level
Pulse Width
PWD
Distortion
Propagation Delay (tPHL - tPLH) -0.35
Difference Between
PDD
Any Two Parts
Rise Time
tr
Fall Time
tf
UVLO Turn On
tUVLO ON
Delay
UVLO Turn Off
tUVLO OFF
Delay
Output High Level
|CMH|
15
Common Mode
Transient
Immunity
Output Low Level
|CML|
15
Common Mode
Transient
Immunity
Typ.*
0.30
Max.
0.50
Units
µs
0.27
0.50
µs
0.3
µs
0.35
µs
34,35
µs
µs
µs
23
0.1
0.1
0.8
Test Conditions
Rg = 10 Ω,
Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%
Fig.
10, 11,
12, 13
14, 23
Note
14
15
10
22
VO > 5 V, IF = 10 mA
VO < 5 V, IF = 10 mA
0.6
30
kV/µs
30
kV/µs
TA = 25°C,
IF = 10 to 16 mA,
VCM = 1500 V,
VCC = 30 V
TA = 25°C,
VCM = 1500 V,
VF = 0 V,
VCC = 30 V
24
Fig.
11, 12
11, 13
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Package Characteristics
Parameter
Symbol
Input-Output
VISO
Momentary
Withstand Voltage**
Resistance
RI-O
(Input - Output)
Capacitance
CI-O
(Input - Output)
LED-to-Case
θLC
Thermal Resistance
LED-to-Detector
θLD
Thermal Resistance
Detector-to-Case
θDC
Thermal Resistance
Min.
2500
Typ.
Max.
Units
VRMS
1012
Ω
Test Conditions
RH < 50%,
t = 1 min.,
TA = 25°C
VI-O = 500 VDC
0.6
pF
f = 1 MHz
467
°C/W
442
°C/W
126
°C/W
Thermocoupler
located at center
underside of
package
Note
8, 9
9
28
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note
1074 entitled “Optocoupler Input-Output Endurance Voltage.”
1-187
0
-2
-3
-4
-40 -20
0
20
40
60
80
100
1.6
1.4
1.2
1.0
-40 -20
TA – TEMPERATURE – °C
IOL – OUTPUT LOW CURRENT – A
0.15
0.10
0.05
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 4. VOL vs. Temperature.
1-188
40
60
80
100
100
3
-1
100 °C
25 °C
-40 °C
-2
-3
-4
IF = 7 to 16 mA
VCC = 15 to 30 V
VEE = 0 V
-5
-6
0
0.5
1.0
1.5
2.0
2.5
IOH – OUTPUT HIGH CURRENT – A
Figure 3. VOH vs. IOH.
4
4
VF(OFF) = -3.0 to 0.8 V
IOUT = 100 mA
VCC = 15 to 30 V
VEE = 0 V
0
-40 -20
20
Figure 2. IOH vs. Temperature.
0.25
0.20
0
TA – TEMPERATURE – °C
Figure 1. VOH vs. Temperature.
VOL – OUTPUT LOW VOLTAGE – V
1.8
IF = 7 to 16 mA
VOUT = (VCC - 4 V)
VCC = 15 to 30 V
VEE = 0 V
VF(OFF) = -3.0 to 0.8 V
VOUT = 2.5 V
VCC = 15 to 30 V
VEE = 0 V
VOL – OUTPUT LOW VOLTAGE – V
-1
2.0
IF = 7 to 16 mA
IOUT = -100 mA
VCC = 15 to 30 V
VEE = 0 V
10. The difference between tPHL and tPLH
between any two HCPL-3120 parts
under the same test condition.
11. Pins 1 and 4 need to be connected to
LED common.
12. Common mode transient immunity in
the high state is the maximum
tolerable dVCM /dt of the common
mode pulse, VCM, to assure that the
output will remain in the high state
(i.e., VO > 15.0 V).
13. Common mode transient immunity in
a low state is the maximum tolerable
dVCM/dt of the common mode pulse,
VCM, to assure that the output will
remain in a low state (i.e., VO < 1.0 V).
14. This load condition approximates the
gate load of a 1200V/75A IGBT.
15. Pulse Width Distortion (PWD) is
defined as |tPHL-tPLH| for any given
device.
(VOH – VCC ) – OUTPUT HIGH VOLTAGE DROP – V
loads VOH will approach VCC as IOH
approaches zero amps.
7. Maximum pulse width = 1 ms,
maximum duty cycle = 20%.
8. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Characteristic
Table, if applicable.
9. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
IOH – OUTPUT HIGH CURRENT – A
(VOH – VCC ) – HIGH OUTPUT VOLTAGE DROP – V
Notes:
1. Derate linearly above 70°C free-air
temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for
component tolerances for designs
with IO peak minimum = 2.0 A. See
Applications section for additional
details on limiting IOH peak.
3. Derate linearly above 70°C free-air
temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air
temperature at a rate of 5.4 mW/°C.
The maximum LED junction temperature should not exceed 125°C.
5. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc
load current. When driving capacitive
2
1
0
-40 -20
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 5. IOL vs. Temperature.
100
VF(OFF) = -3.0 to 0.8 V
VCC = 15 to 30 V
VEE = 0 V
3
2
1
0
100 °C
25 °C
-40 °C
0
0.5
1.0
1.5
2.0
IOL – OUTPUT LOW CURRENT – A
Figure 6. VOL vs. IOL.
2.5
ICC – SUPPLY CURRENT – mA
3.0
2.5
VCC = 30 V
VEE = 0 V
IF = 10 mA for ICCH
IF = 0 mA for ICCL
2.0
1.5
-40 -20
0
20
40
60
80
ICCH
ICCL
3.0
2.5
2.0
1.5
100
IF = 10 mA for ICCH
IF = 0 mA for ICCL
TA = 25 °C
VEE = 0 V
15
VCC – SUPPLY VOLTAGE – V
TA – TEMPERATURE – °C
Figure 7. ICC vs. Temperature.
Figure 8. ICC vs. VCC.
300
200
400
300
200
TPLH
TPHL
100
15
30
25
20
Figure 10. Propagation Delay vs. VCC.
8
10
12
14
300
200
TPLH
TPHL
0
10
20
30
40
3
2
1
0
-40 -20
50
Rg – SERIES LOAD RESISTANCE – Ω
Figure 13. Propagation Delay vs. Rg.
20
40
60
80
100
400
IF = 10 mA
VCC = 30 V, VEE = 0 V
Rg = 10 Ω, Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
300
200
TPLH
TPHL
0
20
40
60
80
100
TA – TEMPERATURE – °C
Figure 12. Propagation Delay vs.
Temperature.
30
VCC = 30 V, VEE = 0 V
TA = 25 °C
IF = 10 mA
Rg = 10 Ω
DUTY CYCLE = 50%
f = 10 kHz
400
300
200
TPLH
TPHL
100
0
TA – TEMPERATURE – °C
100
-40 -20
16
500
VCC = 30 V, VEE = 0 V
TA = 25 °C
IF = 10 mA
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
Tp – PROPAGATION DELAY – ns
Tp – PROPAGATION DELAY – ns
6
Figure 11. Propagation Delay vs. IF.
500
100
4
IF – FORWARD LED CURRENT – mA
VCC – SUPPLY VOLTAGE – V
400
VCC = 15 TO 30 V
VEE = 0 V
OUTPUT = OPEN
500
VCC = 30 V, VEE = 0 V
Rg = 10 Ω, Cg = 10 nF
TA = 25 °C
DUTY CYCLE = 50%
f = 10 kHz
Tp – PROPAGATION DELAY – ns
400
TPLH
TPHL
Tp – PROPAGATION DELAY – ns
Tp – PROPAGATION DELAY – ns
IF = 10 mA
TA = 25 °C
Rg = 10 W
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
5
Figure 9. IFLH vs. Temperature.
500
500
100
30
25
20
VO – OUTPUT VOLTAGE – V
ICC – SUPPLY CURRENT – mA
ICCH
ICCL
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
3.5
3.5
0
20
40
60
80
100
Cg – LOAD CAPACITANCE – nF
Figure 14. Propagation Delay vs. Cg.
25
20
15
10
5
0
0
1
2
3
4
5
IF – FORWARD LED CURRENT – mA
Figure 15. Transfer Characteristics.
1-189
IF – FORWARD CURRENT – mA
1000
TA = 25°C
100
IF
1
+
VF
–
10
8
0.1 µF
1.0
2
+
–
7
4V
IF = 7 to
16 mA
0.1
+ VCC = 15
– to 30 V
3
6
0.01
IOH
0.001
1.10
1.20
1.30
1.40
1.50
4
1.60
5
VF – FORWARD VOLTAGE – VOLTS
Figure 16. Input Current vs. Forward
Voltage.
1
Figure 17. IOH Test Circuit.
8
0.1 µF
2
6
8
2
7
0.1 µF
IOL
7
3
1
+ VCC = 15
– to 30 V
VOH
IF = 7 to
16 mA
2.5 V +
–
+ VCC = 15
– to 30 V
3
6
100 mA
4
4
5
Figure 19. VOH Test Circuit.
Figure 18. IOL Test Circuit.
1
8
2
7
0.1 µF
3
6
4
5
8
2
7
0.1 µF
IF
VOL
VO > 5 V
3
6
4
5
Figure 21. IFLH Test Circuit.
Figure 20. VOL Test Circuit.
1
8
2
7
0.1 µF
IF = 10 mA
VO > 5 V
3
6
4
5
Figure 22. UVLO Test Circuit.
1
100 mA
+ VCC = 15
– to 30 V
1-190
5
+
–
VCC
+ VCC = 15
– to 30 V
1
8
0.1 µF
IF = 7 to 16 mA
+
10 KHz –
500 Ω
2
7
IF
VCC = 15
+ to
30 V
–
tr
tf
VO
50% DUTY
CYCLE
3
90%
10 Ω
6
50%
VOUT
10 nF
4
10%
5
tPLH
tPHL
Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
VCM
1
5V
δt
0.1 µF
A
B
δV
8
IF
2
+
–
VO
6
4
5
VCM
∆t
0V
7
3
=
∆t
+
–
VCC = 30 V
VOH
VO
SWITCH AT A: IF = 10 mA
VO
VOL
–
SWITCH AT B: IF = 0 mA
+
VCM = 1500 V
Figure 24. CMR Test Circuit and Waveforms.
Applications Information
Eliminating Negative IGBT
Gate Drive
To keep the IGBT firmly off, the
HCPL-3120 has a very low
maximum VOL specification of
0.5 V. The HCPL-3120 realizes
this very low VOL by using a
DMOS transistor with 1 Ω
(typical) on resistance in its pull
down circuit. When the HCPL3120 is in the low state, the IGBT
gate is shorted to the emitter by
Rg + 1 Ω. Minimizing Rg and the
lead inductance from the HCPL3120 to the IGBT gate and
emitter (possibly by mounting the
HCPL-3120 on a small PC board
directly above the IGBT) can
eliminate the need for negative
IGBT gate drive in many applications as shown in Figure 25. Care
should be taken with such a PC
board design to avoid routing the
IGBT collector or emitter traces
close to the HCPL-3120 input as
this can result in unwanted
coupling of transient signals into
the HCPL-3120 and degrade
performance. (If the IGBT drain
must be routed near the HCPL3120 input, then the LED should
be reverse-biased when in the off
state, to prevent the transient
signals coupled from the IGBT
drain from turning on the
HCPL-3120.)
HCPL-3120
+5 V
1
270 Ω
8
0.1 µF
2
+
–
VCC = 18 V
+ HVDC
7
Rg
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
3
6
4
5
Q1
3-PHASE
AC
Q2
- HVDC
Figure 25. Recommended LED Drive and Application Circuit.
1-191
Selecting the Gate Resistor
(Rg) to Minimize IGBT
Switching Losses.
Step 1: Calculate Rg Minimum
from the IOL Peak Specification. The IGBT and Rg in Figure
26 can be analyzed as a simple
RC circuit with a voltage supplied
by the HCPL-3120.
(VCC – VEE - VOL)
Rg ≥ –––––––––––––––
IOLPEAK
(VCC – VEE - 2 V)
= –––––––––––––––
IOLPEAK
The VOL value of 2 V in the previous equation is a conservative
value of VOL at the peak current
of 2.5A (see Figure 6). At lower
Rg values the voltage supplied by
the HCPL-3120 is not an ideal
voltage step. This results in lower
peak currents (more margin)
than predicted by this analysis.
When negative gate drive is not
used VEE in the previous equation
is equal to zero volts.
Step 2: Check the HCPL-3120
Power Dissipation and
Increase Rg if Necessary. The
HCPL-3120 total power dissipation (PT) is equal to the sum of
the emitter power (PE) and the
output power (PO):
(15 V + 5 V - 2 V)
= ––––––––––––––––––
2.5 A
= 7.2 Ω ≅ 8 Ω
PT = P E + P O
PE = IF • VF • Duty Cycle
PO = PO(BIAS) + PO (SWITCHING)
= ICC• (VCC - VEE)
+ ESW(RG, QG) • f
For the circuit in Figure 26 with IF
(worst case) = 16 mA, Rg = 8 Ω,
Max Duty Cycle = 80%, Qg = 500
nC, f = 20 kHz and TA max = 85C:
PE = 16 mA • 1.8 V • 0.8 = 23 mW
PO = 4.25 mA • 20 V
+ 5.2 µJ• 20 kHz
= 85 mW + 104 mW
= 189 mW
> 178 mW (PO(MAX) @ 85C
= 250 mW−15C*4.8 mW/C)
HCPL-3120
+5 V
1
270 Ω
8
0.1 µF
2
+
–
VCC = 15 V
+ HVDC
7
Rg
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
Q1
3
6
–
+
4
VEE = -5 V
3-PHASE
AC
5
Q2
- HVDC
Figure 26. HCPL-3120 Typical Application Circuit with Negative IGBT Gate Drive.
PE
Parameter
IF
VF
Duty Cycle
Description
LED Current
LED On Voltage
Maximum LED
Duty Cycle
PO Parameter
ICC
VCC
VEE
ESW(Rg,Qg)
f
1-192
Description
Supply Current
Positive Supply Voltage
Negative Supply Voltage
Energy Dissipated in the HCPL-3120 for each
IGBT Switching Cycle (See Figure 27)
Switching Frequency
shown in Figure 29. The HCPL3120 improves CMR performance
by using a detector IC with an
optically transparent Faraday
shield, which diverts the capacitively coupled current away from
TJE = PE • (θLC||(θLD + θDC) + θCA)
the sensitive IC circuitry. How
Since PO for this case is greater
θLC * θDC
+ PD • ––––––––––––––––
+ θCA + TA ever, this shield does not
than PO(MAX), Rg must be
θLC + θDC + θLD
eliminate the capacitive coupling
increased to reduce the HCPLbetween the LED and optocoup3120 power dissipation.
•
θLC θDC
TJD = PE –––––––––––––––
+ θCA
ler pins 5-8 as shown in
θLC + θDC + θLD
Figure 30. This capacitive
PO(SWITCHING MAX)
coupling causes perturbations in
= PO(MAX) - PO(BIAS)
+ PD• (θDC||(θLD + θLC) + θCA) + TA
the LED current during common
= 178 mW - 85 mW
mode transients and becomes the
= 93 mW
Inserting the values for θLC and
major source of CMR failures for
PO(SWITCHINGMAX)
ESW(MAX) = –––––––––––––––
θDC shown in Figure 28 gives:
a shielded optocoupler. The main
f
design objective of a high CMR
93 mW
TJE = PE • (256°C/W + θCA)
LED drive circuit becomes
= ––––––– = 4.65 µW
+ PD• (57°C/W + θCA) + TA
keeping the LED in the proper
20 kHz
TJD = PE • (57°C/W + θCA)
state (on or off) during common
+ PD• (111°C/W + θCA) + TA
mode transients. For example,
For Qg = 500 nC, from Figure
the recommended application
27, a value of ESW = 4.65 µW
For example, given PE = 45 mW,
circuit (Figure 25), can achieve
gives a Rg = 10.3 Ω.
PO = 250 mW, TA = 70°C and θCA
15 kV/µs CMR while minimizing
= 83°C/W:
component complexity.
Thermal Model
The steady state thermal model
TJE = PE• 339°C/W + PD• 140°C/W + TA Techniques to keep the LED in
for the HCPL-3120 is shown in
= 45 mW• 339°C/W + 250 mW
the proper state are discussed in
Figure 28. The thermal resistance
• 140°C/W + 70°C = 120°C
the next two sections.
values given in this model can be
used to calculate the temperaTJD = PE• 140°C/W + PD• 194°C/W + TA
tures at each node for a given
= 45 mW• 140C/W + 250 mW
operating condition. As shown by
• 194°C/W + 70°C = 125°C
the model, all heat generated
14
flows through θCA which raises
Qg = 100 nC
the case temperature TC
12
Qg = 500 nC
TJE and TJD should be limited to
Qg = 1000 nC
accordingly. The value of θCA
125C based on the board layout
10
depends on the conditions of the
and part placement (θCA) specific
VCC = 19 V
VEE = -9 V
8
board design and is, therefore,
to the application.
determined by the designer. The
6
value of θCA = 83°C/W was
LED Drive Circuit
4
obtained from thermal measureConsiderations for Ultra
ments using a 2.5 x 2.5 inch PC
2
High CMR Performance.
board, with small traces (no
Without a detector shield, the
0
10
20
30
40
50
0
ground plane), a single HCPLdominant cause of optocoupler
Rg – GATE RESISTANCE – Ω
3120 soldered into the center of
CMR failure is capacitive
the board and still air. The
coupling from the input side of
Figure 27. Energy Dissipated in the
absolute maximum power
the optocoupler, through the
HCPL-3120 for Each IGBT Switching
dissipation derating specifications
package, to the detector IC as
Cycle.
assume a θCAvalue of 83°C/W.
From the thermal mode in Figure
28 the LED and detector IC
junction temperatures can be
expressed as:
(
)
(
)
Esw – ENERGY PER SWITCHING CYCLE – µJ
The value of 4.25 mA for ICC in
the previous equation was
obtained by derating the ICC max
of 5 mA (which occurs at -40°C)
to ICC max at 85C (see Figure 7).
1-193
θLD = 442 °C/W
TJE
TJD
θLC = 467 °C/W
θDC = 126 °C/W
TC
θCA = 83 °C/W*
TA
TJE = LED junction temperature
TJD = detector IC junction temperature
TC = case temperature measured at the center of the package bottom
θLC = LED-to-case thermal resistance
θLD = LED-to-detector thermal resistance
θDC = detector-to-case thermal resistance
θCA = case-to-ambient thermal resistance
∗θCA will depend on the board design and the placement of the part.
Figure 28. Thermal Model.
CMR with the LED On
(CMRH).
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED current of 10 mA provides adequate
margin over the maximum IFLH of
5 mA to achieve 15 kV/µs CMR.
CMR with the LED Off
(CMRL).
A high CMR LED drive circuit
must keep the LED off (VF ≤
VF(OFF)) during common mode
transients. For example, during a
-dVcm/dt transient in Figure 31,
the current flowing through CLEDP
also flows through the RSAT and
VSAT of the logic gate. As long as
the low state voltage developed
across the logic gate is less than
VF(OFF), the LED will remain off
and no common mode failure will
occur.
1-194
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dVcm/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMRL
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
coupler output will go into the
low state with a typical delay,
UVLO Turn Off Delay, of 0.6 µs.
When the HCPL-3120 output is in
the low state and the supply
voltage rises above the HCPL3120 VUVLO+ threshold (11.0 <
VUVLO+ < 13.5) the optocoupler
output will go into the high state
(assumes LED is “ON”) with a
typical delay, UVLO Turn On
Delay of 0.8 µs.
Under Voltage Lockout
Feature.
IPM Dead Time and
Propagation Delay
Specifications.
The HCPL-3120 contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3120
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3120
output is in the high state and the
supply voltage drops below the
HCPL-3120 VUVLO– threshold
(9.5 < VUVLO– < 12.0) the opto-
The HCPL-3120 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices between the
high and low voltage motor rails.
1
8
1
7
2
CLEDO1
8
CLEDP
CLEDP
2
7
CLEDO2
3
CLEDN
4
6
3
5
4
Figure 29. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers.
+5 V
Figure 30. Optocoupler Input to Output
Capacitance Model for Shielded Optocouplers.
0.1
µF
CLEDP
2
7
+
–
VCC = 18 V
1
ILEDP
3
5
SHIELD
8
1
+
VSAT
–
6
CLEDN
CLEDP
•••
6
CLEDN
4
8
+5 V
2
Rg
5
SHIELD
•••
3
Q1
7
6
CLEDN
ILEDN
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
4
5
SHIELD
+ –
VCM
Figure 31. Equivalent Circuit for Figure 25 During
Common Mode Transient.
8
1
+5 V
CLEDP
2
3
4
7
CLEDN
SHIELD
6
5
Figure 33. Recommended LED Drive
Circuit for Ultra-High CMR.
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the
turn off of LED1) so that under
worst-case conditions, transistor
Q1 has just turned off when
transistor Q2 turns on, as shown
in Figure 34. The amount of delay
necessary to achieve this conditions is equal to the maximum
value of the propagation delay
difference specification, PDDMAX,
Figure 32. Not Recommended Open
Collector Drive Circuit.
which is specified to be 350 ns
over the operating temperature
range of -40°C to 100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
1-195
maximum and minimum propagation delay difference specifications as shown in Figure 35. The
maximum dead time for the
HCPL-3120 is 700 ns (= 350 ns (-350 ns)) over an operating
temperature range of -40°C to
100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal temperatures and test conditions since
the optocouplers under consideration are typically mounted in
close proximity to each other and
are switching identical IGBTs.
14
VOUT1
Q1 ON
Q1 OFF
Q2 ON
VOUT2
ILED2
Q2 OFF
tPHL MAX
VO – OUTPUT VOLTAGE – V
ILED1
tPLH MIN
12
(12.3, 10.8)
10
(10.7, 9.2)
8
6
4
2
0
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
(10.7, 0.1)
5
0
10
(12.3, 0.1)
15
20
(VCC - VEE ) – SUPPLY VOLTAGE – V
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
ILED1
VOUT1
Q1 ON
Q1 OFF
Q2 ON
VOUT2
Q2 OFF
ILED2
tPHL MIN
tPHL MAX
tPLH
MIN
tPLH MAX
Figure 36. Under Voltage Lock Out.
OUTPUT POWER – PS, INPUT CURRENT – IS
Figure 34. Minimum LED Skew for Zero Dead Time.
800
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
(tPHL-tPLH) MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 35. Waveforms for Dead Time.
1-196
Figure 37. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per VDE 0884.