ACPL-P456 and ACPL-W456 Intelligent Power Module and Gate Drive Interface Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-P456 and ACPL-W456 contain a GaAsP LED optically coupled to an integrated high gain photo detector. Minimized propagation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. Specifications and performance plots are given for typical IPM applications. x Performance Specified for Common IPM Applications Over Industrial Temperature Range. x Short Maximum Propagation Delays x Minimized Pulse Width Distortion (PWD) x Very High Common Mode Rejection (CMR) x High CTR. x Available in Stretched SO-6 package with 8 mm creepage and clearance. x Safety Approval: UL Recognized with 3750 Vrms for 1 minute (5000 Vrms for 1 minute for ACPL-W456 devices) per UL1577. CSA Approved. IEC/EN/DIN EN 60747-5-5 Approved with VIORM = 1140 Vpeak (ACPL-W456) and VIORM = 891 Vpeak (ACPL-P456) for Option 060. Functional Diagram ANODE 1 6 VCC N.C. 2 5 VO CATHODE 3 SHIELD 4 Ground Note: A 0.1 μF bypass capacitor must be connected between pins 4 and 6. Truth Table LED VO ON LOW OFF HIGH Specifications x x x x Wide operating temperature range: –40°C to 100°C. Maximum propagation delay tPHL = 400 ns, tPLH = 490 ns Maximum Pulse Width Distortion (PWD) = 450 ns. 15 kV/μs minimum common mode rejection (CMR) at VCM = 1500 V. x CTR > 44% at IF = 10 mA Applications x x x x IPM Isolation Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information ACPL-P456 and ACPL-W456 are UL Recognized with 3750 Vrms (5000 Vrms for ACPL-W456) for 1 minute per UL1577 and are approved under CSA Component Acceptance Notice #5, File CA 88324. Option Part number RoHS Compliant Package Surface Mount -000E ACPL-P456 ACPL-W456 Tape & Reel IEC/EN/DIN EN 60747-5-5 X -500E X Stretched SO-6 -060E X X -560E X Quantity 100 per tube X 1000 per reel X 100 per tube X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-P456-560E to order product of Stretched SO-6 package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: ACPL-P456-000E to order product of Stretched SO-6 package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawings ACPL-P456 Stretched SO-6 Package, 7 mm clearance +0.254 0 +0.010 0.180 - 0.000 4.580 0.381 ±0.127 0.015 ±0.005 1.27 BSG 0.050 10.7 0.421 1.27 0.050 0.45 0.018 7.62 0.300 6.81 0.268 45° 7° 1.590 ±0.127 0.063 ±0.005 0.76 0.030 2.16 0.085 3.180 ±0.127 0.125 ±0.005 7° 7° 0.20 ±0.10 0.008 ±0.004 7° 5 NOM. 1±0.250 0.040 ±0.010 2 9.7 ±0.250 0.382 ±0.010 0.254 ±0.050 0.010 ±0.002 Floating Lead Protusions max. 0.25 [0.01] Dimensions in Millimeters [ Inches ] Lead Coplanarity= 0.1mm [0.004 Inches ] ACPL-W456 Stretched SO-6 Package, 8 mm clearance 1 0.760 0.030 12.650 0.498 6 2 5 3 4 7.62 [0.300] +0.127 0 +0.005 0.268 - 0.000 6.807 0.45 0.018 +0.254 0 +0.010 0.180 - 0.000 4.580 1.27 BSG 0.050 0.381 ±0.127 0.015 ±0.005 7° 45° 1.905 0.075 1.270 0.050 1.590 ±0.127 0.063 ±0.005 3.180 ±0.127 0.125 ±0.005 7° 0.20 ±0.10 0.008 ±0.004 7° 0.750 ±0.250 [0.0295 ±0.010] 0.254 ±0.050 0.010 ±0.002 7° 35° NOM. Floating Lead protusion max. 0.25[0.01] 11.500 ±0.25 0.453 ±0.010 Dimensions in millimeters [Inches] Lead Coplanarity=0.1mm [0.004 Inches] Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-P456 and ACPL-W456 are approved by the following organizations: IEC/EN/DIN EN 60747-5-5 (Option 060 only) UL Approved with Maximum Working Insulation Voltage VIORM = 1140 Vpeak (ACPL-W456) and VIORM = 891 Vpeak (ACPL-P456). Approval under UL 1577, component recognition program up to VISO = 3750 VRMS (or 5000 VRMS for ACPLW456). File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. 3 Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-P456/W456 Option 060) Description Symbol ACPL-W456 ACPL-P456 Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 450 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – IV I – III I – III I – II I – IV I – IV I – III I – III Climatic Classification 55/100/21 55/100/21 Pollution Degree (DIN VDE 0110/1.89) Unit 2 2 Maximum Working Insulation Voltage VIORM 1140 891 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 2138 1671 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.5=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 1824 1425 Vpeak VIOTM 8000 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 175 230 600 175 230 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS >109 >109 : Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-P456 ACPL-W456 Units Conditions Minimum External Air Gap (External Clearance) L(101) 7.0 8.0 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 8.0 8.0 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Minimum Internal Tracking (Internal Creepage) NA NA mm Measured from input terminals to output terminals, along internal cavity. >175 >175 V IIIa IIIa Tracking Resistance (Comparative Tracking Index) Isolation Group 4 CTI DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature TS -55 125 °C Operating Temperature TA -40 100 °C Average Input Current IF(avg) 25 mA 1 Peak Input Current (50% duty cycle, <1 ms pulse width) IF(peak) 50 mA 2 Peak Transient Input Current (<1 μs pulse width, 300 pps) IF(tran) 1.0 A Reverse Input Voltage (Pin 3-1) VR 5 V Average Output Current (Pin 5) IO(avg) 15 mA Output Voltage (Pin 5-4) VO -0.5 Supply Voltage (Pin 6-4) VCC -0.5 Output Power Dissipation PO 100 mW 3 Total Power Dissipation PT 145 mW 4 Infrared and Vapor Phase Reflow Temperature See Reflow Thermal Profile. 30 30 Table 4. Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage VCC 4.5 30 V Output Voltage VO 0 30 V Input Current (ON) IF(on) 10 20 mA Input Voltage (OFF) VF(off ) -5 0.8 V Operating Temperature TA -40 100 °C Note Table 5. Electrical Specifications Over recommended operating conditions unless otherwise specified: TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off ) = -5 V to 0.8 V Parameter Symbol Min. Typ.* Units Test Conditions Current Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V Low Level Output Current IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA Input Threshold Current ITH 1.5 5.0 mA VO = 0.8 V, IO = 0.75 mA 1 High Level Output Current IOH 5 50 μA VF = 0.8 V 3 High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 9 Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 9 Input Forward Voltage VF 1.5 1.8 V IF = 10 mA Temperature Coefficient of Forward Voltage ΔVF/ΔTA -1.6 mV/°C IF = 10 mA Input Reverse Breakdown Voltage BVR V IR = 10 μA Input Capacitance CIN pF f = 1 MHz, VF = 0 V *All typical values at 25°C, VCC = 15 V. 5 5 60 Max. Fig. Note 5 1, 2 4 9 Table 6. Switching Specifications (RL= 20 kΩ) Over recommended operating conditions unless otherwise specified. TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off ) = -5 V to 0.8 V Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to Low Output Level tPHL 30 200 400 ns CL = 100 pF 5, 7 -11 8, 9 ns CL = 10 pF ns CL = 100 pF ns CL = 10 pF CL = 100 pF 100 Propagation Delay Time to High Output Level 270 tPLH 400 550 130 Pulse Width Distortion PWD 200 450 ns Propagation Delay Difference Between Any 2 Parts tPLH-tPHL -150 200 450 ns Output High Level Common Mode Transient Immunity |CMH| 15 30 kV/μs Output Low Level Common Mode Transient Immunity |CML| 15 30 kV/μs IF(on) = 10 mA, VF(off ) = 0.8 V, VCC = 15.0 V, V THLH = 2.0 V, V THHL = 1.5 V 13 10 IF = 0 mA, VO > 3.0 V VCC = 15.0 V, CL = 100 pF, V IF = 10 mA, CM = 1500 VP-P, VO < 1.0 V TA = 25°C 6 11 12 *All typical values at 25°C, VCC = 15 V. Table 7. Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 3750 Input-Output Resistance RI-O Input-Output Capacitance CI-O Typ. Max. Units Test Conditions Vrms RH < 50%, t = 1 min, TA = 25°C 6, 7 1012 : VI-O = 500 Vdc 6 0.6 pF Freq=1 MHz 6 5000 (For ACPL-W456) Fig. Note Notes: 1. Derate linearly above 90°C free-air temperature at a rate of 0.8 mA/°C. 2. Derate linearly above 90°C free-air temperature at a rate of 1.6 mA/°C. 3. Derate linearly above 90°C free-air temperature at a rate of 3.0 mW/°C. 4. Derate linearly above 90°C free-air temperature at a rate of 4.2 mW/°C. 5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current (IF) times 100. 6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together. 7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 μA) ; each optocoupler under ACPL-W456 is proof tested by applying an insulation test voltage ≥ 6000 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 μA). 8. Pulse: f = 20 kHz, Duty Cycle = 10%. 9. Use of a 0.1 μF bypass capacitor connected between pins 4 and 6 can improve performance by filtering power supply line noise. 10. The difference between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications section.) 11. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0 V). 12. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V). 13. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given device. 6 1.05 NORMALIZED OUTPUT CURRENT IO – OUTPUT CURRENT – mA 10 8 6 4 VO = 0.6 V 2 0 100 C 25 C -40 C 0 5 10 15 IF – FORWARD CURRENT – mA 0.90 IF = 10 mA VO = 0.6 V 0.85 -20 0 20 40 60 TA – TEMPERATURE – C 1000 VF = 0.8 V VCC = VO = 4.5 V OR 30 V IF – FORWARD CURRENT – mA 4.5 V 30 V 0.5 -20 0 20 40 100 TA = 25 C IF 1.5 1.0 80 Figure 2. Normalized Output Current vs. Temperature. 2.0 IOH – HIGH LEVEL OUTPUT CURRENT – μA 0.95 0.80 -40 20 Figure 1. Typical Transfer Characteristics. 0 -40 1.00 80 60 100 + VF - 10 1.0 0.1 0.01 0.001 1.10 100 1.20 1.30 1.40 1.50 1.60 VF – FORWARD VOLTAGE – VOLTS TA – TEMPERATURE – C Figure 3. High Level Output Current vs. Temperature. Figure 4. Input Current vs. Forward Voltage. IF(ON) = 10 mA 1 6 0.1μF + - 2 3 5 SHIELD If 20 kΩ VOUT + C L* VCC = 15 tf VO 4 * TOTAL LOAD CAPACITANCE 7 90% 90% 10% 10% VTHHL VTHLH tPHL Figure 5. Propagation Delay Test Circuit. tr tPLH IF 1 VCM 6 0.1 μF B 2 A 5 3 + SHIELD 20 kΩ VOUT + 100 pF * δV = VCM δt Δt VCC = 15 OV 4 Δt * 100 pF TOTAL CAPACITANCE VFF - VO + - VCC SWITCH AT A: IF = 0 mA VCM = 1500V VO VOL SWITCH AT B: IF = 10 mA Figure 6. CMR Test Circuit and Waveforms. 800 IF = 10 mA VCC = 15 V CL = 100 pF RL = 20 kΩ (EXTERNAL) 400 300 tP – PROPAGATION DELAY – ns tP – PROPAGATION DELAY – ns 500 tPLH tPHL 200 100 -40 -20 0 20 40 60 TA – TEMPERATURE – C 80 1000 tPLH tPHL 800 600 400 200 10 20 30 RL – LOAD RESISTANCE – kΩ 50 40 Figure 8. Propagation Delay vs. Load Resistance. IF = 10 mA CL = 100 pF RL = 20 kΩ TA = 25 C 1200 1000 800 tPLH tPHL 600 400 200 0 0 0 100 200 300 400 CL – LOAD CAPACITANCE – pF Figure 9. Propagation Delay vs. Load Capacitance. 8 200 1400 IF = 10 mA VCC = 15 V RL = 20 KΩ TA = 25 C 1200 tPLH tPHL 0 tP – PROPAGATION DELAY – ns tP – PROPAGATION DELAY – n 1400 400 100 Figure 7. Propagation Delay with External 20 kΩ RL vs. Temperature. IF = 10 mA VCC = 15 V CL = 100 pF TA = 25 C 600 500 5 10 15 20 VCC – SUPPLY VOLTAGE – V Figure 10. Propagation Delay vs. Supply Voltage. 25 30 tP – PROPAGATION DELAY – ns 500 VCC = 15 V CL = 100 pF RL = 20 kΩ TA = 25 C 400 Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through CLEDO1 in Figure 14. Many factors influence the effect and magnitude of the direct coupling including: the position of the LED current setting resistor and the value of the capacitor at the optocoupler output (CL). tPLH tPHL 300 1 CLEDP CLED01 200 2 100 0 5 10 15 IF – FORWARD LED CURRENT – mA 3 20 LED Drive Circuit Considerations For Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 13. The ACPL-P456/W456 improve CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pin and output ground as shown in Figure 14. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 12), can achieve 15 kV/μs CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure 12 to keep the LED off when the gate is in the high state. 6 0.1 μF 2 310 Ω 3 CMOS 5 SHIELD 20 kΩ VOUT + CL* VCC = 15 V 4 * 100 pF TOTAL CAPACITANCE Figure 12. Recommended LED Drive Circuit. 1 CLEDP CLEDN 4 SHIELD CMR With The LED On (CMRL) Applications Information 1 5 Figure 14. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. Figure 11. Propagation Delay vs. Input Current. +5 V 6 A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 10 mA provides adequate margin over the maximum ITH of 4.0 mA (see Figure 1) to achieve 15 kV/μs CMR. The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure 15 is connected to the anode. Figure 16 shows the AC equivalent circuit for Figure 15 during common mode transients. During a +dVCM/dt in Figure 16, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (IF) is reduced from its DC value by an amount equal to the current that flows through CLEDP and CLEDO1. The situation is made worse because the current through CLEDO1 has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure 12) places the current setting resistor in series with the LED cathode. Figure 17 is the AC equivalent circuit for Figure 12 during common mode transients. In this case, the LED current is not reduced during a +dVCM/dt transient because the current flowing through the package capacitance is supplied by the power supply. During a -dVCM/ dt transient, however, the LED current is reduced by the amount of current flowing through CLEDN. But, better CMR performance is achieved since the current flowing in CLEDO1 during a negative transient acts to keep the output low. +5 V 310 Ω 6 1 6 0.1 μF 2 5 20 kΩ VOUT + - VCC = 15 V CL* 2 5 3 CMOS 3 CLEDN 4 Figure 13. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. 9 SHIELD 4 * 100 pF TOTAL CAPACITANCE Figure 15. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended). ITOTAL* 300 Ω 1 ICLEDP ICLED01 IF CLED01 2 6 5 20 kΩ VOUT 100pF 3 CLEDN 4 SHIELD + - * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING + dVCM /dt VCM Figure 16. AC Equivalent Circuit for Figure 15 during Common Mode Transients. 1 + VR**- CLEDP CLED01 2 6 5 3 ICLEDN* CLEDN SHIELD +5 V 20 kΩ 6 2 5 4 SHIELD Q1 4 Figure 18. Not Recommended Open Collector LED Drive Circuit. 1 + - * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR + dVCM /dt TRANSIENTS. ** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH PERFORMANCE. V R < VF (OFF) DURING + dVCM /dt VCM Figure 17. AC Equivalent Circuit for Figure 12 during Common Mode Transients. A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a +dVCM/dt transient in Figure 17, the current flowing through CLEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than VF(OFF) the LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 100 pF capacitor from pins 5-4 will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure 12) provides about 10 V of margin between the lowest optocoupler output voltage and a 3 V IPM threshold during a 15kV/μs transient with VCM = 1500 V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure 17, to clamp the voltage across the LED below VF(OFF). CLEDP 6 CLED01 2 5 3 4 20kΩ VOUT 100pF Q1 300 Ω ICLEDN* CLEDN SHIELD * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR + dVCM /dt TRANSIENTS. + - CMR With The LED Off (CMRH) 10 1 3 VOUT 100pF 300 Ω Since the open collector drive circuit, shown in Figure 18, cannot keep the LED off during a +dVCM/dt transient, it is not desirable for applications requiring ultra high CMRH performance. Figure 19 is the AC equivalent circuit for Figure 18 during common mode transients. Essentially all the current flowing through CLEDN during a +dVCM/dt transient must be supplied by the LED. CMRH failures can occur at dv/dt rates where the current through the LED and CLEDN exceeds the input threshold. Figure 20 is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state. VCM Figure 19. AC Equivalent Circuit for Figure 18 during Common Mode Transients. +5 V 1 6 2 5 3 SHIELD 4 Figure 20. Recommended LED Drive Circuit for Ultra High CMR. IPM Dead Time and Propagation Delay Specifications The ACPL-P456/W456 includes a Propagation Delay Difference specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 21) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn on (tPHL) and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range. The limiting case of zero dead time occurs when the input to Q1 turns off at the same time that the input to Q2 turns on. This case determines the minimum delay between LED1 turn-off and LED2 turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in Figure 22. A minimum dead time of zero is achieved in Figure 22 when the signal to turn on LED2 is delayed by (tPLH max - tPHL min) from the LED1 turn off. Note that the propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under consideration are typically mounted in close proximity to each other. (Specifically, previous equation are not the same as the tPLH max and tPHL min, over the full operating temperature range, specified in the data sheet.) This delay is the maximum value for the propagation delay difference specification which is specified at 450 ns for the ACPL-P456/W456 over an operating temperature range of -40°C to 100°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest tPLH and another with the slowest tPHL are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the tPLH and tPHL propagation delays as shown in Figure 23. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the optocouplers) for the ACPL-P456/W456 are 600 ns (= 450 ns - (-150 ns)) over an operating temperature range of 40°C to 100°C. IPM ILED1 1 +5 V 6 0.1 μF 2 310 Ω CMOS 3 5 SHIELD 1 20 kΩ V OUT1 4 6 0.1 μF 2 310 Ω M 3 5 SHIELD 4 VCC2 20 kΩ V OUT2 ACPL-P/W456 ACPL-P/W456 ACPL-P/W456 ACPL-P/W456 ACPL-P/W456 Figure 21. Typical Application Circuit. 11 +HV ILED2 +5 V CMOS VCC1 --HV ILED1 ILED1 VOUT1 VOUT2 ILED2 Q1 OFF Q1 ON Q2 OFF VOUT1 VOUT2 Q1 OFF Q1 ON Q2 OFF Q2 ON Q2 ON ILED2 tPLH MIN. tPLH MAX. tPLH MAX. tPHL PDD* MAX. MIN. PDD* MAX. = (tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN. tPHL MIN. tPHL MAX. MAX. DEAD TIME *PDD = PROPAGATION DELAY DIFFERENCE MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) NOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES. = (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.) = (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.) = PDD* MAX. - PDD* MIN. Figure 22. Minimum LED Skew for Zero Dead Time. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES. Figure 23. Waveforms for Deadtime Calculation. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0647EN AV02-1306EN - July 31, 2010