AVAGO ACPL-H342-060E

ACPL-H342 and ACPL-K342
2.5 Amp Output Current IGBT Gate Drive Optocoupler
with Active Miller Clamp, Rail-to-Rail Output Voltage
and UVLO in Stretched SO8
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-H342/ACPL-K342 contains an AlGaAs LED,
which is optically coupled to an integrated circuit with a
power output stage. This optocoupler is ideally suited for
driving power IGBTs and MOSFETs used in motor control
inverter applications. The high operating voltage range of
the output stage provides the drive voltages required by
gate controlled devices. The voltage and high peak output
current supplied by this optocoupler make it ideally suited
for direct driving IGBT with ratings up to 1200V/150A. For
IGBTs with higher ratings, the ACPL-H342/ACPL-K342 can
be used to drive a discrete power stage which drives the
IGBT gate. The ACPL-H342 and ACPL-K342 have the highest
insulation voltage of VIORM = 891Vpeak and 1140Vpeak
respectively in the IEC/ EN/DIN EN 60747-5-5.
• 2.5 A Maximum Peak Output Current
• 2.0A Minimum Peak Output Current
• Built-in Active Miller Clamp
• Rail-to-Rail Output Voltage
• Fast Propagation Delay to minimize Dead Time
•tPHL < tPLH to provide “Anti-Cross” Conduction
• LED input threshold current hysteresis
•ICC = 2.5 mA Maximum Supply Current to allow bootstrap power supply
•Under Voltage Lock-Out Protection (UVLO) with
Hysteresis
• 40 kV/µs Minimum Common Mode Rejection (CMR) at
VCM = 1500 V
• Wide Operating VCC Range: 15 to 30 Volts
• Industrial Temperature Range: -40°C to 105°C
• Safety Approval:
– UL Recognized 3750/5000 VRMS for 1min.
–CSA
– IEC/EN/DIN EN 60747-5-5 VIORM = 891/1140 Vpeak
Functional Diagram
ANODE
1
8
VCC
NC
2
7
VOUT
CATHODE
3
6
VCLAMP
5
VEE
VVCLAMP
CLAMP
NC
4
Note: Design Note: A 1 μF bypass capacitor must be connected between
pins VCC and VEE.
Truth Table
LED
OFF
ON
ON
ON
VCC – VEE
VCC – VEE
“POSITIVE GOING” “NEGATIVE GOING”
(i.e., TURN-ON)
(i.e., TURN-OFF)
0 – 30V
0 – 11V
11 – 13.5V
13.5 – 30V
0 – 30V
0 – 9.5V
9.5 – 12V
12 – 30V
VO
Applications
•
•
•
•
•
IGBT/MOSFET Gate Drive
AC and Brushless DC Motor Drives
Renewable Energy Inverters
Industrial Inverters
Switching Power Supplies
VCLAMP
LOW
LOW
LOW
LOW
TRANSITION TRANSITION
HIGH
Hi-Z
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-H342 is UL Recognized with 3750 VRMS for 1 minute per UL1577.
ACPL-K342 is UL Recognized with 5000 VRMS for 1 minute per UL1577.
Part number
Option
(RoHS Compliant)
ACPL-H342
-000E
-500E
ACPL-K342
Package
Stretched
SO-8
Surface
Mount
X
X
-560E
X
-500E
Stretched
SO-8
UL 5000 VRMS /1
Minute rating
IEC/EN/DIN EN
60747-5-5
X
-060E
-000E
Tape &
Reel
80 per tube
X
X
X
-560E
X
1000 per reel
X
X
-060E
Quantity
X
80 per tube
X
1000 per reel
X
X
X
80 per tube
X
1000 per reel
X
X
80 per tube
X
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-H342-560E to order product of Stretched SO-8 Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-5 Safety Approval and RoHS compliant.
Example 2:
ACPL-K342-000E to order product of Stretched SO-8 Surface Mount package in Tube packaging with UL 5000 VRMS/1
minute and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
ACPL-H342 Outline Drawing
0.381
0.015
+ 0.127
0
+ 0.005
5.850
1.270
0.050
0.230
+ 0.254
0
+ 0.010
Land Pattern Recommendation
0.76 (0.03)
1.27 (0.05)
7.620
0.300
6.807
0.268
0.450
0.018
2.16
(0.085)
10.7
(0.421)
3.180 ±0.127
0.125 ±0.005
1.590 ±0.127
0.063 ±0.005
7°
45°
7°
0.200 ±0.100
0.008 ±0.004
0.254 ±0.050
0.010 ±0.002
7°
5° NOM.
1 ±0.250
0.040 ±0.010
7°
Lead Coplanarity = 0.1mm [0.004 Inches]
Floating Lead protusions max. 0.25 [0.0]
9.7 ±0.25
0.382 ±0.010
Dimensions in Millimeters [Inches]
ACPL-K342 Outline Drawing
+ 0.25
0
0.230 + 0.010
–
0.000

5.850
1.270BSG


 0.050 
0.381 ±0.13


0.015 ±0.005
1
8
2
7
3
6
4
5
Land Pattern Recommendation
0.76 (0.03)
1.27 (0.05)
7.62
0.300 
6.807 ±0.127


0.268 ±0.005




0.450
0.018 
0.200 ±0.100
0.008 ±0.004
0.750 ±0.25


0.0295 ±0.01


45°
7°
7°


35° NOM.
11.5 ±0.250
0.453 ±0.010


12.65
(0.5)
1.590 ±0.127
0.063 ±0.005




0.254 ±0.050
0.010 ±0.002
3.180 ±0.127
0.125 ±0.005
7°
7°
Lead Coplanarity = 0.1mm [0.004 Inches]
Floating Lead protusions max. 0.25 [0.0]
Dimensions in Millimeters [Inches]
3
1.905
(0.075)
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used.
Regulatory Information
The ACPL-H342 / ACPL-K342 is approved by the following organizations:
UL
Recognized under UL 1577, component recognition program up to VISO = 3750 VRMS (ACPL-H342) and VISO = 5000 VRMS
(ACPL-K342), File 55361
CSA
CSA Component Acceptance Notice #5, File CA 88324
IEC/EN/DIN EN 60747-5-5 (ACPL-H342/K342 Option 060 Only)
Maximum Working Insulation Voltage Viorm = 891Vpeak (ACPL-H342) and Viorm = 1140 Vpeak(ACPL-K342)
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-H342 / ACPL-K342 Option 060)
ACPL-H342
Option 060
ACPL-K342
Option 060
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
I – IV
I – IV
I – III
I – IV
I – IV
I – IV
for rated mains voltage ≤ 600 Vrms
I – III
I – IV
Description
Symbol
for rated mains voltage ≤ 1000 Vrms
Unit
I – III
Climatic Classification
Pollution Degree (DIN VDE 0110/39)
40/105/21
40/105/21
2
2
Maximum Working Insulation Voltage
VIORM
891
1140
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
VPR
1671
2137
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
VPR
1426
1824
Vpeak
Highest Allowable Overvoltage*
(Transient Overvoltage tini = 60 sec)
VIOTM
6000
8000
Vpeak
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature
Input Current
Output Power
TS
IS, INPUT
PS, OUTPUT
175
230
600
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
>109
>109
W
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
Note:
These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802.
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-H342
ACPL-K342
Units
Conditions
Minimum External Air Gap
(Clearance)
L(101)
7.0
8.0
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(Creepage)
L(102)
8.0
8.0
mm
Measured from input terminals to output
terminals, shortest distance path along body.
0.08
0.08
mm
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
> 175
> 175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
Notes:
1. All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting
point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board,
minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance
path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered (the recommended
Land Pattern does not necessarily meet the minimum creepage of the device). There are recommended techniques such as grooves and ribs which
may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending
on factors such as pollution degree and insulation level.
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Note
Operating Temperature
TA
-40
105
°C
Output IC Junction Temperature
TJ
125
°C
Average Input Current
IF(AVG)
25
mA
Peak Transient Input Current
(<1 µs pulse width, 300pps)
IF(TRAN)
1
A
Reverse Input Voltage
VR
5
V
“High” Peak Output Current
IOH(PEAK)
2.5
A
2
“Low” Peak Output Current
IOL(PEAK)
2.5
A
2
Peak Clamp Sink Current
ICLAMP
2.5
A
2
Total Output Supply Voltage
(VCC - VEE)
0
35
V
Output Voltage
VO(PEAK)
-0.5
VCC
V
Output IC Power Dissipation
PO
500
mW
3
Total Power Dissipation
PT
550
mW
4
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Note
1
Table 4. Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Operating Temperature
TA
- 40
105
°C
Output Supply Voltage
(VCC - VEE)
15
30
V
Input Current (ON)
IF(ON)
7
16
mA
Input Voltage (OFF)
VF(OFF)
- 3.6
0.8
V
5
Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values are at TA = 25°C, VCC - VEE = 30 V, VEE = Ground; all Minimum/Maximum specifications are at Recommended Operating Conditions (TA = -40 to 105°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC =
15 to 30 V, VEE = Ground).
Parameter
Symbol
Min.
Typ.
High Level Peak Output Current
IOH
-0.5
-1.2
Max.
-2.0
Low Level Peak Output Current
IOL
0.5
2.7
2.0
High Output Transistor RDS(ON)
RDS,OH
Low Output Transistor RDS(ON)
RDS,OL
Clamp Output Peak Current
ICLAMP
Clamp Pin Threshold
Units
Test Conditions
Fig.
Note
A
VO = VCC – 4
3, 4, 23
5
A
VO = VCC – 15
A
VO = VEE + 2.5V
A
VO = VEE + 15V
2
6, 7, 24
2
2.6
5.0
Ω
IOH = -2.0A
8
0.8
2.0
Ω
IOL = 2.0A
9
2.5
A
VO = VEE + 2.5
14, 16,
27
VtCLAMP
2.3
V
Clamp Output Transistor
RDS(ON)
RDS,CLAMP
0.8
High Level Output Voltage
VOH
High Level Output Voltage
1.0
5
2
15,16,
28
Ω
ICLAMP = 1.5 A
VCC-0.80
V
IO = -100 mA
2, 4, 25 6, 7
VOH
VCC
V
IO = 0 mA , IF=10 mA
1
Low Level Output Voltage
VOL
0.07
0.25
V
IO = 100 mA
5, 7, 26
High Level Supply Current
ICCH
1.68
2.5
mA
Rg = 10W,
Cg = 25 nF, IF = 10 mA,
10, 11
Low Level Supply Current
ICCL
2.0
2.5
mA
Rg = 10W,
Cg = 25 nF, IF = 0 mA
Threshold Input Current
Low to High
IFLH
0.5
1.5
4.0
mA
Rg = 10W,
Cg = 25 nF, VO > 5 V
12, 13,
29
Threshold Input Voltage
High to Low
VFHL
0.8
Input Forward Voltage
VF
1.2
IF = 10 mA
22
Temperature Coefficient of
Input Forward Voltage
ΔVF/ΔTA
Input Reverse Breakdown
Voltage
BVR
Input Capacitance
CIN
UVLO Threshold
VUVLO+
11.0
12.3
13.5
VUVLO-
9.5
10.7
12.0
UVLO Hysteresis
6
UVLOHYS
VCC-2.0
2.0
V
1.55
1.95
-1.7
mV/°C
5
70
1.4
V
V
IR = 100 µA
pF
f = 1 MHz, VF = 0 V
V
VO > 5 V, IF = 10 mA
30
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values are at TA = 25°C, VCC - VEE = 30 V, VEE = Ground; all Minimum/Maximum specifications are at Recommended Operating Conditions (TA = -40 to 105°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC =
15 to 30 V, VEE = Ground).
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time to
High Output Level
Propagation Delay Time to
Low Output Level
Propagation Delay Difference
Between Any Two Parts
Rise Time
Fall Time
Output High Level Common
Mode Transient Immunity
tPLH
0.100
0.260
0.350
µs
0.050
0.145
0.250
µs
17, 18,
19, 20,
21, 31
15
tPHL
-0.100
-0.200
µs
Rg = 10 W,
Cg = 25 nF,
f = 20 kHz ,
Duty Cycle = 50%,
IF = 7 mA to 16 mA,
VCC = 15 V to 30V
39, 40
11
VCC = 30 V
31
PDD
-0.010
(tPHL - tPLH)
tR
tF
|CMH|
40
Output Low Level Common
Mode Transient Immunity
|CML|
22
18
50
25
35
40
50
25
35
ns
ns
kV/µs
kV/µs
TA = 25 °C, IF = 10 mA, 32
VCC = 30 V, VCM = 1500
V with split resistors
TA = 25 °C, IF = 10 mA,
VCC = 30 V, VCM = 1000
V without split resistors
32
TA = 25 °C, VF = 0 V,
VCC = 30 V, VCM = 1500
V with split resistors,
TA = 25 °C, VF = 0 V,
VCC = 30 V, VCM = 1000
V without split resistors
12, 13
12, 14
Table 7. Package Characteristics
Unless otherwise noted, all typical values are at TA = 25 °C; all Minimum/Maximum specifications are at Recommended
Operating Conditions.
Parameter
Symbol
Device
Min.
Units
Test Conditions
Input-Output Momentary
Withstand Voltage*
VISO
ACPL-H342
3750
VRMS
ACPL-K342
5000
VRMS
RH < 50%,
t = 1 min., TA = 25 °C
RH < 50%,
t = 1 min., TA = 25 °C
VI-O = 500 VDC
f =1 MHz
Thermal Model in
Application Notes
Below
Input-Output Resistance
Input-Output Capacitance
LED-to-Ambient Thermal
Resistance
LED-to-Detector Thermal
Resistance
Detector-to-Ambient
Thermal Resistance
Typ.
RI-O
CI-O
R11
>5012
0.2
145
R12, R21
25, 38
R22
46
Max.
W
pF
°C/W
Fig.
Note
8,10
9,10
10
16
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074
entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70 °C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10µs
3. Derate linearly above 85°C free-air temperature at a rate of 12.5 mW/°C.
4. Derate linearly above 85°C free-air temperature at a rate of 13.75 mW/°C. The maximum LED junction temperature should not exceed 125°C.
5. Maximum pulse width = 50 µs.
6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms.
8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection
current limit, II-O ≤5 µA).
9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second (leakage detection
current limit, II-O ≤5 µA).
10.Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
11. The difference between tPHL and tPLH between any two ACPL-H342 parts under the same test condition.
12. Pins 2 and 4 need to be connected to LED common.
13. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VO > 15.0 V).
14. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VO < 1.0 V).
15. This load condition approximates the gate load of a 1200V/150A IGBT.
16.The device was mounted on a high conductivity test board as per JEDEC 51-7.
7
0
IF = 10 mA
VCC = 30 V
VEE = 0 V
29.974
29.973
29.972
29.971
29.97
29.969
29.968
-0.2
-1.2
-0.4
-0.6
-0.8
-1
-1.2
TA = 25°C
IOH - OUTPUT HIGH CURRENT - A
IOH - OUTPUT HIGH CURRENT - A
-1
0.00
IF = 10 mA
VOUT = (VCC  4 V)
VCC = 15 to 30 V
VEE = 0 V
Figure 3. IOH vs. temperature.
-0.50
-1.00
-1.50
-2.00
-2.50
0.00
-1.4
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
1.00
3.00
4.00
5.00
2.00
(VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V
6.00
Figure 4. IOH vs. VOH.
4
0.1
0.08
0.06
0.04
VF(OFF) = 0 V
IOUT = 100 mA
VCC = 15 to 30 V
VEE = 0 V
0.02
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 5. VOL vs. temperature.
IOL - OUTPUT LOW CURRENT - A
0.12
VOL - OUTPUT LOW VOLTAGE - V
-0.8
Figure 2. VOH vs. temperature.
0
8
-0.6
-1.6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 1. High Ouput Rail Voltage vs. Temperature.
0
-0.4
-1.4
29.967
29.966
IF = 10 mA
IOUT = -100 mA
VCC = 15 to 30 V
VEE = 0 V
-0.2
(VOH - VCC) - HIGH OUTPUT
VOLTAGE DROP - V
VOH - HIGH OUTPUT RAIL VOLTAGE- V
29.975
VF(OFF) = 0 V
VOUT = 2.5 V
VCC = 15 to 30 V
VEE = 0 V
3.5
3
2.5
2
1.5
1
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 6. IOL vs. temperature.
3.5
2.5
3
RDS,OH - HIGH OUTPUT
TRANSISTOR RDS(ON) - Ω
IOL - OUTPUT LOW CURRENT - A
3.0
2.0
1.5
1.0
0.5
0.0
0
1
2
VOL - OUTPUT LOW VOLTAGE - V
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 8. RDS,OH vs. temperature.
2.5
ICC - SUPPLY CURRENT -mA
RDS,OL - LOW OUTPUT TRANSISTOR
RDS (ON) - Ω
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
IF = 10 mA
IOUT = -2 A
VCC = 15 to 30 V
VEE = 0 V
1
3
VF(OFF) = 0 V
IOUT = 2 A
VCC = 15 to 30 V
VEE = 0 V
2
1.5
1
IF = 10 mA for ICCH
IF = 0 mA for ICCL
VCC = 30 V
VEE = 0 V
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
ICCH
ICCL
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 10. ICC vs. temperarure.
35
2.5
TA = 25°C
VCC = 30 V
VEE = 0 V
30
2
VO - OUTPUT VOLTAGE- V
ICC - SUPPLY CURRENT - mA
1.5
0.5
Figure 9. RDS,OL vs. temperature.
1.5
1
IF = 10 mA for ICCH
IF = 0 mA for ICCL
TA = 25°C
VEE = 0 V
0.5
15
Figure 11. ICC vs. VCC.
9
2
TA = 25°C
VF(OFF) = 0 V
Figure 7. IOL vs. VOL
0
2.5
20
25
VCC - SUPPLY VOLTAGE - V
ICCH
ICCL
25
20
15
10
IFLH ON
IFLH OFF
5
30
0
0.0
0.5
1.0
1.5
2.0
2.5
IFLH - LOW TO HIGH CURRENT THRESHOLD - mA
Figure 12. IFLH hysteresis.
3.0
ICLAMP - CLAMP OUTPUT PEAK CURRENT - A
VCC = 15 to 30 V
VEE = 0 V
2.0
1.5
1.0
0.5
0.0
IFLH ON
IFLH OFF
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 13. IFLH vs. temperature.
VtCLAMP - CLAMP PIN THRESHOLD - V
3.5
3
2.5
2
1.5
1
VCC = 15 V
VEE = 0 V
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
3
2.5
2
1.5
1
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
3.0
2.0
1.5
1.0
0.5
0.0
-0.5
300
250
250
TPHL
TPLH
150
IF = 7 mA
TA = 25°C
Rg = 10 Ω, Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
100
50
0
15
20
25
VCC - SUPPLY VOLTAGE - V
Figure 17. Propagation delay vs. VCC.
TA = 25°C
2.5
300
200
VCC = 15 to 30 V
VEE = 0 V
VOUT = 2.5 V
0.5
0
0.5
1
1.5
2
VtCLAMP - CLAMP PIN THRESHOLD - V
2.5
Figure 16. ICLAMP vs. VtCLAMP.
TP - PROPAGATION DELAY - ns
TP - PROPAGATION DELAY - ns
Figure 15. VtCLAMP vs. temperature.
10
3.5
Figure 14. ICLAMP vs. temperature.
ICLAMP - CLAMP OUTPUT PEAK CURRENT - A
IFLH - LOW TO HIGH CURRENT
THRESHOLD - mA
2.5
30
TPHL
TPLH
200
150
VCC = 30 V, VEE = 0 V
TA = 25°C
Rg = 10 Ω, Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
100
50
0
6
8
10
12
IF - FORWAR LED CURRENT - mA
Figure 18. Propagation delay vs. IF.
14
16
300
TPHL
TPLH
300
250
200
150
IF = 7 mA
VCC = 30 V, VEE = 0 V
Rg = 10 Ω, Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
100
50
0
150
VCC = 30 V, VEE = 0 V
IF = 7 mA, TA = 25°C
Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
100
50
0
5
10
15 20 25 30 35 40
Rg - SERIES LOAD RESISTANCE - Ω
45
50
100
250
IF - FORWARD CURRENT - mA
TP - PROPAGATION DELAY - ns
TPLH
TPHL
200
Figure 20. Propagation delay vs. Rg.
300
TPLH
TPHL
200
150
VCC = 30 V, VEE = 0 V
IF = 7 mA, TA = 25°C
Rg = 10 Ω
DUTY CYCLE = 50%
f = 20 kHz
100
50
0
5
10
15 20 25 30 35
Cg - LOAD CAPACITANCE - nF
Figure 21. Propagation delay vs. Cg.
11
250
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 19. Propagation delay vs. temperature.
0
TP - PROPAGATION DELAY - ns
TP - PROPAGATION DELAY - ns
350
40
45
50
10
1
0.1
1.4
1.45
1.5
1.55
1.6
VF - FORWARD VOLTAGE - VOLTS
Figure 22. Input current vs. forward voltage.
1.65
4V Pulsed
1
IF = 10mA
8
+
_
1µF
2
3
7
VVCLAMP
CLAMP
+
_
IOH
VCC = 15 to 30V
6
4
5
1
8
2
7
Figure 23. IOH test circuit.
1µF
3
VVCLAMP
CLAMP
IOL
+
_
6
4
5
1
8
2
7
VCC = 15 to 30V
+
_
2.5V
Pulsed
Figure 24. IOL test circuit.
IF = 10mA
3
1µF
VVCLAMP
CLAMP
VCC = 15 to 30V
VOH
+
_
6
100mA
4
5
1
8
2
7
Figure 25. VOH test circuit.
3
4
Figure 26. VOL test circuit.
12
1µF
VVCLAMP
CLAMP
6
5
VOL
100mA VCC = 15 to 30V
+
_
1
8
2
7
1µF
VCC = 15 to 30V
+
_
ICLAMP
3
VVCLAMP
CLAMP
4
6
+
_
5
2.5V Pulsed
Figure 27. ICLAMP test circuit.
1
8
2
7
1µF
3
VVCLAMP
CLAMP
4
VtCLAMP
6
1kΩ
VCC = 15 to 30V
3V
+
_
+
_
5
Figure 28. VtCLAMP test circuit.
IF
1
8
2
7
1µF
3
VVCLAMP
CLAMP
VO > 5V
10Ω
6
25nF
4
5
1
8
2
7
Figure 29. IFLH test circuit.
IF = 10mA
1µF
3
4
Figure 30. UVLO test circuit.
13
VVCLAMP
CLAMP
6
5
VO > 5V
+
_
+
_
VCC = 15 to 30V
IF = 7 to 16mA,
20kHz, 50% Duty
Cycle
1
8
2
7
3
6
IF
1µF
VVCLAMP
CLAMP
4
VO
10Ω
+
_
VCC = 15 to 30V
tr
tf
90%
50%
25nF
V OUT
5
10%
tPLH
tPHL
Figure 31. tPLH, tPHL, tr and tf test circuit and waveforms.
170 ohm
5V
+
_
V CM
1
δV
8
1µF
2
170 ohm
3
7
VVCLAMP
CLAMP
4
6
5
VO
VCC = 30V
+
_
δt
V CM
∆t
0V
∆t
VO
V OH
SWITCH AT A: IF = 10 mA
VO
+
_
=
V OL
SWITCH AT B: IF = 0 mA
VCM = 1500V
Figure 32. CMR test circuit with split resistors network and waveforms.
Application Information
Product Overview Description
Recommended Application Circuit
The ACPL-H342/K342 is an optically isolated power output
stage capable of driving IGBTs of up to 150 A and 1200
V. It has very high CMR rating which allows the microcontroller and the IGBT to operate at very large common
mode noise found in industrial motor drives and other
power switching applications. And to achieve better
system reliability in such noisy environment, this power
control device incorporates new features like Active Miller
clamp, Rail-to-Rail output voltage, Anti-cross conduction
and LED input current hysteresis.
The recommended application circuit shown in Figure 33
illustrates a typical gate drive implementation using the
ACPL-H342. The following describes about driving IGBT.
However, it is also applicable to MOSFET. Designers will
need to adjust the VCC supply voltage, depending on the
MOSFET or IGBT gate threshold requirements (Recommended VCC = 18V for IGBT and 12V for MOSFET).
Active Miller clamp function eliminates the need of
negative gate drive in most application and allows the
use of simple bootstrap supply for high side driver. Rail-toRail output voltage ensures that the IGBT’s gate voltage is
driven to the optimum intended level with no power loss
across IGBT. Anti-cross conduction prevents current shoot
through between the high and low side of half bridge
IGBT configuration. This will help to simplify the controller
design in terms of having to account for the delay needed
at the LED input. And lastly, the LED input current hysteresis prevents output oscillation if insufficient LED driving
current is applied. This will eliminates the need of additional Schmitt trigger circuit at the input LED.
This feature rich IGBT gate driver is designed to increase the
performance and reliability of a motor drive without the
cost, size, and complexity of external circuitry or control.
14
The supply bypass capacitors (1 µF) provide the large
transient currents necessary during a switching transition.
Because of the transient nature of the charging currents,
a low current (2.5mA) power supply will be enough to
power the device. The split resistors across the LED will
provide a high CMR response by providing a balanced resistance network across the LED.
The gate resistor RG serves to limit gate charge current
and controls the IGBT collector voltage rise and fall times.
In PC board design, care should be taken to avoid routing
the IGBT collector or emitter traces close to the ACPL-H342
input as this can result in unwanted coupling of transient
signals into ACPL-H342 and degrade performance.
R
1
+
_
ANODE
2
NC
3
CATHODE
4
NC
R
8
VCC
VOUT
7
VCLAMP
6
VEE
5
RG
+
_
1µF
VCC=18V
Q1
Q2
+
VCE
+
VCE
-
+ HVDC
3-PHASE
AC
-HVDC
Figure 33. Recommended application circuit with split resistors LED drive and active Miller Clamp.
Active Miller Clamp
Rail-to-Rail Output
A Miller clamp allows the control of the Miller current
during a high dV/dt situation. And it can also eliminate
the use of a negative supply voltage by quickly discharging the large gate capacitance of IGBT to low level without
affecting the IGBT turn-off characteristics. During turn-off,
the gate voltage is monitored and the clamp output is
activated when gate voltage goes below 2.3V (relative to
VEE). The clamp voltage is VOL+2.5V typ for a Miller current
up to 2.5 A. The clamp is disabled when the LED input is
triggered again.
Figure 34 shows a typical gate driver’s high current
output stage with 3 bipolar transistors in darlington configuration. During the output high transition, the output
voltage rises rapidly to within 3 diode drops of VCC. To
ensure the VOUT is at VCC in order to achieve IGBT rated
VCE(ON) voltage. The level of VCC will be need to be raised
to beyond VCC+3(VBE) to account for the diode drops. And
to limit the output voltage to VCC, a pull-down resistor,
RPULL-DOWN between the output and VEE is recommended
to sink a static current while the output is high.
AN5314 application note describes how the clamp reduces
the parasitic turn-on effect due to the Miller capacitor and
at the same time eliminates the need of a negative power
supply.
ACPL-H342 uses a power NMOS follower stage to deliver
the initial large current and a smaller PMOS to pull it to VCC
to achieve Rail-to-Rail output voltage as shown in Figure
35. This ensures that the IGBT’s gate voltage is driven to
the optimum intended level with no power loss across
IGBT even when an unstable power supply is used.
The Miller pin should be connected to VEE when not in use.
ANODE
8
1
VCC
RG
7
NC
2
CATHODE
3
6
NC
4
VEE
5
VOUT
RPULL-DOWN
Figure 34. Typical gate driver with output stage in darlington configuration
ANODE
1
8
VCC
NC
2
7
VOUT
CATHODE
3
6
VCLAMP
NC
4
5
VEE
VVCLAMP
CLAMP
Figure 35. ACPL-H342 with NMOS and PMOS output stage for Rail-to-Rail output voltage
15
Selecting the Gate Resistor (Rg)
Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 33 can be analyzed as a simple
RC circuit with a voltage supplied by ACPL-H342/K342.
Rg ≥
VCC  VEE  VOL
IOLPEAK
=
18V  0V  2.3V
2.5A
= 6.28Ω ≈ 7Ω
The VOL value of 2.3V in the previous equation is the VOL at the peak current of 2.5A (see Figure 7).
Step 1: Check the ACPL-H342/K342 power dissipation and increase Rg if necessary. The ACPL-H342/K342 total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO).
PT = PE + PO
PE = IF • VF • Duty Cycle
PO= PO(BIAS) + PO(SWITCHING)
= ICC • (VCC-VEE) + ESW(Rg;Qg) • f
Using IF(worst case) = 16mA, Rg = 7Ω, Max Duty Cycle = 80%, Qg = 500nC, f = 25kHz and TA max = 85°C:
PE = 16mA • 1.95V • 0.8 = 25mW
PO= 2.5mA • 18V + 4µJ • 25 kHz
= 45mW + 100mW
= 145mW < 500mW (PO(MAX) @ 85°C)
The value of 2.5mA for ICC in the previous equation is the maximum ICC over the entire operating temperature range.
Esw - ENERGY PER SWITCHING CYCLE - µJ
Since PO is less than PO(MAX), Rg = 7Ω is alright for the power dissipation.
8
Qg = 100nc
Qg = 500nc
Qg = 1000nc
7
6
5
4
3
2
1
0
0
10
20
30
Rg - GATE RESISTANCE - Ω
40
50
Figure 36. Energy Dissipated in the ACPL-H342/K342 for each IGBT switching cycle.
16
Anti-Cross Conduction to Prevent Current Shoot Through and Determining Dead Time
The ACPL-H342 includes a Propagation Delay Difference (PDD = tPHL – tPLH ) specification to help prevent both the
high(Q1) and low(Q2) side power transistors from turning on at the same time. This “Anti-Cross” conduction feature
prevents large currents from flowing through the power transistors by ensuring tPHLMAX is faster than tPLHMIN. In another
words, the “Anti-Cross” feature will ensure one power transistor is turned off before the other is turned on.
A gate driver without Anti-Cross feature will for example has a PDDMIN of -350ns and a PDDMAX of 350ns. A positive
PDDMAX of 350ns would mean one transistor will be turn on before the other is off since tPHLMAX is longer than tPLHMIN.
This is shown in Figure 37. To prevent this and the shoot through current, the turn on of LED2 should be delayed (relative
to the turn off of LED1) so that under worst-case conditions, Q1 has just turned off when Q2 turns on. The amount of
delay to achieve this condition is equal to PDDMAX as shown in Figure 38.
R
High Side PWM
+ HVDC
RG
Low Side PWM
LED1
R
VOUT1
Q1
AC
RG
LED2
VOUT2
Q2
-HVDC
ILED1
ILED1
VOUT1
VOUT1
Q1 ON
tPHLMAX
Q1 ON
tPHLMAX
Q1 OFF
Q2 ON
Q2 ON
VOUT2
Q2 OFF
tPLHMIN
VOUT2
ILED2
ILED2
Shoot
Through
Figure 37. Current shoot through without Anti-Cross feature
17
Q1 OFF
Q2 OFF
tPLHMIN
PDDMAX = tPHLMAX - tPLHMIN = 350 ns
Figure 38. Adding delay to prevent shoot through
The ACPL-H342 with the Anti-Cross feature has a PDDMIN
of -10ns and a PDDMAX of -200ns. Since the PDD is always
a negative value, the tPHLMAX is always faster than tPLHMIN.
Thus this simplified the design without having to add any
amount of delay for the input LEDs as shown in Figure 39.
Symbol
Min.
Typ.
Max.
Units
tPLH
0.100
0.260
0.350
µs
tPHL
0.050
0.145
0.250
µs
PDD (tPHL - tPLH)
-0.010
-0.100
-0.200
µs
ILED1
Dead time is the time period during which both the
high(Q1) and low(Q2) side transistor are off. During this
time, no work is done and this reduces the efficiency of
the inverter or motor drive. The minimum and maximum
dead time is shown in Figure 39 and 40 and is equivalent
to the PDDMIN and PDDMAX . Due to the smaller PDD and
skewed propagation delay configuration, ACPL-H342
shows a smaller maximum dead time as compared to its
predecessor, HCPL-3120 as shown in figure 41 and hence
an improve in efficiency. Note that the propagation delays
used to calculate PDD and dead time are taken at equal
temperature and test conditions since the optocouplers under consideration are typically mounted in close
proximity to each other and are switching identical IGBTs.
ILED1
VOUT1
Q1 ON
tPHLMAX
Q1 OFF
tPLHMAX
VOUT2
Q2 OFF
VOUT1
Q1 ON
tPHLMIN
Q2 ON
tPLHMIN
Q1 OFF
tPHLMAX
VOUT2
Q2 ON
Q2 OFF
ILED2
PDDMIN = -10 ns
= Minimum Dead Time
ILED2
Figure 39. Anti-Cross to prevent shoot through
Maximum Dead Time
= (tPHLMAX – tPHLMIN) + (tPLHMAX – tPLHMIN)
= (tPHLMAX – tPLHMIN) + (tPHLMIN – tPLHMAX)
= PDDMAX – PDDMIN
= 350 – (-350) = 700 ns
ILED1
Figure 41. HCPL-3120 maximum dead time
VOUT1
Q1 ON
VOUT2
Q2 OFF
tPHLMIN
Q1 OFF
tPLHMAX
Q2 ON
tPLHMIN
ILED2
PDDMAX = -200 ns
= Minimum Dead Time
Figure 40. Determining maximum dead time
18
tPLHMIN
tPLHMAX
LED Input Current Hysteresis
The detector has optical receiver input stage with built in
Schmitt trigger to provide logic compatible waveforms,
eliminating the need for additional wave shaping. The
hysteresis (Figure 12) provides differential mode noise
immunity and minimizes the potential for output signal
chatter.
Under Voltage Lockout
The ACPL-H342 Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the ACPL-H342 output low
during power-up. IGBTs typically require gate voltages of
15 V to achieve their rated VCE(ON) voltage. At gate voltages
below 13 V typically, the VCE(ON) voltage increases dramatically, especially at higher currents. At very low gate
voltages (below 10 V), the IGBT may operate in the linear
region and quickly overheat. The UVLO function causes
the output to be clamped whenever insufficient operating
supply (VCC) is applied. Once VCC exceeds VUVLO+ (the positive-going UVLO threshold), the UVLO clamp is released
to allow the device output to turn on in response to input
signals.
Thermal Model for ACPL-H342/K342 Stretched SO8
Package Optocoupler
Definitions:
Ambient Temperature: Junction to Ambient Thermal Re­
sistances were measured approximately 1.25cm above
optocoupler at ~23°C in still air
Thermal Resistance
°C/W
R11
145
R12, R21
25, 38
R22
46
This thermal model assumes that an 8-pin single-channel
plastic package optocoupler is soldered into a 7.62 cm x
7.62 cm printed circuit board (PCB) per JEDEC standards.
The temperature at the LED and Detector junctions of the
optocoupler can be calculated using the equations below.
T1 = (R11 * P1 + R12 * P2) + TA(1)
T2 = (R21 * P1 + R22 * P2) + TA(2)
Using the given thermal resistances and thermal model
formula in this datasheet, we can calculate the junction
temperature for both LED and the output detector. Both
junction temperature should be within the absolute
maxi­mum rating.
For example, given P1 = 45 mW, P2 =210 mW, Ta = 85°C:
LED junction temperature,
R11: Junction to Ambient Thermal Resistance of LED due
to heating of LED
T1 = (R11 * P1 + R12 * P2) + TA
= (145 * 0.045 + 25 * 0.210) + 85
= 97°C
R12: Junction to Ambient Thermal Resistance of LED due
to heating of Detector (Output IC)
Output IC junction temperature,
R21: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of LED.
T2 = (R21 x P1 + R22 x P2) + TA
= (38 *0.045 + 46 * 0.210) + 85
= 96°C
R22: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of Detector (Output IC).
T1 and T2 should be limited to 125°C based on the board
layout and part placement.
P1: Power dissipation of LED (W).
Related Application Noted
P2: Power dissipation of Detector / Output IC (W).
T1: Junction temperature of LED (°C).
AN5336 – Gate Drive Optocoupler Basic Design for IGBT/
MOSFET
T2: Junction temperature of Detector (°C).
AN1043 – Common-Mode Noise: Sources and Solutions
TA: Ambient temperature.
AN02-0310EN – Plastics Optocouplers Product ESD and
Moisture Sensitivity
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www.avagotech.com
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Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-2526EN - March 13, 2013