SUMMIT S24VP04 MICROELECTRONICS, Inc. 4K Serial E2PROM with a Precision Low-VCC Lockout Circuit 3 and 5 Volt Systems FEATURES • Voltage Protection™ OVERVIEW The S24VP04 is a 4K-bit serial E2PROM memory integrated with a precision VCC sense circuit. The sense circuit will disable write operations whenever VCC falls below the VLOCK voltage. It is fabricated using SUMMIT’s advanced CMOS E2PROM technology and is suitable for both 3 and 5 volt systems. • Precision Low-VCC Write Lockout • All Write Operations Inhibited When VCC Falls below VLOCK • One 3Volt and Two 5Volt System Versions – VLOCK = 2.6V+.1V/-.05V – VLOCK = 4.25V +.25V/-0.0V – VLOCK = 4.50 +.25V/-0.0V • 100% Compatible with Industry Standard I2C™ Devices – Bi-directional data transfer protocol – Standard 100kHz and 400kHz Transfer Rates • 16-Byte Page-Write Mode – Minimizes total write time per byte • 1,000,000 Program/Erase Cycles The S24VP04 is internally organized as 512 x 8. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus. • 100 Year Data Retention • Commercial Industrial Temperature Range BLOCK DIAGRAM VCC 8 RESET PULSE GENERATOR 5KHz Oscillator NC 7 + VTRIP GND RESET CONTROL 4 1.26V SCL 6 SDA 5 NC 1 NC 3 NC 2 MODE DECODE WRITE CONTROL ADDRESS DECODER E2PROM MEMORY ARRAY DATA I/O 2008 ILL2 1.2 SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 © SUMMIT MICROELECTRONICS, Inc. 1998 2008 1.4 5/15/98 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com Characteristics subject to change without notice 1 S24VP04 PIN CONFIGURATIONS Address Inputs A0, A1, A2- Device Address Inputs These inputs are unused by the S24VP04; however, to ensure proper operation they should be left unconnected or tied to ground. The should not be tied high. Plastic Dual-in-line “P” Package A0 1 8 VCC A1 2 7 DC A2 3 6 SCL GND 4 5 SDA ENDURANCE AND DATA RETENTION The S24VP04 is designed for applications requiring 1,000,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 1,000,000 erase/write cycles. JEDEC Small Outline “S” Package DEVICE OPERATION A0 1 8 VCC A1 2 7 DC A2 3 6 SCL GND 4 5 SDA APPLICATIONS The S24VP04 was designed specifically for applications where the integrity of the stored data is paramount. In recent years, as the operating voltage range of serial E2PROMs has widened, most semiconductor manufacturers have arbitrarily eliminated their VCC sense circuits. The S24VP04 will protect your data by guaranteeing write lockout below the selected VCC Lockout voltage. 2008 ILL1 1.2 VCC Lockout The S24VP04 has an on-board precision VCC sense circuit. Whenever VCC is below VLOCK, the S24VP04 will disable the internal write circuitry. The VCC lockout circuit will ensure a higher level of data integrity than can be expected from industry standard devices that have either a very loose specification or no VCC lockout specification. PIN NAMES A0, A1,A2 SDA SCL DC GND VCC Address Inputs Serial Data I/O Serial Clock Input Don’t Care Ground Supply Voltage During a power-on sequence all writes will be inhibited below the VLOCK level and will continue to be held in a write inhibit state for approximately 200ms after VCC reaches, then stays at or above VLOCK. The 200ms delay provides a buffer space for the microcontroller to complete its power-on initialization routines (reading is OK) while still protecting against inadvertent writes. PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. During a power-down sequence initiation of writes will be inhibited whenever VCC falls below VLOCK. This will guard against the system’s microcontroller performing an inadvertent write within the ‘danger zone’. (see AN001) Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. 2008 1.4 5/15/98 2 S24VP04 Vcc SDA RESET SCL Master Transmitter/ Receiver Slave Transmitter/ Receiver Slave Receiver Master Transmitter/ Receiver Master Transmitter (µC/ µP) (24VP04) 2008 ILL 3 1.1 FIGURE 1. TYPICAL SYSTEM CONFIGURATION SCL Data must remain stable while clock is HIGH. Change of data allowed Data must remain stable while clock is HIGH. SDA In tHD:DAT tSU:DAT tHD:DAT 2008 ILL4 1.0 FIGURE 2. INPUT DATA PROTOCOL SCL STOP Condition START Condition SDA In 2008 ILL5 1.0 FIGURE 3. START AND STOP CONDITIONS 3 2008 1.4 5/15/98 S24VP04 SCL from Master Data Output from Transmitter 1 9 8 Start Condition tAA Data Output from Receiver ACKnowledge tAA 2008 ILL6 1.0 FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER CHARACTERISTICS OF THE I2C BUS Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 4). General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). The S24VP04 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the S24VP04 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition (See Figure 2). In the READ mode, the S24VP04 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the S24VP04 will continue to transmit data. If an ACKnowledge is not detected, the S24VP04 will terminate further data transmissions and awaits a STOP condition before returning to the standby power mode. START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the “START” condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the “STOP” condition (See Figure 3). Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see figure 5). For the S24VP04 this is fixed as 1010[B]. DEVICE OPERATION The S24VP04 is a 16,384-bit serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a “transmitter” and any device which receives data as a “receiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” In all cases, the S24VP04 will be a “slave” device, since it never initiates any data transfers. DEVICE IDENTIFIER 1 0 1 HIGH ORDER WORD ADDRESS 0 S2 S1 BS (A8) 2008 ILL7 1.0 FIGURE 5. SLAVE ADDRESS BYTE 2008 1.4 5/15/98 4 S24VP04 The next two bits are don’t care. The S24VP04 will respond to all commands for device 1010. Upon receipt of the word address, the S24VP04 responds with an ACKnowledge. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the S24VP04 begins the internal write cycle. Bank Select Bit The next bit of the serial stream is the bank select bit. It is used by the host to toggle between the two 2K-bit banks of memory. It is, in effect, the most significant bit of the word address, or A8. While the internal write cycle is in progress, the S24VP04 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 6 for the address, ACKnowledge and data transfer sequence. Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to “1,” a read operation is selected; when set to “0,” a write operation is selected. Page WRITE The S24VP04 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more words of data. After the receipt of each word, the S24VP04 will respond with an ACKnowledge. WRITE OPERATIONS The S24VP04 allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. The S24VP04 automatically increments the address for subsequent data words. After the receipt of each word, the four low order address bits are internally incremented by one. The high order five bits of the address byte remain constant. Should the master transmit more than sixteen words, prior to generating the STOP condition, the address counter will “roll over,” and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 6 for the address, ACKnowledge and data transfer sequence. Byte WRITE After the slave address is sent (to identify the slave device, specify high order word address and a read or write operation), a second byte is transmitted which contains the low 8 bit addresses of any one of the 512 words in the array. If single byte-write only, Stop bit issued here. Acknowledges Transmitted from 24VP04 to Master Receiver SDA Bus Activity A 2 A B R 1 S W 1010 0 A C Word Address K A A A A A A A A 7 6 5 4 3 2 1 0 A C K Data Byte n D D D D D D D D 7 6 5 4 3 2 1 0 A C K Acknowledges Transmitted from 24043 to Master Receiver A A Data Byte n+1 C Data Byte n+15 C K K D D D D D D D D 7 6 5 4 3 2 1 0 D D D D D D D D 7 6 5 4 3 2 1 0 S T O P S T Device A2,A1,BS Type A R Address Read/Write T 0= Write Slave Address Master Sends Read Request to Slave Master Transmitter to Slave Receiver Master Writes Word Address to Slave Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Master Writes Data to Slave Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Master Writes Data to Slave Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Master Writes Data to Slave Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver 2008 ILL8 1.0 Shading Denotes 24VP04 SDA Output Active FIGURE 6. PAGE/BYTE WRITE MODE 5 2008 1.4 5/15/98 S24VP04 Acknowledge Polling When the S24VP04 is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to “1.” There are four different read options: 1. 2. 3. 4. To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 7). Current Address Byte Read The S24VP04 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the S24VP04 receives the slave address field with the R/W bit set to “1,” it issues an acknowledge and transmits the 8-bit word stored at address location n+1. Internal WRITE Cycle In Progress; Begin ACK Polling Issue Start Issue Slave Address and R/W = 0 ACK Returned? Issue Stop No The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the S24VP04 discontinues data transmission. See Figure 8 for the address acknowledge and data transfer sequence. Yes (Internal WRITE Cycle is completed) Next operation a WRITE? Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read No Yes Issue Byte Address Issue Stop Proceed with WRITE Await Next Command 2008 ILL9 1.0 FIGURE 7. ACKNOWLEDGE POLLING SDA Bus Activity A A B R 2 1 S W 1 1 0 1 0 1 S Device T Type A2,A1,BS A Address Read/Write R 1= Read T Slave Address Master sends Read request to Slave Master Transmitter to Slave Receiver A C K Data Byte D D D D D D D D 7 6 5 4 3 2 1 0 1 Lack of ACK (low) from Master determines last data byte to be read S T O P Slave sends Data to Master Slave Transmitter to Master Receiver Shading Denotes 24VP04 SDA Output Active 2008 ILL 10 1.0 FIGURE 8. CURRENT ADDRESS BYTE READ MODE 2008 1.4 5/15/98 6 S24VP04 Random Address Byte Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the S24VP04 to the desired address. SDA Bus Activity A A B R 2 1 S W 1 0 1 0 0 A C K After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The S24VP04 will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The S24VP04 discontinues data transmission and reverts to its standby power mode. See Figure 9 for the address, acknowledge and data transfer sequence. Word Address A A A A 7 6 5 4 A A 3 2 A A 1 0 Slave Address Master Transmitter to Slave Receiver Shading Denotes 24VP04 SDA Output Active A A B R 2 1 S W 1 0 1 0 1 S T Device A2,A1,BS A Type Address Read/Write R 1= Read T S T Device A2,A1,BS Type A Address Read/Write R 0= Write T Master sends Read request to Slave A C K Slave Address Master Writes Word Address to Slave Master Requests Data from Slave Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver A C K Data Byte D D D D D D D D 7 6 5 4 3 2 1 0 1 Lack of ACK (low) from Master determines last data byte to be read S T O P Slave sends Data to Master Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver 2008 ILL11 1.0 FIGURE 9. RANDOM ADDRESS BYTE READ MODE 7 2008 1.4 5/15/98 S24VP04 Sequential READ Sequential READs can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the S24VP04. The S24VP04 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP conditions. During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will ‘roll-over’ and the memory will continue to output data. See Figure 10 for the address, acknowledge and data transfer sequence. Acknowledge from Master Receiver Acknowledges from 24VP04 SDA Bus Activity A A B R 2 1 S W 1 0 1 0 S T Device A Type R Address T 0 A C Word Address K A A A A A A A A 7 6 5 4 3 2 1 0 Read/Write 0= Write 1 0 1 0 1 A C K A First Data Byte C Last Data Byte K D D D D D D D D 7 6 5 4 3 2 1 0 D D D D D D D D 7 6 5 4 3 2 1 0 Lack of ACK (low) determines last data byte to be read Slave Address Master Writes Word Address to Slave Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Master Requests Data from Slave Master Transmitter to Slave Receiver Slave sends Data to Master Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave sends Data to Master Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver Shading Denotes 24VP04 SDA Output Active 2008 ILL 12 1.0 FIGURE 10. SEQUENTIAL READ OPERATION (starting with a Random Address READ) 2008 1.4 5/15/98 1 S T O P 1= Read Slave Address Master Transmitter to Slave Receiver A A B R 2 1 S W S T Device A Type A2,A1,BS R Address Read/Write T A2,A1,BS Master sends Read request to Slave A C K Lack of Acknowledge from Master Receiver 8 S24VP04 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................................................................................................................ -40°C to +85°C Storage Temperature ..................................................................................................................... -65°C to +125°C Soldering Temperature (less than 10 seconds) ............................................................................................... 300°C Supply Voltage ............................................................................................................................................ 0 to 6.5V Voltage on Any Pin ...................................................................................................................... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) ...................................................................................................................... 2,000V NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. DC ELECTRICAL CHARACTERISTICS S24VP04, TA = -40°C to +85°C, VCC = 5V + 10% S24VP04-3, TA = -40°C to +85°C, VCC = 2.7V to 5.5V Symbol ICC ISB Parameter Supply Current (CMOS) Standby Current (CMOS) Conditions Min Max Units 3 mA VCC =3.3V 2 mA VCC =5.5V 50 VCC =3.3V 25 µA µA SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC VCC =5.5V SCL = SDA = VCC All other inputs = GND ILI Input Leakage VIN = 0 To VCC 10 µA ILO Output Leakage VOUT = 0 To VCC 10 µA VIL Input Low Voltage S0, S1, S2, SCL, SDA, RESET 0.3xVCC V VIH Input High Voltage S0, S1, S2, SCL, SDA VOL Output Low Voltage IOL = 3mA 0.4 V 0.7xVCC V 2008 PGM T1 1.0 AC ELECTRICAL CHARACTERISTICS S24VP04, TA = -40°C to +85°C, VCC = 5V + 10% S24VP04-3, TA = -40°C to +85°C, VCC = 2.7V to 5.5V Symbol Parameter Conditions 2.7V to 4.5V 4.5V to 5.5V Min Max Min 0 100 Max Units 400 KHz fSCL SCL Clock Frequency tLOW Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4.0 0.6 µs tBUF Bus Free Time 4.7 1.3 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tSU:STO Stop Condition Setup Time 4.7 0.6 µs tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 tR SCL and SDA Rise Time 1000 300 ns tF SCL and SDA Fall Time 300 300 ns tSU:DAT Data In Setup Time 250 100 ns tHD:DAT Data In Hold Time 0 0 ns TI Noise Spike Width @ SCL, SDA Inputs tWR Write Cycle Time Before New Transmission Noise Suppression Time Constant 3.5 0.2 0.9 µs µs 0.2 100 100 ns 10 10 ms 2008 PGM T2 1.0 9 2008 1.4 5/15/98 S24VP04 CAPACITANCE TA = 25°C, f = 100KHz Symbol CIN COUT Parameter Max Units Input Capacitance 5 pF Output Capacitance 8 pF 2008 PGM T3 1.0 tR tH IGH tLOW tSU:STO tF SCL tSU:SDA tHD:SDA tSU:DAT tHD:DAT tBUF SDA In tDH tAA SDA Out 2008 ILL 13 1.0 FIGURE 11. BUS TIMING VLOCK CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C S24VP04-2.7 Symbol S24VP04–A S24VP04–B Parameter Min Max Min Max Min Max Unit VLOCK Write Lockout Voltage Level 2.55 2.70 4.25 4.50 4.50 4.75 V tPUW Power-Up Write Delay 130 20 130 270 130 270 ms tLDLY Delay to VLOCKOUT 5 5 5 µs tGLITCH Glitch Filter 30 30 30 ns 2008 PGM T4 1.3 2008 1.4 5/15/98 10 S24VP04 tGLITCH VLOCK tPUW tLDLY tPUW tLDLY VCC Internal Action VLOCKOUT VLOCKOUT VLOCKOUT 2008 ILL 14 1.0 FIGURE 12. VLOCK OUTPUT TIMING 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. .030 (.762) TYP. 8 Places 1 .196 (5.00) .189 (4.80) FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 11 2008 1.4 5/15/98 S24VP04 8 Pin PDIP (Type P) Package .375 (9.525) .250 (6.350) PIN 1 INDICATOR .300 (7.620) .070 (1.778) .0375 (0.952) .015 (.381) Min. 5°-7°TYP. (4 PLCS) 0°-15° SEATING PLANE .130 (3.302) .060 ± .005 (1.524) ± .127 TYP. .100 (2.54) TYP. .130 (3.302) .018 (.457) TYP. .350 (8.89) .009 ± .002 (.229 ± .051) 8pn PDIP/P ILL.3 ORDERING INFORMATION S24VP04 P I -2.7 TE7 Tape and Reel Option TE7 = 500/reel TE13 = 2000/reel Base Part Number Package P = 8 Lead PDIP S = 8 Lead 150mil SOIC Operating Voltage Range A = 4.5V to 5.5V VLOCK Min. @ 4.25V B = 4.5V to 5.5V VLOCK Min. @ 4.50V 2.7 = 2.7V to 5.5V VLOCK Min. @ 2.55V Operating Temperature Range Blank = 0°C to +70°C I = -40°C to +85°C 2008 ILL15 1.0 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. I2C is a trademark of Philips Corporation. © Copyright 1998 SUMMIT Microelectronics, Inc. 2008 1.4 5/15/98 12