ETC X24CO4PC7187

X24C04
X24C04
4K
512 x 8 Bit
Serial E2PROM
FEATURES
DESCRIPTION
•
•
The X24C04 is a CMOS 4096 bit serial E2PROM,
internally organized 512 x 8. The X24C04 features a
serial interface and software protocol allowing operation on a simple two wire bus.
•
•
•
•
•
•
1.8V to 3.6V, 2.7V to 5.5V Power Supply Versions
Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 1.5 mA
—Standby Current Less Than 1 µA
Internally Organized 512 x 8
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
—Schmitt Trigger Input Noise Suppression
400Khz across VCC range
Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8 Pin Mini-DIP, 8 Pin SOIC, 8 pin MSOP and
8 pin TSSOP
The X24C04 is fabricated with Xicor’s advanced
CMOS Textured Poly Floating Gate Technology.
The X24C04 utilizes Xicor’s proprietary DirectWrite™
cell providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
(8) VCC
(4) VSS
(7) TEST
H.V. GENERATION
TIMING
& CONTROL
START CYCLE
(5) SD A
START
STOP
LOGIC
CONTROL
LOGIC
(6) SCL
SLAVE ADDRESS
REGISTER
+COMPARATOR
LOAD
(3) A 2
INC
E2 PROM
128 X 128
XDEC
WORD
ADDRESS
COUNTER
(2) A 1
(1) A 0
R/W
YDEC
8
CK
PIN
DATA REGISTER
DOUT
DOUT
ACK
ÓXicor, 1995, 1996 Patents Pending
6551-2.5 2/24/99 T1/C10/D0 NS
1
Characteristics subject to change without notice
X24C04
PIN CONFIGURATION
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
DIP/SOIC/MSOP
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the PullUp Resistor selection graph at the end of this data
sheet.
Write Protect (WP)
The write protect pin provides Hardware Write Protection.
When held low Hardware Write Protection is disabled;
when connected to VCC, the write protection feature is
enabled and the whole array is write-proptected.
PIN NAMES
Description
A0–A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
VSS
Ground
VCC
Supply Voltage
1
A1
2
A2
3
VSS
4
X24C04
8
VCC
7
WP
6
SCL
5
SDA
8-LEAD TSSOP
Address (A0, A1, A2)
A0 is a no connect. The Address inputs (A1, A2) are
used to set the appropriate bits of the seven bit slave
address. These inputs can be used static or actively
driven. If used statically they must be tied to VSS or
VCC as appropriate. If driven they must be driven to
VSS or to VCC.
Symbol
A0
2
WP
1
8
SCL
VCC
2
7
SDA
A0
3
6
VSS
A1
4
5
A2
X25138
X24C04
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
DEVICE OPERATION
The X24C04 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers, and provide the clock for both transmit and
receive operations. Therefore, the X24C04 will be
considered a slave in all applications.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The X24C04 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3
X24C04
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used by
the X24C04 to place the device in the standby power
mode after a read sequence. A stop condition can only
be issued after the transmitting device has released
the bus.
The X24C04 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the X24C04 will respond with an acknowledge
after the receipt of each subsequent eight bit word.
In the read mode the X24C04 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24C04
will continue to transmit data. If an acknowledge is not
detected, the X24C04 will terminate further data transmissions. The master must then issue a stop condition
to return the X24C04 to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
4
X24C04
DEVICE ADDRESSING
The last bit of the slave address defines the operation
to be performed. When set to one a read operation is
selected, when set to zero a write operation is
selected.
Following a start condition the master must output the
address of the slave it is accessing. The most significant four bits of the slave are the device type identifier
(see Figure 4). For the X24C04 this is fixed as
1010[B].
Following the start condition, the X24C04 monitors the
SDA bus comparing the slave address being transmitted with its slave address (device type and state of
A1 and A2 inputs). Upon a correct compare the X24C04
outputs an acknowledge on the SDA line. Depending
on the state of the R/W bit, the X24C04 will execute a
read or write operation.
Figure 4. Acknowledge Response From Receiver
DEVICE TYPE
INDENTIFIER
1
0
1
DEVICE
ADDRESS
0
A2
A1
HIGHER
ORDER
WORD
ADDRESS
A0
WRITE OPERATIONS
Byte Write
For a write operation, the X24C04 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 512 words of memory. Upon receipt of the word
address the X24C04 responds with an acknowledge,
and awaits the next eight bits of data, again
responding with an acknowledge. The master then
terminates the transfer by generating a stop condition,
at which time the X24C04 begins the internal write
cycle to the nonvolatile memory. While the internal
write cycle is in progress the X24C04 inputs are
disabled, and the device will not respond to any
requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
R/ W
The next two significant bits address a particular
device. A system could have up to four X24C04
devices on the bus (see Figure 10). The four addresses
are defined by the state of the A1 and A2 inputs.
The next bit of the slave address is an extension of the
array’s address and is concatenated with the eight bits
of address in the word address field, providing direct
access to the whole 512 x 8 array. Note: this bit is part
of word address. Not related to device address pin A0.
Figure 5. Byte Write
BUSS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE
S
BUSS ACTIVITY:
X24C04
WORD
ADDRESS
SLAVE
ADDRESS
DATA
S
T
O
P
P
A
C
K
A
C
K
5
A
C
K
X24C04
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Page Write
The X24C04 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte
write operation, but instead of terminating the write
cycle after the first data word is transferred, the master
can transmit up to fifteen more words. After the receipt
of each word, the X24C04 will respond with an
acknowledge.
Flow 1. ACK Polling Sequence
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
After the receipt of each word, the four low order
address bits are internally incremented by one. The
high order five bits of the address remain constant. If
the master should transmit more than sixteen words
prior to generating the stop condition, the address
counter will “roll over” and the previously written data
will be overwritten. As with the byte write operation, all
inputs are disabled until completion of the internal
write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
ISSUE
START
ISSUE SLAVE
ADDRESS AND R/W = 0
Acknowledge Polling
The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s
write operation the X24C04 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the
slave address for a write operation. If the X24C04 is still
busy with the write operation no ACK will be returned.
If the X24C04 has completed the write operation an
ACK will be returned and the host can then proceed
with the next read or write operation. Refer to Flow 1.
ACK
RETURNED?
ISSUE STOP
NO
YES
NEXT
OPERATION
A WRITE?
NO
YES
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address is set to a one. There are three basic
read operations: current address read, random read
and sequential read.
ISSUE BYTE
ADDRESS
ISSUE STOP
PROCEED
PROCEED
Figure 6. Page Write
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE
S
BUS ACTIVITY:
X24C04
SLAVE
ADDRESS
DATA n + 1
DATA n
WORD ADDRESS (n)
S
T
O
P
DATA n + 15
P
A
C
K
A
C
K
A
C
K
6
A
C
K
A
C
K
X24C04
Current Address Read
Internally the X24C04 contains an address counter
that maintains the address of the last word accessed,
incremented by one. Therefore, if the last access
(either a read or write) was to address n, the next read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to
one, the X24C04 issues an acknowledge and transmits the eight bit word. The read operation is terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
Figure 7 for the sequence of address, acknowledge
and data transfer.
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to
issuing the slave address with the R/W bit set to one,
the master must first perform a “dummy” write operation. The master issues the start condition, and the
slave address followed by the word address it is to
read. After the word address acknowledge, the master
immediately reissues the start condition and the slave
address with the R/W bit set to one. This will be
followed by an acknowledge from the X24C04 and
then by the eight bit word. The read operation is terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
Figure 8 for the address, acknowledge and data
transfer sequence.
Figure 7. Current Address Read
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE
S
SLAVE
ADDRESS
DATA
S
T
O
P
P
A
C
K
BUS ACTIVITY:
X24C04
Figure 8. Random Read
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C04
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
WORD
ADDRESS n
S
SLAVE
ADDRESS
DATA n
S
A
C
K
A
C
K
7
S
T
O
P
P
A
C
K
X24C04
Sequential Read
Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24C04 continues to
output data for each acknowledge received. The read
operation is terminated by the master; by not responding
with an acknowledge and by issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from n + 1. The
address counter for read operations increments all
address bits, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space (address 511), the counter “rolls over”
to address 0 and the X24C04 continues to output data
for each acknowledge received. Refer to Figure 9 for
the address, acknowledge and data transfer sequence.
Figure 9. Sequential Read
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
A
C
K
S
T
O
P
A
C
K
A
C
K
P
SDA LINE
BUS ACTIVITY:
X24C04
A
C
K
DATA n+1
DATA n
DATA n+2
DATA n+x
Figure 10. Typical System Configuration
VCC
PULL-UP
RESISTORS
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
8
MASTER
TRANSMITTER/
RECEIVER
X24C04
ABSOLUTE MAXIMUM RATINGS*
*COMMET
Temperature Under Bias .................. –65°C to +135°C
Storage Temperature........................ –65°C to +150°C
Voltage on any Pin with
Respect to VSS .......................... –1.0V to +7.0V
D.C. Output Current............................................5 mA
Lead Temperature
(Soldering, 10 Seconds) ........................... 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
0°C
70°C
X24C04-2.7
2.7V to 5.5V
Industrial
–40°C
+85°C
X24C04-1.8
1.8V to 3.6V
Military
–55°C
+125°C
Commercial
Supply Voltage
Limits
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified)
Limits
Symbol
Parameter
ICC1
Min.
Max.
VCC Supply Current (Read)
Units
1
Test Conditions
SCL = VCC x 0.1/Vd x 0.9 Levels @
100 KHz, SDA = Open, All Other
Inputs = GND or VCC – 0.3V
ICC2
VCC Supply Current (Write)
1.5
mA
ISB1(1)
VCC Standby Current
150
µA
SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC, VCC = 5.5V
ISB2(1)
VCC Standby Current
50
µA
SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC, VCC = 3V
ILI
Input Leakage Current
10
µA
VIN = GND to VCC
ILO
Output Leakage Current
10
µA
VOUT = GND to VCC
VlL(2)
Input Low Voltage
–1.0
VCC x
0.3
V
VIH(2)
Input High Voltage
VCC x
0.7
VCC +
0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 3 mA
CAPACITANCE TA = 25°C, F = 1.0MHZ, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
CI/O(3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN(3)
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
Notes: (1)
(2)
(3)
Must perform a stop command prior to measurement.
VIL min. and VIH max. are for reference only and are not tested.
This parameter is periodically sampled and not 100% tested.
9
X24C04
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input and Output
Timing Levels
VCC x 0.5
5.0V
1533W
Output
100pF
A.C. CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
400
KHz
fSCL
SCL Clock Frequency
0
TI
Noise Suppression Time Constant at SCL, SDA Inputs
50
td
SCL Low to SDA Data Out Valid
0.1
tBUF
Time the Bus Must Be Free Before a New Transmission Can Start
1.2
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tLOW
Clock Low Period
1.2
µs
tHIGH
Clock High Period
0.6
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
µs
tHD:DAT
Data In Hold Time
0
µs
tSU:DAT
Data In Setup Time
100
ns
tR
SDA and SCL Rise Time
300
µs
tF
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
0.6
tDH
Data Out Hold Time
50
ns
0.9
µs
µs
300
ns
POWER-UP TIMING
Symbol
Parameter
Max.
Units
tPUR(4)
Power-up to Read Operation
1
ms
tPUW(4)
Power-up to Write Operation
5
ms
Notes: (4)
tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
10
X24C04
Bus Timing
t HIGH
tF
t LOW
tR
SCL
tSU:STA
t HD:STA
tHD:DAT
t SU:DAT
t SU:STO
SDA IN
tAA
t DH
t BUF
SDA OUT
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Write Cycle Time
TWR(6)
Max.
5
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal erase/
program cycle. During the write cycle, the X24C04 bus
Units
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave address.
Write Cycle Timing
SCL
SDA
ACK
8th BIT
WORD n
t WR
STOP
CONDITION
Notes: (5)
(6)
START
CONDITION
Typical values are for TA = 25°C and nominal supply voltage (5V).
tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
120
RESISTANCE (KW)
X24C04
ADDRESS
V
RMIN = CC MAX =1.8KW
IOL MIN
t
RMAX = R
CBUS
MAX.
RESISTANCE
100
80
60
40
20
MIN.
RESISTANCE
0
0
20
40
60
80 100 120
BUS CAPACITANCE (pF)
11
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X24C04
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.060 (1.52)
0.020 (0.51)
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP .0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
12
X24C04
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50) X 45°
0.050" TYPICAL
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
0.030"
TYPICAL
8 PLACES
X24C04
PACKAGING INFORMATION
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) TYP
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
7° TYP
0.008 (0.20)
0.004 (0.10)
0.150 (3.81)
REF.
0.193 (4.90)
REF.
0.007 (0.18)
0.005 (0.13)
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
14
X24C04
PACKAGING INFORMATION
8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° Ð 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail ÒAÓ
NOTE:ALL DIMENSIONS IN INCHES (INARENTHESES
P
IN MILLIMETERS)
15
X24C04
ORDERING INFORMATION
X24C04
X
X
-X
VCC Range
2.7 = 2.7V to 5.5V
1.8 = 1.8V to 3.6V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
M = 8-Lead MSOP
V = 8-Lead TSSOP
S8 = 8-Lead SOIC
P = 8-Lead PDIP
Part Mark Convention
8-Lead MSOP
EYWW
XXX
AAA = 1.8 to 3.6V, 0 to +70°C
AAC = 1.8 to 3.6V, -40 to +85°C
AAO = 2.7 to 5.5V, 0 to +70°C
AAP = 2.7 to 5.5V, -40 to +85°C
8-Lead TSOP
8-Lead SOIC/PDIP
EYWW
2404XX
X24C04
XX
AG = 1.8 to 3.6V, 0 to +70°C
AH = 1.8 to 3.6V, -40 to +85°C
F = 2.7 to 5.5V, 0 to +70°C
G = 2.7 to 5.5V, -40 to +85°C
Blank = 8-Lead SOIC
P = 8-Lead PDIP
AG = 1.8 to 3.6V, 0 to +70°C
AH = 1.8 to 3.6V, -40 to +85°C
F = 2.7 to 5.5V, 0 to +70°C
G = 2.7 to 5.5V, -40 to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the
freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any
purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without
notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482;
4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
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