ICS162834 Integrated Circuit Systems, Inc. Advance Information 18-Bit 3.3V Registered Buffer Recommended Applications: • PC133 Registered Memory Module • PC motherboards • Servers and workstations • Provides complete PC133 DIMM solution with ICSVF2509, ICSVF2510 PLL. NC NC Y1 GND Y2 Y3 VDD Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VDD Y16 Y17 GND Y18 OE# LE# Product Features: • Meets JESD 82-2 specification • Internal series resistors to reduce switching noise • ±12 mA device capability • Low voltage operation - VDD = 3.3 ± 0.3V • 0.50 mm pitch, 56-Pin TSSOP package 1 Function Table Inputs Outputs OE# LE# CLK Ax Yx H X X X Z L L X L L L L X H H L H ↑ L L L H ↑ H H L H H X Y0(2) L H L X Y0(3) 2. 3. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND NC A1 GND A2 A3 VDD A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VDD A16 A17 GND A18 CLK GND 56-Pin TSSOP Notes: 1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS162834 Pin Configurations 6.10 mm. Body, 0.50 mm. pitch H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance ↑ = LOW-to-HIGH Transition Output level before the indicated steady-state input conditions were established, provided that CLK is HIGH before LE# went LOW. Output level before the indicated steady-state input conditions were established. Block Diagram OE# CLK LE# A1 Pin Description Pin Names OE# Output Enable Input (Active Low) CLK Clock Input LE# Latch Enable Input Ax Data Input Yx Data Outputs VDD Supply Voltage GND 1D C1 Description Ground Y1 CK To 17 Other Channels 0774—02/10/03 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICS162834 Advance Information General Description The ICS162834 low voltage 18-bit register combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Date flow is controlled by output-enable (OE#), latch enable (LE#), and clock (CLK) inputs. The device operates in transparent mode when LE# is held low. The device operates in clocked mode when LE# is high and CLK is toggled. Data transfers from the inputs (A[18:1]) to outputs (Y[18:1]) on a positive edge transition of the clock. When OE# is low, the output state is enabled. When OE# is high, the output port is in a high impedance state. The 18-bit registered buffer is designed to operate with a 3.0V to 4.6V supply voltage. All inputs support operation with standard LVTTL interface levels. This includes data inputs, clock inputs and control inputs. Device outputs meet the requirements of the PC133 Registered DIMM specification. The device functions as defined supports latched, registered and flow through modes of operations. The PC133 Specification requires only registered mode. Package is a 56 thin shrink small-outline package as defined by JEDEC Publication, JEP95, MO-153. 0774—02/10/03 2 ICS162834 Advance Information Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage (V DD) . . . . . . . . . . . . . . . . . . . Input Voltage (VI) . . . . . . . . . . . . . . . . . . . . . . . Output Voltage (VO) . . . . . . . . . . . . . . . . . . . . Input Clamp Current (IIK) . . . . . . . . . . . . . . . . Output Clamp Current (IOK) . . . . . . . . . . . . . . Continuous Output Current (IO) . . . . . . . . . . . VDD, VDDQ or GND Current/Pin . . . . . . . . . . . –65°C to + 150°C -0.5 to 4.6V -0.5 to 4.6V -0.5 to VDDQ + 0.5 50 mA ±50 mA ±50 mA ±100 mA Package Thermal Impedance, O JA . . . . . . . . . . . 64°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions DESCRIPTION PARAMETER Supply Voltage VDD Voltage Applied to input pins VIN Outputs enabled Voltage Applied to VOUT output or I/O pins Outputs high-Z Operating free-air temperature TA MIN 3.0 -0.3 0 0 0 TYP 3.3 Switching Characteristics Symbol t PLH, tPHL Parameter Propagation Delay CLK to Yx Output Skew* VCC = 3.3V ± 0.15V MIN MAX 1.8 3.5 UNITS ns t SK(0) 500 ps 150 MHz f CLOCK * Skew between any two putputs of the same package and switching in the same direction 0774—02/10/03 3 MAX 3.6 3.6 VDD VDD 70 ICS162834 Advance Information Electrical Characteristics - DC TA = 0 - 70° C; VDD = 3.3 ± 0.3V, VDDQ=3.3 ± 0.3V; (unless otherwise stated) SYMBOL PARAMETERS CONDITIONS V IH VIL VOH V OL II I OZ HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Low-level output voltage Input leakage current Off-state leakage current I OH = -12 mA, V IH = 2.0V I OL = 12 mA, VIL = 0.8V VI = VDD or GND VO = VDD or GND#, OE = V DD I DD Quiescent Supply Current VI = VDD or GND, I O = 0 VDD (V) MIN 3.0 - 3.6 3.0 - 3.6 3.0 3.0 3.0 - 3.6 2.0 TYP MAX UNITS 0.8 V V V 2.2 0.8 ±10 ±20 µA µA ±40 µA * Parameters are characterized over recommended operating conditions. Critical Register Specifications* SYMBOL PARAMETERS CONDITION VDD (V) MIN TYP MAX UNITS Propagation Delay (CK to Y) RL = 500 Ω, CL = 50 pF 3.0 - 3.6 1.4 3.5 ns tPD** tPD** Propagation Delay (CK to Y) RL = 500 Ω, CL = 30 pF 3.0 - 3.6 0.7 2.5 ns Setup time (A before CK) 3.0 - 3.6 1.0 ns tS tH Hold time (A after CK) 3.0 - 3.6 0.6 ns Clock input capacitance 3.0 - 3.6 3.3 4.0 6.0 pF CI * Parameters are characterized over recommended operating conditions. ** The t PD value in this table would equate to the 'Time-to-Vm' delay described in the post register timing specifications of the PC133 registered DIMM Specification. The first value applies to DIMMs with nine SDRAM loads per register output, and the second to DIMMs with eighteen SDRAM loads per register output. These values should serve as only an initial starting point, 0774—02/10/03 4 ICS162834 Advance Information Test Circuit and Switching Waveforms 2 x VDD Open GND RL Puls e Generator DUT CL RT RL Test Circuit Test circuit component values: RL = Load Resistor = 500 Ω CL = Load Capacitance and includes probe and jig capacitance RT = Termination resistance should be equal to ZOUT of Pulse Generator V IN = 0 to VDD t r = t f 2.0 ns (10% to 90%) unless otherwise specified. Parameter Tested Switch Position tPLH Open tPHL Open tPZH GND tPZL 2 x VDD tPHZ GND tPLZ 2 x VDD 0774—02/10/03 5 ICS162834 Advance Information PROPAGATION DELAY MEASUREMENT SETUP TIME MEASUREMENTS VIH An VIH An VIL tS VIH CK tPLH VIL tS VIH CK VIL tPHL VIL VOH VOH Yn Yn VOL VOL ENABLE AND DISABLE TIMES HOLD TIME MEASUREMENTS DISABLE ENABLE VIH An tH CONTROL INPUT VIL tH tPZL VIH CK OUTPUT SW ITCH NORM ALLY CLOSE D LOW tPZH OUTPUT SW ITCH NORM ALLY OPEN HIGH VIL VOH Yn VOL tPLZ V IH VT 0V V LOAD /2 V LOAD /2 VT V LZ V OL tPH Z VT V OH V HZ 0V 0V NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. OUTPUT SKEW - PULSE WIDTH tSK(X) V IH INPUT VT 0V tPH L1 tPLH1 LOW -HIGH-LOW PULSE V OH OUTPUT 1 tSK (x) tSK (x) tW VT V OL HIGH-LOW -HIGH PULSE V OH VT V OL OUTPUT 2 tPLH2 VT tPH L2 tSK (x) = t PLH2 - tP LH1 or tPH L2 - tP HL1 NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 Switching Waveforms 0774—02/10/03 6 VT ICS162834 Advance Information c N L E1 INDEX AREA E 1 2 D A A2 A1 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° α aaa -0.10 -.004 -Ce SEATING PLANE b VARIATIONS N aaa C 56 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 Reference Doc.: JEDEC Publication 95, M O-153 10-0039 Ordering Information ICS162834AG-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0774—02/10/03 7 MAX .555