ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843001I-22 is a a highly versatile, low phase noise LVPECL/LVCMOS Synthesizer HiPerClockS™ which can generate low jitter reference clocks for a variety of communications applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. The dual crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel using a 25.5625MHz cr ystal). The r ms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET and 10Gb Ethernet. The ICS843001I-22 is packaged in a small 24-pin TSSOP package. • One 3.3V or 2.5V LVPECL output pair and one LVCMOS/LVTTL output ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • VCO range: 490MHz - 640MHz • Output frequency range: 490MHz - 640MHz • Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV • RMS phase jitter @ 125MHz (1.875MHz - 20MHz): 0.5ps (typical) • Full 3.3V or 2.5V supply modes • -40°C to 85°C ambient operating temperature • Available in both, Standard and RoHS/Lead-Free compliant packages CONTROL INPUT FUNCTION TABLE Control Input Outputs OE Q/nQ REF_OUT 0 High-Z High-Z 1 High-Z Active FLOAT Active High-Z PIN ASSIGNMENT VCCO_LVCMOS N0 N1 N2 VCCO _LVPECL Q nQ V EE V CCA VCC XTAL_OUT1 XTAL_IN1 BLOCK DIAGRAM 3 N2:N0 SEL0 Pulldown N XTAL_IN0 00 11 XTAL_OUT0 XTAL_IN1 OSC 01 Phase Detector 10 01 00 VCO 490MHz -640MHz XTAL_OUT1 CLK MR M2:M0 Pulldown 24 23 22 21 20 19 18 17 16 15 14 13 REF_OUT VEE OE M2 M1 M0 MR SEL1 SEL0 CLK XTAL_IN0 XTAL_OUT0 ICS843001I-22 SEL1 Pulldown OSC 1 2 3 4 5 6 7 8 9 10 11 12 10 11 000 001 010 011 100 101 000 001 010 011 ÷1 ÷2 ÷3 ÷4 (default) 100 101 110 111 ÷5 ÷6 ÷8 ÷10 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View Q nQ M ÷18 ÷22 ÷24 ÷25 ÷32 (default) ÷40 Pulldown 3 REF_OUT OE 843001AGI-22 Pullup/Pulldown www.icst.com/products/hiperclocks.html 1 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1, 5 VCCO_LVCMOS, VCCO_LVPECL Type Description Power 2, 3 N0, N1 Input 4 N2 Input Pullup Output divider select pins. Default value = ÷4. Pulldown LVCMOS/LVTTL interface levels. See Table 3C. Output supply pins. 6, 7 Q, nQ Ouput Differential output pair. LVPECL interface levels. 8, 23 VEE Power Negative supply pin. 9 VCCA Power Analog supply pin. 10 11 12 13 14 15 VCC XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 CLK Power 16, 17 SEL0, SEL1 Input 18 MR Input 19, 20 M0, M1 Input 21 M2 Input 22 OE Input 24 REF_OUT Output Input Input Input Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown LVCMOS/LVTTL clock input. Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inver ted output nQ Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Feedback divider select pins. Default value = ÷32. LVCMOS/LVTTL interface levels. See Table 3B. Pullup 3-State clock output enable, (High/Low/Float). See page 1, Control Input Function Table. Reference clock output. LVCMOS/LVTTL interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ Rout Output Impedance 15 Ω 843001AGI-22 Test Conditions Minimum REF_CLK www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 3A. COMMON CONFIGURATIONS TABLE Input Reference Clock (MHz) M Divider Value N Divider Value VCO (MHz) Output Frequency (MHz) Application 22 8 594 74.25 HDTV 27 22.4 25 8 560 70 24.75 24 8 59 4 74.25 HDTV 25 24 3 60 0 200 Processor 14.8351649 40 8 593.4066 74.1758245 HDTV 19.44 32 4 622.08 155.52 SONET 19.44 32 8 622.08 77.76 SONET 19.44 32 1 622.08 622.08 SONET 19.44 32 2 622.08 311.04 SONET 19.53125 32 4 625 156.25 10 GigE 20 25 2 500 250 Ethernet 25 25 5 625 125 1 GigE 25 25 10 625 62.5 1 GigE 25 24 6 60 0 100 PCI Express 25 24 4 600 150 SATA 25 24 8 60 0 75 SATA 26.5625 24 6 637.5 106.25 Fibre Channel 1 26.5625 24 3 637.5 212.5 4 Gig Fibre Channel 26.5625 24 4 637.5 159.375 10 Gig Fibre Channel 31.25 18 3 562.5 187.5 12 Gig Ethernet TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER FUNCTION TABLE TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER FUNCTION TABLE Inputs M2 M1 M0 M Divider Value 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 Inputs Input Frequency (MHz) N Divide Value Minimum Maximum N2 N1 N0 18 27.22 35.56 0 0 0 1 22 22.27 29.09 0 0 1 2 0 24 20.41 26.67 0 1 0 3 25 19.6 25.6 0 1 1 32 15.31 20 1 0 0 5 40 12.25 16 1 0 1 6 1 1 0 8 1 1 1 10 1 4 (default) TABLE 3D. BYPASS MODE FUNCTION TABLE Inputs SEL1 SEL0 Reference Input PLL Mode 0 0 XTAL0 Active 0 1 XTAL1 Active 1 0 CLK Active 1 1 CLK Bypass 843001AGI-22 www.icst.com/products/hiperclocks.html 3 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL= 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.97 3.3 3.63 V VCCA Analog Supply Voltage 2.97 3. 3 3.63 V VCCO_LVPECL, VCCO_LVCMOS Output Supply Voltage 2.97 3. 3 3.63 V IEE Power Supply Current 160 mA ICCO Output Supply Current 8 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V VCCO_LVPECL, Output Supply Voltage VCCO_LVCMOS 2.375 2.5 2.625 V IEE Power Supply Current 155 mA ICCO Output Supply Current 8 mA 843001AGI-22 www.icst.com/products/hiperclocks.html 4 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIM Input Medium Voltage VIL Input Low Voltage IIH Input High Current IIM IIL Minimum Typical Units 2 VCC + 0.3 V VCC = 2.5V ± 5% 1.7 VCC + 0.3 V V V CLK, SEL0, SEL1, MR, M0, M1, N2, OE VCC = 3.3V ± 10% -0.3 0.8 V VCC = 2.5V ± 5% VCC = VIN = 3.63V -0.3 0.7 V 150 µA 5 µA or 2.625V VCC = VIN = 3.63V or 2.625V M2, N0, N1 Input Medium Current Input Low Current µA VCC = 3.63V or 2.625V, CLK, SEL0, SEL1, MR, M0, M1, N2, OE VIN = 0V VCC = 3.63V or 2.625V, M2, N0, N1, OE VOH Maximum VCC = 3.3V ± 10% VIN = 0V VCCO_LVCMOS = 3.63V Output High Voltage; NOTE 1 -5 µA -150 µA 2.6 V VCCO_LVCMOS = 2.625V 1.8 VCCO_LVCMOS = 3.63V VOL Output Low Voltage: Note 1 or 2.625V NOTE 1: Outputs terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section, "Output Load Test Circuit Diagram". V 0.5 V TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1. 0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 14 MHz 35.55 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant crystal. 843001AGI-22 www.icst.com/products/hiperclocks.html 5 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL= 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter fIN Input Frequency CL K Test Conditions Minimum Maximum Units SEL1 = 1, SEL0 = 0 14 Typical 35.55 MHz SEL1 = 1, SEL0 = 0 DC 250 MHz Maximum Units 640 MHz TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter fOUT fVCO Output Frequency RMS Phase Jitter, (Random); NOTE 1 PLL VCO Lock Range t R / tF Output Rise/Fall Time tjit(Ø) Test Conditions Minimum Typical 49 125MHz (1.875MHz - 20MHz) Q/nQ REF_OUT Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Phase jitter using a cr ystal interface. 0.5 20% to 80% ƒ≤ 250MHz ps 490 640 MHz 200 500 ps 200 700 ps 45 44 55 56 % % Maximum Units 640 MHz TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL= 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter, (Random); NOTE 1 PLL VCO Lock Range tjit(Ø) fVCO t R / tF Output Rise/Fall Time Test Conditions Typical 49 125MHz (1.875MHz - 20MHz) Q/nQ REF_OUT Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Phase jitter using a cr ystal interface. 843001AGI-22 Minimum 20% to 80% ƒ≤ 250MHz www.icst.com/products/hiperclocks.html 6 0.5 ps 490 640 MHz 200 500 ps 300 800 ps 45 44 55 56 % % REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ ➤ 0 -10 10Gb Ethernet Filter -20 -30 125MHz -40 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.5ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -50 -120 -130 -140 ➤ -150 -160 Phase Noise Result by adding a 10Gb Ethernet Filter to raw data -170 -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843001AGI-22 www.icst.com/products/hiperclocks.html 7 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65±10% 2V VCC, VCCA, VCCO_LVPECL SCOPE Qx SCOPE VCC, VCCA, VCCO_LVCMOS LVPECL Qx LVCMOS nQx VEE VEE -1.3V±0.33V -1.65V±10% 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 2V 1.25V±5% VCC, VCCA, VCCO_LVPECL Qx SCOPE SCOPE VCC, VCCA, VCCO_LVCMOS LVPECL Qx LVCMOS nQx VEE VEE -0.5V ± 0.125V -1.25V±5% 2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot V CCO_LVCMOS 2 Noise Power REF_OUT t PW t Phase Noise Mask odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER 843001AGI-22 LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 8 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER nQ 80% Q t PW t odc = Clock Outputs PERIOD t PW 80% 20% 20% tR tF x 100% t PERIOD LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% LVCMOS OUTPUT RISE/FALL TIME 80% VSW I N G Clock Outputs 20% 20% tR tF LVPECL OUTPUT RISE/FALL TIME 843001AGI-22 www.icst.com/products/hiperclocks.html 9 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843001I-22 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VCCA. 3.3V or 2.5V VCC .01μF 10 Ω V CCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS843001I-22 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS843001I-22 ICS84332 Figure 2. CRYSTAL INPUt INTERFACE 843001AGI-22 www.icst.com/products/hiperclocks.html 10 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 843001AGI-22 FIN 50Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 11 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE 843001AGI-22 www.icst.com/products/hiperclocks.html 12 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843001I-22. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843001I-22 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 160mA = 554.4mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 554.4mW + 30mW = 584.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.584W * 65°C/W = 123°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843001AGI-22 0 1 2.5 70°C/W 65°C/W 62°C/W www.icst.com/products/hiperclocks.html 13 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V OL_MAX CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CCO_MAX CCO_MAX OH_MAX OH_MAX CCO_MAX OH_MAX L CCO_MAX L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843001AGI-22 www.icst.com/products/hiperclocks.html 14 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843001I-22 is: 3881 843001AGI-22 www.icst.com/products/hiperclocks.html 15 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 24 LEAD TSSOP TABLE 10. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843001AGI-22 www.icst.com/products/hiperclocks.html 16 REV. A AUGUST 1, 2005 ICS843001I-22 Integrated Circuit Systems, Inc. FEMTOCLOCKS™CRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843001AGI-22 ICS843001AI22 24 Lead TSSOP tube -40°C to 85°C ICS843001AGI-22T ICS843001AI22 24 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS843001AGI-22LF ICS43001AI22L 24 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS843001AGI-22LFT ICS43001AI22L 24 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843001AGI-22 www.icst.com/products/hiperclocks.html 17 REV. A AUGUST 1, 2005