ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843004I-04 is a 4 output LVPECL Synthesizer optimized to generate clock HiPerClockS™ frequencies for a variety of high performance applications and is a member of the HiPerClocks TM family of high perfor mance clock solutions from ICS. This device can select its input reference clock from either a crystal input or a singleended clock signal. It can be configured to generate 4 outputs with individually selectable divide-by-one or divide-by-four function via the 4 frequency select pins ( F _ S E L [ 3 : 0 ] ) . T h e I C S 8 4 3 0 0 4 I - 0 4 u s e s I C S ’ 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical r ms phase jitter. This ensures that it will easily meet clocking requirements for SDH (STM-1/STM-4/STM-16) and SONET (OC-3/ OC12/OC-48). This device is suitable for multi-rate and multiple port line card applications. The ICS843004I-04 is conveniently packaged in a small 24-pin TSSOP package. • Four LVPECL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following applications: SONET/SDH, SATA, or 10Gb Ethernet • Output frequency range: 140MHz - 170MHz, 560MHz - 680MHz • VCO range: 560MHz - 680MHz • Crystal oscillator and CLK range: 17.5MHz - 21.25MHz • RMS phase jitter @ 622.08MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.82ps (typical) • RMS phase jitter @ 156.25MHz output, using a 19.53125MHz crystal (1.875MHz - 20MHz): 0.57ps (typical) • RMS phase jitter @ 155.52MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.94ps (typical) • Full 3.3V supply mode • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages PIN ASSIGNMENT BLOCK DIAGRAM XTAL_IN OSC 0 ÷1 0 ÷4 1 XTAL_OUT CLK Pulldown 1 Phase Detector VCO Q0 nQ0 INPUT_SEL Pulldown M = ÷32 MR F_SEL0 Pulldown Pullup 0 Q1 1 nQ1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 V EE F_SEL2 INPUT_SEL CLK V EE XTAL_IN XTAL_OUT ICS843004I-04 F_SEL1 Pullup F_SEL2 nQ1 Q1 VCCo Q0 nQ0 MR F_SEL3 nc V CCA F_SEL0 VCC F_SEL1 0 Q2 1 nQ2 0 Q3 1 nQ3 Pullup 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View F_SEL3 Pullup 843004AGI-04 www.icst.com/products/hiperclocks.html 1 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 VCCO Power Output supply pins. 4, 5 Q0, nQ0 Ouput 6 MR Input 7, 10, 12, 18 8 F_SEL3, F_SEL0, F_SEL1, F_SEL2 nc Unused 9 VCCA Power Analog supply pin. 11 Power 15, 19 VCC XTAL_OUT, XTAL_IN VEE Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Negative supply pins. 16 CLK Input 17 INPUT_SEL Input 20, 21 nQ3, Q3 Output 23, 24 Q2, nQ2 Output 13, 14 Type Description Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Input Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3. No connect. Input Power Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or CLK inputs as the the PLL Reference source. Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ TABLE 3. OUTPUT CONFIGURATION Inputs AND Minimum Maximum Units FREQUENCY RANGE FUNCTION TABLE Output Frequency (MHz) F_SELx XTAL (MHz) VCO (MHz) 0 19.44 622.08 ÷1 622.08 1 19.44 622.08 ÷4 155.52 Divider Value Q0/nQ0:Q3/nQ3 0 18.75 600 ÷1 60 0 1 18.75 600 ÷4 150 0 19.53125 625 ÷1 625 1 19.53125 625 ÷4 156.25 0 20.141601 644.5312 ÷1 644.5312 1 20.141601 644.5312 ÷4 161.13 843004AGI-04 Typical www.icst.com/products/hiperclocks.html 2 Application SONET/SDH SATA 10 Gigabit Ethernet 10 Gigabit Ethernet 66B/64B FEC REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 70°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 120 mA ICCA Analog Supply Current 10 mA ICCO Output Supply Current 120 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical 2 -0.3 Maximum VCC + 0.3 Units V 0.8 V CLK, MR, INPUT_SEL VCC = VIN = 3.465 150 µA F_SEL0:F_SEL3 VCC = VIN = 3.465 5 µA CLK, MR, INPUT_SEL VCC = 3.465V, VIN = 0V -5 µA F_SEL0:F_SEL3 VCC = 3.465V, VIN = 0V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. 843004AGI-04 www.icst.com/products/hiperclocks.html 3 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 21.25 MHz Fundamental Frequency 17.5 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 1, 2, 3 tjit(Ø) t R / tF RMS Phase Jitter (Random); NOTE 4 Output Rise/Fall Time Test Conditions Minimum Maximum Units Output Divider = ÷1 560 680 MHz Output Divider = ÷4 140 170 MH z 75 ps 155.52MHz, Integration Range: 12kHz - 20MHz 156.25MHz, Integration Range: 1.875MHz - 20MHz 622.08MHz, Integration Range: 12kHz - 20MHz 20% to 80% Typical 0.94 ps 0.57 ps 82 ps 175 Output Divider = ÷4 48 Output Divider = ÷1 40 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Output skew measurements taken with all outputs in the same divide configuration. NOTE 4: Please refer to the Phase Noise Plot. odc 843004AGI-04 Output Duty Cycle www.icst.com/products/hiperclocks.html 4 675 ps 52 60 % % REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V VCCA = 2V nQx Qx VCC, VCCO Qx SCOPE nQy Qy LVPECL tsk(o) nQx VEE -1.3V±0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Noise Power Phase Noise Plot Phase Noise Mask 80% 80% VSW I N G f1 Offset Frequency Clock Outputs f2 20% 20% tR tF RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT RISE/FALL TIME nQ0:nQ3 Q0:Q3 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843004AGI-04 www.icst.com/products/hiperclocks.html 5 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843004I-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VCCA. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS843004I-04 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.44MHz, XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 843004AGI-04 www.icst.com/products/hiperclocks.html 6 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 843004AGI-04 www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 843004AGI-04 125Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER SCHEMATIC EXAMPLE recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R2, C3 and C4 should also be located as close to the VCCA pin as possible. Figure 5 shows a schematic example for ICS843004I-04. In this example, the input is a 19.44MHz parallel resonant crystal with load capacitor CL=18pF. The 22pF frequency fine tuning capacitors are used C1 and C2. This example also shows general logic control input handling. For decoupling capacitors, it is MR F_SEL3 VCC VCCA R2 10 3.3V C3 10uF C4 0.01u R3 133 VCCO VCC Logic Control Input Examples Set Logic Input to '0' VDD Zo = 50 Ohm XTAL_OUT XTAL_IN VEE CLK INPUT_SEL F_SEL2 VEE nQ3 Q3 VCCO Q2 nQ2 To Logic Input pins RD2 1K (U1-11) - U1 R4 82.5 843004i-04 R6 82.5 VCC=3.3V VCCO=3.3V 13 14 15 16 17 18 19 20 21 22 23 24 RD1 Not Install VCC F_SEL1 RU2 Not Install To Logic Input pins (U1-3) + F_SEL1 VCC F_SEL0 VCCA NC F_SEL3 MR nQ0 Q0 VCCO Q1 nQ1 RU1 1K F_SEL0 12 11 10 9 8 7 6 5 4 3 2 1 Set Logic Input to '1' VDD R5 133 Zo = 50 Ohm (U1-22) Zo = 50 Ohm C1 0.1uF C2 0.1uF + C3 0.1uF Zo = 50 Ohm C2 22pF X1 19.44MHz 18pF VCC VCCO R5 50 R6 50 C1 22pF Q1 Ro ~ 7 Ohm R8 Optional Y-Termination Zo = 50 Ohm R7 50 43 Driv er_LVCMOS INPUT_SEL F_SEL2 FIGURE 5. ICS844004I-04 SCHEMATIC EXAMPLE 843004AGI-04 www.icst.com/products/hiperclocks.html 9 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843004I-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843004I-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 415.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 415.8 + 120mW = 535.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming an air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.536W * 65°C/W = 119.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843004AGI-04 0 1 2.5 70°C/W 65°C/W 62°C/W www.icst.com/products/hiperclocks.html 10 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (V CC_MAX • -V OH_MAX ) = 0.9V For logic low, VOUT = V OL_MAX =V – 1.7V CC_MAX (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V ) = [(2V - (V OL_MAX CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843004AGI-04 www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843004I-04 is: 2273 843004AGI-04 www.icst.com/products/hiperclocks.html 12 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER 24 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843004AGI-04 www.icst.com/products/hiperclocks.html 13 REV. A FEBRUARY 15, 2006 ICS843004I-04 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843004AGI-04 ICS843004AI04 24 Lead TSSOP tube -40°C to 85°C ICS843004AGI-04T ICS843004AI04 24 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS843004AGI-04LF ICS43004AI04L 24 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS843004AGI-04LFT ICS43004AI04L 24 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843004AGI-04 www.icst.com/products/hiperclocks.html 14 REV. A FEBRUARY 15, 2006