ICS ICS843002AGILFT

ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843002I is a 2 output LVPECL synthesizer
optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The ICS843002I uses ICS’ FemtoClockTM low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS843002I is packaged in a small 20-pin
TSSOP package.
• Two 3.3V or 2.5V LVPECL outputs
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @212.5MHz (2.55MHz - 20MHz):
0.50ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PIN ASSIGNMENT
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
26.5625
Inputs
M Divider
F_SEL1 F_SEL0
Value
0
0
24
N Divider
Value
3
M/N
Divider Value
8
Output
Frequency
(MHz)
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125
23.4375
0
0
24
3
8
187.5
nPLL_SEL
2
Pulldown
1
1
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
20
19
18
17
16
15
14
13
12
11
VCCO
Q1
nQ1
VEE
VCC
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
ICS843002I
Q0
F_SEL[1:0]
REF_CLK Pulldown
1
2
3
4
5
6
7
8
9
10
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nc
VCCO
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCC
0
Phase
Detector
VCO
637.5MHz
00
01
10
11
÷3
÷4
÷6
÷12
0
(w/26.5625MHz
Reference)
nQ0
Q1
nQ1
nXTAL_SEL Pulldown
M = 24 (fixed)
MR Pulldown
843002AGI
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1
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 7
nc
Unused
2, 20
VCCO
Power
3, 4
Q0, nQ0
Ouput
5
MR
Input
6
nPLL_SEL
Input
8
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Power
14
VCCA
F_SEL0,
F_SEL1
VCC
XTAL_OUT,
XTAL_IN
REF_CLK
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pulldown
LVCMOS/LVTTL interface levels.
Analog supply pin.
15
nXTAL_SEL
Input
17
VEE
Power
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between cr ystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Negative supply pins.
18, 19
nQ1, Q1
Output
9, 11
10, 16
12, 13
Type
Input
Input
Description
No connect.
Output supply pins.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
843002AGI
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.97
3.3
3.63
V
VCCA
Analog Supply Voltage
2.97
3.3
3.63
V
VCCO
Output Supply Voltage
2.97
3.3
3.63
V
IEE
Power Supply Current
130
mA
ICCA
Analog Supply Current
13
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VCC
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.375
2.5
2.625
V
Analog Supply Voltage
2.375
2.5
2.625
V
VCCO
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
115
mA
ICCA
Analog Supply Current
12
mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
843002AGI
Test Conditions
VCC = 3.3V
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Minimum Typical
2
Maximum
VCC + 0.3
Units
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
150
µA
VCC = VIN = 3.63V or 2.625V
VCC = 3.63V or 2.625V,
VIN = 0V
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3
-150
µA
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1. 0
V
Maximum
Units
28.33
MHz
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
23.33
26.5625
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
226.67
MH z
NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] =11
46.67
56.67
MHz
30
ps
212.5MHz, (2.55MHz - 20MHz)
0.50
ps
159.375MHz, (1.875MHz - 20MHz)
0.54
ps
106.25MHz, (637kHz - 5MHz)
0.68
ps
53.125MHz, (637kHz - 5MHz)
20% to 80%
0.70
350
F_SEL[1:0] ≠ 00
49
F_SEL[1:0] = 00
43
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using crystal input.
odc
843002AGI
Output Duty Cycle
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4
ps
650
ps
51
57
%
%
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
fOUT
tsk(o)
tjit(Ø)
t R / tF
Parameter
Output Frequency
Test Conditions
Minimum
Typical
F_SEL[1:0] = 00
186.67
226.67
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] =11
46.67
56.67
MHz
30
ps
Output Skew; NOTE 1, 2
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Units
212.5MHz, (2.55MHz - 20MHz)
0.50
159.375MHz, (1.875MHz - 20MHz)
0.55
ps
106.25MHz, (637kHz - 5MHz)
0.75
ps
53.125MHz, (637kHz - 5MHz)
0.76
ps
20% to 80%
350
F_SEL[1:0] ≠ 00
49
odc
Output Duty Cycle
F_SEL[1:0] = 00
43
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using crystal input.
843002AGI
Maximum
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5
ps
650
ps
51
57
%
%
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
AT
212.5MHZ @ 3.3V
0
-10
-20
-30
212.5MHz
-40
-50
➤
-60
-70
-80
Fibre Channel Jitter Filter
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
RMS Phase Jitter (Random)
2.55MHz to 20MHz = 0.50ps (typical)
-120
-130
➤
-140
-150
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843002AGI
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6
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
Qx
V CC ,
VCCA, VCCO
LVPECL
SCOPE
Qx
V CC ,
VCCA, VCCO
LVPECL
nQx
nQx
VEE
VEE
-1.3V ± 0.33V
-0.5V ± 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
REF_CLK
Qx
nQy
nQ0, nQ1
Qy
Q0, Q1
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
Phase Noise Plot
nQ0, nQ1
Noise Power
Q0, Q1
t PW
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
843002AGI
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7
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VCCA. The 10Ω resistor can also be replaced by a ferrite bead.
3.3V or 2.5V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
843002AGI
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REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
below were determined using a 26.5625MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS843002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
ICS843002I
Figure 2. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
843002AGI
FIN
50Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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9
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in Figure 4C.
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
-
2,5V LVPECL
Driv er
2,5V LVPECL
Driv er
R2
62.5
R1
50
R4
62.5
R2
50
R3
18
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
843002AGI
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10
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
18pF parallel resonant 26.5625MHz crystal is used. The
C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be
slightly adjusted for optimizing frequency accuracy.
Figure 5A shows a schematic example of the ICS843002I. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an
3.3V
VCC
VCCA
R2
10
R3
133
R5
133
Zo = 50 Ohm
C3
10uF
C4
0.01u
+
VCC
VCCO
C6
0.1u
RD1
Not Install
R6
82.5
VCC=3.3V
F_SEL1
XTAL_OUT
XTAL_IN
REF_CLK
nXTAL_SEL
VCC
VEE
nQ1
Q1
VCCO
RU2
Not Install
To Logic
Input
pins
-
R4
82.5
ICS843002i
To Logic
Input
pins
VCCO=3.3V
Zo = 50 Ohm
+
11
12
13
14
15
16
17
18
19
20
RU1
1K
Set Logic
Input to
'0'
VCC
U1
VCC
F_SEL0
VCCA
nc
nPLL_SEL
MR
nQ0
Q0
VCCO
nc
Set Logic
Input to
'1'
VCC
Zo = 50 Ohm
C7
0.1u
10
9
8
7
6
5
4
3
2
1
Logic Control Input Examples
RD2
1K
Zo = 50 Ohm
VCCO
C8
0.1u
R7
50
C2
33pF
X1
26.5625MHz
18pF
R8
50
VCC
ICS843002I
R9
50
C9
0.1u
C1
27pF
Optional Termination
FIGURE 5A. ICS843002I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 5B shows an example of ICS843002I P.C. board layout.
The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5, C6, C7, C8
0603
R2
0603
NOTE: Table 6, lists component sizes
shown in this layout example.
FIGURE 5B. ICS843002I PC BOARD LAYOUT EXAMPLE
843002AGI
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11
REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 130mA = 471.9mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.532W * 66.6°C/W = 120.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843002AGI
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REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
CCO_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CCO_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843002AGI
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REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843002I is: 2578
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REV. A JANUARY 4, 2006
ICS843002I
Integrated
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Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
FOR
20 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843002AGI
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REV. A JANUARY 4, 2006
ICS843002I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843002AGI
ICS843002AGI
20 Lead TSSOP
tube
-40°C to 85°C
ICS843002AGIT
ICS843002AGI
20 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS843002AGILF
ICS843002AGILF
20 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS843002AGILFT
ICS843002AGILF
20 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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