ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85210-31 is a low skew, high perforICS mance dual 1-to-5 Differential-to-HSTL Fanout HiPerClockS™ Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLKx, nCLKx pairs can accept most standard differential input levels. The ICS85210-31 is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS85210-31 ideal for those clock distribution applications demanding well defined performance and repeatability. • Dual 1-to-5 HSTL compatible bank outputs • 2 selectable differential clock input pairs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVHSTL levels with resistor bias on nCLKx inputs • Output skew: 50ps (maximum) • Part-to-part skew: 350ps (maximum) • Propagation delay: 2ns (maximum) • 3.3V core, 1.8V output operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT QA4 nQA4 QB0 nQB0 VDD 1 24 QA3 CLK0_EN 2 23 nQA3 CLK0 3 22 QA4 nCLK0 4 21 nQA4 CLK1_EN 5 20 QB0 CLK1 6 19 nQB0 nCLK1 7 18 QB1 GND 8 17 nQB1 VDDO QB2 nQB2 QB3 nQB3 QB4 LE QB2 nQB2 nQB4 Q VDDO D ICS85210-31 9 10 11 12 13 14 15 16 QB1 nQB1 CLK1_EN VDDO 32 31 30 29 28 27 26 25 QA2 nQA2 QA3 nQA3 CLK1 nCLK1 nQA2 LE QA2 Q nQA1 D QA1 CLK0_EN nQA0 QA1 nQA1 QA0 VDDO QA0 nQA0 CLK0 nCLK0 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View QB3 nQB3 QB4 nQB4 85210AY-31 www.icst.com/products/hiperclocks.html 1 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD Power Type Description Core supply pin. 2 CLK0_EN Pullup 3 CLK0 Input Pullup Synchronizing clock enable. 4 nCLK0 Input 5 CLK1_EN Pullup 6 CLK1 Input 7 nCLK1 Input 8 9, 16, 25, 32 10, 11 GND Power Power supply ground. VDDO Power Output supply pins. nQB4, QB4 Output Differential output pair. HSTL interface levels. 12, 13 nQB3, QB3 Output Differential output pair. HSTL interface levels. 14, 15 nQB2, QB2 Output Differential output pair. HSTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pullup Synchronizing clock enable. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. 17, 18 nQB1, QB1 Output Differential output pair. HSTL interface levels. 19, 20 nQB0, QB0 Output Differential output pair. HSTL interface levels. 21, 22 nQA4, QA4 Output Differential output pair. HSTL interface levels. 23, 24 nQA3, QA3 Output Differential output pair. HSTL interface levels. 26, 27 nQA2, QA2 Output Differential output pair. HSTL interface levels. 28, 29 nQA1, QA1 Output Differential output pair. HSTL interface levels. 30, 31 nQA0, QA0 Output Differential output pair. HSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 85210AY-31 www.icst.com/products/hiperclocks.html 2 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK0_EN, CLK1_EN QA0:QA4, QB0:QB4 nQA0:QA4, nQB0: nQB4 0 Disabled; LOW Disabled; HIGH 1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described in Table 3B. Enabled Disabled nCLK0, nCLK1 CLK0, CLK1 CLK0_EN, CLK1_EN nQA0:nQA4, nQB0:nQB4 QA0:QA4, QB0:QB4 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs nQA0:nQA4, nQB0:nQB4 HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting LOW Differential to Differential Non Inver ting LOW HIGH Single Ended to Differential Non Inver ting HIGH LOW Single Ended to Differential Non Inver ting HIGH LOW Single Ended to Differential Inver ting LOW HIGH Single Ended to Differential Inver ting CLK0 or CLK1 nCLK0 or nCLK1 0 0 QA0:QA4, QB0:QB4 LOW 1 1 HIGH 0 Biased; NOTE 1 1 Biased; NOTE 1 Biased; NOTE 1 0 Biased; NOTE 1 1 NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 85210AY-31 www.icst.com/products/hiperclocks.html 3 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions VDD Input Power Supply Voltage VDDO Output Power Supply Voltage IDD Power Supply Current IDDO Output Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.4 1.8 2.0 V 120 mA No Load 0 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage CLK0_EN, CLK1_EN 2 VDD + 0.3 V VIL Input Low Voltage CLK0_EN, CLK1_EN -0.3 0.8 V IIH Input High Current CLK0_EN, CLK1_EN VDD = VIN = 3.465V 5 µA IIL Input Low Current CLK0_EN, CLK1_EN VDD = 3.465V, VIN = 0V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions nCLK0, nCLK1 CLK0, CLK1 Minimum Typical VDD = VIN = 3.465V VDD = VIN = 3.465V Units 5 µA 150 µA nCLK0, nCLK1 VDD = 3.465V, VIN = 0V -150 µA CLK0, CLK1 VDD = 3.465V, VIN = 0V -5 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLKx and nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 85210AY-31 Maximum www.icst.com/products/hiperclocks.html 4 1.3 V VDD - 0.85 V REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Test Conditions Output Crossover Voltage Minimum Maximum Units 1 1.4 V 0 0.4 V 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V 0.6 1.1 V Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50Ω to ground. VSWING Typical TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.4V TO 2.0V, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time Test Conditions Minimum ƒ≤ 650MHz 1.4 30% to 70% @ 50MHz Typical 300 odc Output Duty Cycle 47 All parameters measured at 400MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 85210AY-31 www.icst.com/products/hiperclocks.html 5 Maximum Units 650 MHz 2 ns 50 ps 350 ps 700 ps 53 % REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.4V to 2.0V 3.3V±5% V DD V DD Qx SCOPE nCLK0, nCLK1 VDDO V HSTL Cross Points PP GND V CMR CLK0, CLK1 nQx GND 0V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx Qx PART 1 nQx Qx Qy PART 2 nQy nQy Qy t sk(pp) t sk(o) OUTPUT SKEW PART-TO-PART SKEW nCLK0, nCLK1 80% 80% CLK0, CLK1 VSW I N G Clock Outputs nQAx, nQBx QAx, QBx 20% 20% tF tR OUTPUT RISE/FALL TIME tPD PROPAGATION DELAY nQAx, nQBx QAx, QBx Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 85210AY-31 www.icst.com/products/hiperclocks.html 6 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 85210AY-31 www.icst.com/products/hiperclocks.html 7 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS HSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V Zo = 50 Ohm 3.3V 3.3V R3 125 BY R4 125 LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 85210AY-31 BY www.icst.com/products/hiperclocks.html 8 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85210-31. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85210-31 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 120mA = 416mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 32.8mW = 328mW Total Power_MAX (3.465V, with all outputs switching) = 416mW + 328mW = 744mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.744W * 42.1°C/W = 101°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 500 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85210AY-31 www.icst.com/products/hiperclocks.html 9 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 4. VDDO Q1 VOUT RL 50Ω FIGURE 4. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V OH_MIN Pd_L = (V /R ) * (V L -V DDO_MAX /R ) * (V OL_MAX L DDO_MAX ) OH_MIN -V ) OL_MAX Pd_H = (1V/50Ω) * (2V - 1V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 85210AY-31 www.icst.com/products/hiperclocks.html 10 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85210-31 is: 1216 85210AY-31 www.icst.com/products/hiperclocks.html 11 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 85210AY-31 www.icst.com/products/hiperclocks.html 12 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85210AY-31 ICS85210AY-31 32 lead LQFP 250 per tray 0°C to 70°C ICS85210AY-31T ICS85210AY-31 32 lead LQFP on Tape and Reel 1000 0°C to70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85210AY-31 www.icst.com/products/hiperclocks.html 13 REV. B MARCH 19, 2004 ICS85210-31 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page 1 A 2 2 2 7 8 4&5 B 85210AY-31 T4A T5 4 5 6 Description of Change Throughout data sheet changed LVHSTL to HSTL. Pin Description Table changed VDD description from Positive to Core. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Revised Single Ended Signal Driving Differential Input diagram. Added Differential Clock Input Interface section. Updated data sheet format. All DC & AC Chararcteristics tables changed VDDO to 1.4V to 2.0V from 1.8V±0.2V. Power Supply DC Characteristics Table - changed VDDO min. from 1.6V to 1.4V. AC Characteristics Table - changed tPD min. from 1.5ns to 1.4ns. Parameter Measurement Information section - corrected 3.3V Output Load AC Test Circuit diagram adding VDDO. www.icst.com/products/hiperclocks.html 14 Date 9/29/03 3/19/04 REV. B MARCH 19, 2004