PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8521I is a low skew, 1-to-9 Differentialto-HSTL Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS8521I has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. • Nine HSTL outputs Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8521I ideal for today’s most advanced applications, such as IA64 and static RAMs. • Part-to-part skew: 200ps (typical) ICS • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency: 500MHz • Output skew: 25ps (typical) • Propagation delay: 1.3ns (typical) • VOH = 1.4V (maximum) • 3.3V core, 1.8V output operating supply voltages • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VDDO nQ2 Q2 nQ1 Q1 nQ0 Q0 VDDO D CLK_EN Q CLK nCLK PCLK nPCLK CLK_SEL LE 0 1 32 31 30 29 28 27 26 25 Q0 nQ0 VDD CLK nCLK CLK_SEL PCLK nPCLK GND CLK_EN Q1 nQ1 Q2 nQ2 Q3 nQ3 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 ICS8521I VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO 9 1 0 1 1 1 2 1 3 1 4 1 5 16 VDDO Q6 nQ6 Q7 nQ7 Q8 nQ8 VDDO Q4 nQ4 Q5 nQ5 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Q6 nQ6 Q7 nQ7 Q8 nQ8 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8521BYI www.icst.com/products/hiperclocks.html 1 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD Type Description Power Power supply pin. 2 CLK Input Pulldown 3 nCLK Input Pullup 4 CLK_SEL Input Pulldown 5 PCLK Input Pulldown 6 nPCLK Input Pullup 7 GND Power 8 CLK_EN Input Pullup Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS /LVTTL interface levels. 9, 16, 17, 24, 25, 32 10, 11 VDDO Power Output supply pins. nQ8, Q8 Output Differential output pair. HSTL interface levels. 12, 13 nQ7, Q7 Output Differential output pair. HSTL interface levels. 14, 15 nQ6, Q6 Output Differential output pair. HSTL interface levels. 18, 19 nQ5, Q5 Output Differential output pair. HSTL interface levels. 2 0, 21 nQ4, Q4 Output Differential output pair. HSTL interface levels. 22, 23 nQ3 Q3 Output Differential output pair. HSTL interface levels. 26, 27 nQ2, Q2 Output Differential output pair. HSTL interface levels. 28, 29 nQ1, Q1 Output Differential output pair. HSTL interface levels. 30, 31 nQ0, Q0 Output Differential output pair. HSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8521BYI www.icst.com/products/hiperclocks.html 2 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN CLK_SEL Outputs Selected Sourced Q0:Q8 nQ0:nQ8 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0:nQ8 Q0:Q8 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK Q0:Q8 nQ0:nQ8 0 1 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information "Wiring the Differential Input to Accept Single Ended Levels". 8521BYI www.icst.com/products/hiperclocks.html 3 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum VDD VDDO IDD Power Supply Current Power Supply Voltage 3.135 3.3 3.465 V Output Supply Voltage 1.6 1.8 2.0 V 60 Units mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage CLK_EN, CLK_SEL 2 VDD + 0.3 V VIL Input Low Voltage CLK_EN, CLK_SEL -0.3 0.8 V IIH Input High Current 5 µA IIL Input Low Current Test Conditions CLK_EN Minimum Typical VIN = VDD = 3.465V Maximum Units CLK_SEL VIN = VDD = 3.465V CLK_EN VIN = 0V, VDD = 3.465V -150 µA CLK_SEL VIN = 0V, VDD = 3.465V -5 µA 150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Units CLK VIN = VDD = 3.465V 150 µA nCLK VIN = VDD = 3.465V 5 µA CLK VIN = 0V, VDD = 3.465V -5 nCLK VIN = 0V, VDD = 3.465V -150 Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. VPP 8521BYI Maximum www.icst.com/products/hiperclocks.html 4 µA µA 1.3 V VDD - 0.85 V REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol IIH IIL Parameter Input High Current Input Low Current Test Conditions PCLK Minimum Typical Maximum Units 150 µA VDD = VIN = 3.465V nPCLK VDD = VIN = 3.465V PCLK VDD = 3.465V, VIN = 0V -5 5 µA nPCLK VDD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0.3 Common Mode Input Voltage; VCMR 1.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. µA 1 V VDD V TABLE 4E. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Test Conditions Output Crossover Voltage Minimum Maximum Units 1.0 1.4 V 0 0.4 V 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V 0.6 1.1 V Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50Ω to ground. VSWING Typical TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time Test Conditions Minimum ƒ≤ 250MHz Typical Units 500 MHz 1.3 ns 25 ps 200 20% to 80% @ 50MHz 300 odc Output Duty Cycle 50 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured from VDD/2 to the output differential crossing point for single ended input levels. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8521BYI Maximum www.icst.com/products/hiperclocks.html 5 ps 700 ps % REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V ± 5% 1.8V ± 0.2V VDD V DD Qx SCOPE nCLK, nPCLK VDDO V HSTL V Cross Points PP CMR CLK, PCLK nQx GND GND = 0V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK, nPCLK 80% CLK, PCLK 80% VOD Clock Outputs nQ0:nQ8 20% 20% tR tF Q0:Q8 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0:nQ8 Q0:Q8 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8521BYI www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. HSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 8521BYI www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS HSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8521BYI BY www.icst.com/products/hiperclocks.html 8 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 nCLK Receiv er Zo = 50 Ohm HiPerClockS Input R2 84 FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 8521BYI www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8521I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8521I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 60mA = 208mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 32.8mW = 295.2mW Total Power_MAX (3.465V, with all outputs switching) = 208mW + 295.2mW = 503.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.503W * 42.1°C/W = 106.2°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 32-pin LQFP, Forced Convection θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8521BYI www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 5. VDDO Q1 VOUT RL 50Ω FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MIN Pd_L = (V L DDO_MAX /R ) * (V OL_MAX L -V ) OH_MIN -V DDO_MAX ) OL_MAX Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8521BYI www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8521I is: 944 8521BYI www.icst.com/products/hiperclocks.html 12 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8521BYI www.icst.com/products/hiperclocks.html 13 REV. A NOVEMBER 17, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8521I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8521BYI ICS8521BYI 32 Lead LQFP tray -40°C to 85°C ICS8521BYIT ICS8521BYI 32 Lead LQFP 1000 tape & reel -40°C to 85°C ICS8521BYILF ICS8521BYILF 32 Lead "Lead-Free" LQFP tray -40°C to 85°C ICS8521BYILFT ICS8521BYILF 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8521BYI www.icst.com/products/hiperclocks.html 14 REV. A NOVEMBER 17, 2005