Revised September 2000
74F161A • 74F163A
Synchronous Presettable Binary Counter
General Description
Features
The 74F161A and 74F163A are high-speed synchronous
modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have
two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multi-stage
counters. The 74F161A has an asynchronous MasterReset input that overrides all other inputs and forces the
outputs LOW. The 74F163A has a Synchronous Reset
input that overrides counting and parallel loading and
allows the outputs to be simultaneously reset on the rising
edge of the clock. The 74F161A and 74F163A are highspeed versions of the 74F161 and 74F163.
■ Synchronous counting and loading
■ High-speed synchronous expansion
■ Typical count frequency of 120 MHz
Ordering Code:
Order Number
Package Number
Package Description
74F161ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F161ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F161APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F163ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F163ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F163APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F161A
© 2000 Fairchild Semiconductor Corporation
74F163A
DS009486
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74F161A • 74F163A Synchronous Presettable Binary Counter
April 1988
74F161A • 74F163A
Logic Symbols
74F161A
74F163A
IEEE/IEC
IEEE/IEC
74F161A
74F163A
Unit Loading/Fan Out
Pin Names
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
Description
CEP
Count Enable Parallel Input
1.0/1.0
20 µA/−0.6 mA
CET
Count Enable Trickle Input
1.0/2.0
20 µA/−1.2 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
MR (74F161A)
Asynchronous Master Reset Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
SR (74F163A)
Synchronous Reset Input (Active LOW)
1.0/2.0
20 µA/−1.2 mA
P0–P3
Parallel Data Inputs
1.0/1.0
20 µA/−0.6 mA
PE
Parallel Enable Input (Active LOW)
1.0/2.0
20 µA/−1.2 mA
Q0–Q3
Flip-Flop Outputs
50/33.3
−1 mA/20 mA
TC
Terminal Count Output
50/33.3
−1 mA/20 mA
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2
rising edge of CP. With PE and MR ('F161A) or SR
(74F163A) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
Mode Select Table
State Diagram
SR
(Note 1)
L
PE CET
X
X
CE
P
The 74F161A and 74F163A use D-type edge triggered flipflops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided
that the recommended setup and hold times, with respect
to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement synchronous multi-stage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways. Please
refer to the 74F568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
Action on the Rising
Clock Edge (
X
Reset (Clear)
Load (Pn→Qn)
H
L
X
X
H
H
H
H
Count (Increment)
H
H
L
X
No Change (Hold)
H
H
X
L
No Change (Hold)
)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: For 74F163A only
Block Diagram
3
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74F161A • 74F163A
Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the 74F161A) occur as a
result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence:
asynchronous reset (74F161A), synchronous reset
(74F163A), parallel load, count-up and hold. Five control
inputs—Master Reset (MR, 74F161A), Synchronous Reset
(SR, 74F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the
mode of operation, as shown in the Mode Select Table. A
LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to
go LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (Pn) inputs to be loaded into the flip-flops on the next
74F161A • 74F163A
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
VCC
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
VOH
Output HIGH
V
Min
0.5
V
Min
IOL = 20 mA
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
−0.6
mA
Max
VIN = 0.5V (CEP, CP, MR, P0–P3)
−1.2
mA
Max
VIN = 0.5V (CET, PE, SR)
VOUT = 0V
VOL
Output LOW
10% VCC
2.5
5% VCC
2.7
V
Conditions
Input HIGH Voltage
Voltage
2.0
Units
VIH
10% VCC
Voltage
IIH
Input HIGH
Current
IBVI
Input HIGH Current
Breakdown Test
ICEX
Output HIGH
Leakage Current
VID
Input Leakage
Test
IOD
4.75
Output Leakage
Circuit Current
IIL
Input LOW Current
IOS
Output Short-Circuit Current
ICC
Power Supply Current
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−60
37
4
Recognized as a HIGH Signal
Recognized as a LOW Signal
−150
mA
Max
55
mA
Max
IIN = −18 mA
IID = 1.9 µA
All Other Pins Grounded
VIOD = 150 mV
All Other Pins Grounded
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
CL = 50 pF
Min
Typ
fMAX
Maximum Count Frequency
100
120
Max
Min
tPLH
Propagation Delay
3.5
5.5
7.5
tPHL
CP to Qn (PE Input HIGH)
3.5
7.5
10.0
3.5
tPLH
Propagation Delay
4.0
6.0
8.5
4.0
Max
Min
75
Max
90
3.5
9.0
Units
MHz
3.5
8.5
11.5
3.5
11.0
10.0
4.0
9.5
ns
tPHL
CP to Qn (PE Input LOW)
4.0
6.0
8.5
4.0
10.0
4.0
9.5
tPLH
Propagation Delay
5.0
10.0
14.0
5.0
16.5
5.0
15.0
tPHL
CP to TC
5.0
10.0
14.0
5.0
15.5
5.0
15.0
tPLH
Propagation Delay
2.5
4.5
7.5
2.5
9.0
2.5
8.5
tPHL
CET to TC
2.5
4.5
7.5
2.5
9.0
2.5
8.5
tPHL
Propagation Delay
5.5
9.0
12.0
5.5
14.0
5.5
13.0
ns
4.5
8.0
10.5
4.5
12.5
4.5
11.5
ns
MR to Qn (74F161A)
tPHL
Propagation Delay
MR to TC (74F161A)
ns
ns
AC Operating Requirements
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
VCC = +5.0V
VCC = +5.0V
Min
Max
Min
Max
TA = 0°C to +70°C
VCC = +5.0V
Min
tS(H)
Setup Time, HIGH or LOW
5.0
5.5
5.0
tS(L)
Pn to CP
5.0
5.5
5.0
tH(H)
Hold Time, HIGH or LOW
2.0
2.5
2.0
tH(L)
Pn to CP
2.0
2.5
2.0
tS(H)
Setup Time, HIGH or LOW
11.0
13.5
11.5
tS(L)
PE or SR to CP
8.5
10.5
9.5
tH(H)
Hold Time, HIGH or LOW
2.0
3.6
2.0
tH(L)
PE or SR to CP
0
0
0
tS(H)
Setup Time, HIGH or LOW
11.0
13.0
11.5
5.0
6.0
5.0
0
0
0
tS(L)
CEP or CET to CP
tH(H)
Hold Time, HIGH or LOW
tH(L)
CEP or CET to CP
0
0
0
tW(H)
Clock Pulse Width (Load)
5.0
5.0
5.0
tW(L)
HIGH or LOW
5.0
5.0
5.0
Units
Max
ns
ns
ns
ns
tW(H)
Clock Pulse Width (Count)
4.0
5.0
4.0
tW(L)
HIGH or LOW
6.0
8.0
7.0
tW(L)
MR Pulse Width, LOW
5.0
5.0
5.0
ns
6.0
6.0
6.0
ns
(74F161A)
tREC
Recovery Time
MR to CP (74F161A)
5
ns
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74F161A • 74F163A
AC Electrical Characteristics
74F161A • 74F163A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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6
74F161A • 74F163A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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74F161A • 74F163A Synchronous Presettable Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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