SCLS500A − MAY 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D Ioff Supports Partial-Power-Down Mode − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 105°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports D Operation ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) PW PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK description/ordering information The SN74LV374A is an octal edge-triggered D-type flip-flop designed for 2-V to 5.5-V VCC operation. This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 105°C TSSOP − PW Tape and reel SN74LV374ATPWREP LV374AEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS500A − MAY 2003 − REVISED MAY 2004 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L L X Q0 H X X Z logic diagram (positive logic) OE CLK 1 11 C1 1D 3 1D 2 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS500A − MAY 2003 − REVISED MAY 2004 recommended operating conditions (see Note 4) VCC VIH VIL MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V IOH IOL ∆t/∆v V VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 Output voltage High or low state 0 3-state 0 VCC × 0.3 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current V VCC 5.5 V −50 µA −8 mA −16 µA 50 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 2 VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V 16 8 mA 200 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate V −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V Low-level output current V VCC × 0.7 VCC × 0.7 Input voltage VO UNIT 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V Low-level input voltage VI MIN 100 ns/V 20 TA Operating free-air temperature −40 105 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA VCC 2 V to 5.5 V 2.3 V IOH = −8 mA IOH = −16 mA IOL = 50 µA IOL = 2 mA VI = 5.5 V or GND VO = VCC or GND ICC Ioff VI = VCC or GND, VI or VO = 0 to 5.5 V Ci VI = VCC or GND TYP UNIT VCC−0.1 2 3V 2.48 4.5 V 3.8 V 0.1 2.3 V 0.4 3V 0.44 4.5 V 0.55 V 0 to 5.5 V ±1 µA 5.5 V ±5 µA 5.5 V 20 µA 5 µA IO = 0 0 3.3 V POST OFFICE BOX 655303 MAX 2 V to 5.5 V IOL = 8 mA IOL = 16 mA II IOZ MIN • DALLAS, TEXAS 75265 2.9 pF 3 SCLS500A − MAY 2003 − REVISED MAY 2004 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ MIN MAX UNIT 5 5.5 ns 4.5 4.5 ns 2 2 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX MIN MAX UNIT tw Pulse duration, CLK high or low 5 5 ns tsu Setup time, data before CLK↑ 3 3 ns th Hold time, data after CLK↑ 2 2 ns switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tpd FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE free-air temperature TA = 25°C MIN TYP MAX 55 110 MIN MAX 50 CLK Q 8.3 16.2 1 18.5 OE Q 7.7 14.5 1 17.5 tdis tsk(o) OE Q 5.9 14 1 16 FROM (INPUT) TO (OUTPUT) fmax tpd CLK Q ten OE Q tdis tsk(o) OE Q 4 ns 1.5 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER UNIT MHz ten CL = 50 pF range, LOAD CAPACITANCE free-air MIN 85 CL = 50 pF temperature TA = 25°C TYP MAX 170 • DALLAS, TEXAS 75265 MAX 75 UNIT MHz 5.9 10.1 1 13.5 5.5 9.6 1 13 4 8.8 1 10 1 POST OFFICE BOX 655303 MIN range, ns SCLS500A − MAY 2003 − REVISED MAY 2004 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.6 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.5 −0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage 2.9 V 2.31 V 0.99 V VCC 3.3 V TYP UNIT 5V 22.8 NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS Outputs enabled POST OFFICE BOX 655303 CL = 50 pF, • DALLAS, TEXAS 75265 f = 10 MHz 21.1 pF 5 SCLS500A − MAY 2003 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC VCC Output Control 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV374ATPWREP ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03663-01XE ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74LV374A-EP : SN74LV374A • Catalog: • Automotive: SN74LV374A-Q1 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LV374ATPWREP Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV374ATPWREP TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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