www.ti.com SN74ALVCHG162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • • • Member of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process A-Port Outputs Have Equivalent 50-Ω Series Resistors and B-Port Outputs Have Equivalent 20-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in Thin Very Small-Outline Package NOTE: For order entry, the DBB package is abbreviated to G. For tape and reel, the DBBR package is abbreviated to GR. DESCRIPTION The SN74ALVCHG162282 is an 18-bit to 36-bit registered bus exchanger. This device is intended for use in applications where data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. It is designed specifically for low-voltage (3.3-V) VCC operation. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input. For data transfer in the B-to-A direction, the select (SEL) input selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the 1B path, with a single storage register in the 2B path. Data flow is controlled by the active-low output-enable (OE) and direction-control (DIR) input. DIR is registered to synchronize the bus direction changes with the clock. DBB PACKAGE (TOP VIEW) VCC GND 2B9 1B9 2B8 GND 1B8 2B7 1B7 VCC 2B6 1B6 2B5 1B5 GND 2B4 1B4 2B3 1B3 VCC GND 2B2 1B2 2B1 1B1 VCC A1 A2 A3 GND A4 A5 A6 VCC A7 A8 A9 GND CLK SEL 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 33 48 34 47 35 46 36 45 37 44 38 43 39 42 40 41 VCC GND 1B10 2B10 1B11 GND 2B11 1B12 2B12 VCC 1B13 2B13 1B14 2B14 GND 1B15 2B15 1B16 2B16 VCC GND 1B17 2B17 1B18 2B18 VCC A18 A17 A16 GND A15 A14 A13 VCC A12 A11 A10 GND OE DIR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2004, Texas Instruments Incorporated SN74ALVCHG162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004 DESCRIPTION (CONTINUED) The A-port N-channel output transistors are sized at 450 µm, and the P-channel output transistors are sized at 700 µm. All A-port outputs have equivalent 50-Ω series resistors. The B-port N-channel output transistors are sized at 225 µm, and the P-channel output transistors are sized at 560 µm. All B-port outputs have equivalent 20-Ω series resistors Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The switching characteristics are based on 25-pF (A port) and 80-pF (B port) loads, but are tested with the standard 50-pF load. The SN74ALVCHG162282 is characterized for operation from 0°C to 70°C. FUNCTION TABLES XXX A-TO-B STORAGE (OE = L, DIR = H) INPUTS SEL (1) (2) OUTPUTS CLK H X L ↑ L ↑ A X 1B 1B0 2B (1) 2B0 (1) L L (2) L H H (2) H Output level before indicated steady-state input conditions were established Two CLK edges are needed to propagate the data. XXX B-TO-A STORAGE (OE = L, DIR = L) INPUTS (1) CLK SEL 1B 2B OUTPUT A ↑ H X L L (1) ↑ H X H H (1) ↑ L L X L ↑ L H X H Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and propagates to the second register when SEL is high. XXX OUTPUT ENABLE INPUTS 2 OUTPUTS CLK OE DIR A ↑ H X Z 1B, 2B Z ↑ L H Z Active ↑ L L Active Z SN74ALVCHG162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) CLK SEL OE 39 40 42 CE C1 DIR 41 1D 25 1 of 18 Channels 1B1 G1 CE C1 A1 27 1 1D C1 1D 1 24 2B1 CE C1 C1 1D 1D CE C1 1D 3 SN74ALVCHG162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage range MAX -0.5 4.6 Except I/O ports (2) -0.5 VCC + 0.5 I/O ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.5 UNIT V VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current ±50 mA 106 °C/W 150 °C θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) -65 V V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The input and output positive voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VIH High-level input voltage VCC = 3 V to 3.6 V VIL Low-level input voltage VCC = 3 V to 3.6 V VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current MIN MAX 3 3.6 2 (1) 4 Operating free-air temperature V V 0.8 V 0 VCC V 0 VCC V A to B VCC = 3 V 8 B to A VCC = 3 V 6 A to B VCC = 3 V 8 B to A VCC = 3 V 6 ∆t/∆v Input transition rise or fall rate TA UNIT 0 mA mA 10 ns/V 70 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74ALVCHG162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA VOH VOL VCC 3 V to 3.6 V MIN TYP (1) MAX VCC - 0.2 A to B IOH = -8 mA 3V 2 B to A IOH = -6 mA 3V 2 IOL = 100 µA 3 V to 3.6 V 0.2 V A to B IOL = 8 mA 3V 0.8 B to A IOL = 6 mA 3V 0.8 3.6 V ±5 II VI = VCC or GND II(hold) VI = 0.8 V 3V 75 VI = 2 V 3V -75 VI = 0 to 3.6 V (2) IOZ (3) VO = VCC or GND ICC VI = VCC or GND, IO = 0 ∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND UNIT V µA µA 3.6 V ±500 3.6 V ±10 µA 3.6 V 40 µA 3 V to 3.6 V 750 µA Ci Control inputs VI = VCC or GND 3.3 V 4 pF Cio A or B ports VO = VCC or GND 3.3 V 8.5 pF (1) (2) (3) All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu th Setup time, high or low Hold time, high or low 160 2.3 A data before CLK↑ 1.5 B data before CLK↑ 2 DIR before CLK↑ 2 SEL before CLK↑ 2 A data after CLK↑ 0.3 B data after CLK↑ 0.3 DIR after CLK↑ 0.3 SEL after CLK↑ 0.3 UNIT MAX MHz ns ns ns 5 SN74ALVCHG162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 25 pF (A port), 80 pF (B port) (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd MIN UNIT MAX 160 CLK CLK ten OE CLK tdis OE 6 VCC = 3.3 V ± 0.3 V MHz A 1.5 5 B 1.5 7.4 A 1.5 6.3 B 1.5 9.4 A 1.5 6 B 1.5 9.5 A 1.5 6.4 B 1.5 7.8 A 1.5 5 B 1.5 7.6 ns ns ns SN74ALVCHG162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω S1 Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 3V 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 2.7 V 1.5 V tPZL 2.7 V Output VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 0V 0V tsu Input 1.5 V Input VOH 1.5 V VOH − 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The output is measured with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 74ALVCHG162282GRE4 ACTIVE TSSOP DBB 80 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCHG162282GRG4 ACTIVE TSSOP DBB 80 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TSSOP DBB 80 TSSOP DBB 80 SN74ALVCHG162282DBBR OBSOLETE SN74ALVCHG162282GR ACTIVE Pins Package Eco Plan (2) Qty TBD 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish Call TI CU NIPDAU MSL Peak Temp (3) Call TI Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74ALVCHG162282GR TSSOP DBB 80 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.4 17.3 1.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCHG162282GR TSSOP DBB 80 2000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MTSS005D – JANUARY 1995 – REVISED MARCH 2002 DBB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 80 PINS SHOWN 0,23 0,13 0,40 80 0,07 M 41 6,20 6,00 8,30 7,90 0,20 0,09 1 Gage Plane 40 A 0,25 0°–ā8° 0,75 0,45 Seating Plane 1,20 MAX 0,15 0,05 PINS** 0,08 80 100 A MAX 17,10 20,90 A MIN 16,90 20,70 DIM 4040212 / E 03/02 NOTES: A. All linear dimensions are in millimeters. B. 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