TI UC1707-SP

UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
DUAL CHANNEL POWER DRIVER
Check for Samples: UC1707-SP
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
J OR W PACKAGE
(TOP VIEW)
Rad-Tolerant: 50 kRad (Si) for
5962-8761903VEA, 5962-8761903VFA (1)
QML-V Qualified, SMD
(5962-8761901VEA, 5962-8761903VEA,
5962-8761903VFA, 5962-8761901V2A)
Two Independent Drivers
1.5-A Totem Pole Outputs
Inverting and Non-Inverting Inputs
40-ns Rise and Fall Into 1000 pF
High-Speed, Power MOSFET Compatible
Low Cross-Conduction Current Spike
Analog Shutdown With Optional Latch
Low Quiescent Current
5-V to 40-V Operation
Thermal Shutdown Protection
16-Pin Dual-In-Line Package
INPUT B INV.
1
16
INPUT A INV.
INPUT B N.I.
2
INPUT A N.I.
LATCH DISABLE
3
15
14
GROUND
4
13
GROUND
GROUND
5
12
GROUND
OUTPUT A
SHUTDOWN
6
11
OUTPUT B
7
8
10
ANALOG STOP NON-INV.
+VC
ANALOG STOP INV.
NOTE: All four ground pins must be connected to a
common ground.
FK PACKAGE
(TOP VIEW)
NC
INPUT A INV.
INPUT A NON INV.
INPUT B INV.
INPUT B I.N.
3
Radiation tolerance is a typical value based upon initial device
qualification with dose rate = 10 mrad/sec. Radiation Lot
Acceptance Testing is available - contact factory for details.
2
1
20
19
LATCH DISABLE
4
18
VIN
GROUND
5
17
GROUND
NC
6
16
NC
GROUND
7
15
GROUND
OUTPUT A
8
14
OUTPUT B
9
(1)
9
+VIN
SHUTDOWN
VC
10
11
12
13
ANALOG STOP INV.
ANALOG STOP NON INV.
NC
DESCRIPTION
The UC1707 power driver is made with a high-speed Schottky process to interface between low-level control
functions and high-power switching devices–particularly power MOSFETs. The UC1707 contains two
independent channels, each of which can be activated by either a high or low input logic level signal. Each output
can source or sink up to 1.5 A as long as power dissipation limits are not exceeded.
Although each output can be activated independently with its own inputs, it can be forced low in common through
the action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. The
Shutdown command from either source can either be latching or not, depending on the status of the Latch
Disable pin.
Supply voltage for both VIN and VC can independently range from 5 V to 40 V.
TRUTH TABLE
(Each Channel) (1)
(1)
INV.
N.I.
H
H
OUT
L
L
H
H
H
L
L
L
L
L
OUT = INV and N.I.
OUT = INV or N.I.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2011, Texas Instruments Incorporated
UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
ORDERING INFORMATION (1)
TA
PACKAGE
(2)
(J) CDIP
–55°C to 125°C
(1)
(2)
2
ORDERABLE PART NUMBER
TOP-SIDE MARKING
5962-8761901VEA
5962-8761901VEA
5962-8761903VEA
5962-8761903VEA
(W) CFP
5962-8761903VFA
5962-8761903VFA
(FK) LCCC
5962-8761901V2A
5962-8761901V2A
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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© 2011, Texas Instruments Incorporated
Product Folder Link(s): UC1707-SP
UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
Supply voltage
40
VC
Collector supply voltage
40
±500
Output current (each output, source or sink) steady-state
θJC
Capacitive discharge energy
15
mJ
Digital inputs (1)
5.5
V
Analog stop inputs
VIN
Operating virtual-junction temperature
150
Package thermal impedance, junction to case (2) (3)
J package
9.6
W package
8.3
FK package
9.5
J package
13
W package
15
FK package
13
(3)
°C
°C/W
W
Operating temperature range
–55
125
°C
Storage temperature range
–65
150
°C
300
°C
Lead temperature (soldering, 10 seconds)
(2)
V
mA
A
Power dissipation at Tcase = 25°C (1)
(1)
V
±1
Peak transient
TJ
UNIT
All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of the
specified terminal. Digital drive can exceed 5.5 V if input current is limited to 10 mA. Consult packaging section of databook for thermal
limitations and considerations of package.
Maximum power dissipation is a function of TJ (max), θJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ (max) – TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with MIL-STD-883.
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for TA = –55°C to 125°C; VIN = VC = 20 V. TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Supply current
VIN = 40 V
12
15
mA
VC
Supply current
VC = 40 V, outputs low
5.2
7.5
mA
VC
Leakage current
VIN = 0, VC - 30 V, no load
0.05
0.1
mA
0.8
V
–0.06
–1.0
mA
0.05
0.1
mA
Digital input low level
Digital input high level
Input current
VI = 0
Input leakage
VI = 5 V
VC – VO Output high sat.
VO
2.2
Output low sat.
V
IO = –50 mA
2.0
IO = –500 mA
2.5
IO = –50 mA
0.4
IO = –500 mA
2.5
Analog threshold
VCM = 0 to 15 V
Input bias current
VCM = 0
8761901
100
130
150
8761903
90
130
150
–10
–20
Thermal shutdown
V
V
mV
μA
°C
155
Shutdown threshold
Pin 7 input
0.4
1.0
2.2
V
Latch disable threshold
Pin 3 input
0.8
1.2
2.2
V
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Product Folder Link(s): UC1707-SP
3
UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
TYPICAL SWITCHING CHARACTERISTICS
VIN = VC = 20 V, TA = 25°C. Delays measured to 10% output change.
PARAMETER
TEST CONDITIONS
From Inv. Input to Output
OUTPUT CL =
UNIT
open
1.0
2.2
nF
Rise time delay
40
50
60
ns
10% to 90% rise
25
40
50
ns
Fall time delay
30
40
50
ns
90% to 10% fall
25
40
50
ns
Rise time delay
30
40
50
ns
10% to 90% rise
25
40
50
ns
Fall time delay
45
55
65
ns
90% to 10% fall
25
40
50
ns
From N.I. Input to Output
VC cross-conduction current spike duration Output rise
25
ns
0
ns
Stop non-Inv. = 0 V
180
ns
Stop Inv. = 0 to 0.5 V
180
ns
50
ns
Output fall
Analog shutdown delay
Digital shutdown delay
4
2 V input on Pin 7
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© 2011, Texas Instruments Incorporated
Product Folder Link(s): UC1707-SP
UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
SIMPLIFIED INTERNAL CIRCUITRY
Figure 1. Typical Digital Input Gate
Figure 2. Typical Digital Input Gate
Figure 3. Latch Disable
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UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
SIMPLIFIED INTERNAL CIRCUITRY (continued)
Figure 4. Use of the Shutdown Pin
SHUTDOWN CIRCUIT DESCRIPTION
The function of the circuitry is to be able to provide a shutdown of the device. This is defined as functionality that
will drive both outputs to the low state. There are three different inputs that govern this shutdown capability.
• Analog Stop Pins — The differential inputs to this comparator provide a way to execute a shutdown.
• Latch Disable Pin — Assuming that the Shutdown pin is left open, a high on this pin disables the latching
functionality of the Analog Stop shutdown. A low on this pin enables the latching functionality of the Analog
Stop shutdown. If a shutdown occurs through the Analog Stop circuit while Latch Disable is high, then the
outputs will go low, but will return to normal operation as soon as the Analog Stop circuit allows it. If a
shutdown occurs through the Analog Stop circuit while Latch Disable is low, then the outputs will go low and
remain low even if the Analog Stop circuit no longer drives the shutdown. The outputs will remain "latched"
low (in shutdown) until the Latch Disable goes high and the Analog Stop circuit allows it to return from
shutdown or the VIN voltage is cycled to 0V and then returned above 5V.
• Shutdown Pin — This pin serves two purposes.
1. It can be used as an output of the Analog Stop circuit.
2. It can be used as an input to force a shutdown or to force the device out of shutdown. This pin can
override both the Analog Stop circuit as well as the Latch Disable Pin. When driving hard logic levels into
the Shutdown pin, the Latch Disable functionality will be overridden and the Latch Disable will not function
as it does when used in conjunction with the Analog Stop circuit. When the Shutdown pin is high, the
outputs will be in the low state (shutdown). When the Shutdown pin is low (hard logic low) the outputs will
operate normally, regardless of the state of the Latch Disable pin or the Analog Stop pins.
In order to use the Shutdown Pin with the Latch Disable functional it is necessary to use either a diode in series
with the Shutdown signal or to use an open collector pull-up so that the Shutdown pin is not pulled low. This
configuration will allow the Latch Disable function to work with the Shutdown pin.
6
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Product Folder Link(s): UC1707-SP
UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
SIMPLIFIED INTERNAL CIRCUITRY (continued)
Table 1. UG1707 SHUTDOWN TRUTH TABLE
(1)
ANALOG STOP
LOGIC
SHUTDOWN
LATCH DISABLE
PREVIOUS STATE OF
OUTPUT
OUTPUT
X
0
X
X
Follows Input Logic
X
1
X
X
Low (Shutdown)
1
Open
X
X
Low (Shutdown)
(1)
0
Open
0
Shutdown
0
Open
0
Normal
Follows Input Logic
0
Open
1
X
Follows Input Logic
Latched Shutdown
If the output was previously in Shutdown and Latch Disable was low and stays low, then even if the Analog Stop Logic is changed or the
Shutdown pin is open, the outputs will remain in Shutdown.
Figure 5. Transformer Coupled Push-Pull MOSFET Drive Circuit
Figure 6. Current Limiting
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Product Folder Link(s): UC1707-SP
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UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
Figure 7. Over-Voltage Protection
Figure 8. Power MOSFET Drive Circuit
Figure 9. Charge Pump Circuits
8
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© 2011, Texas Instruments Incorporated
Product Folder Link(s): UC1707-SP
UC1707-SP
SLUSAG0 – MARCH 2011
www.ti.com
Figure 10. Power Bipolar Drive Circuit
Figure 11. Transformer Coupled MOSFET Drive Circuit
Figure 12. Power MOSFET Drive Circuit Using Negative Bias Voltage
and Level Shifting to Ground Reference PWM
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© 2011, Texas Instruments Incorporated
Product Folder Link(s): UC1707-SP
9
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
5962-8761901V2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
5962-8761901VEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
5962-8761903VEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
5962-8761903VFA
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1707-SP :
• Catalog: UC1707
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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