MDT10P23(CC ) 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 2K words EPROM and80 bytes static RAM. Four comparator inputs with external Vref (not for 18 pin package) are also provided. 2. Features u u u u Fully CMOS static design 8-bit data bus On chip EPROM size : 2 K words Internal RAM size : 80 bytes (72 general purpose registers, 8 special registers) u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3V ~ 6.0 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u Built-in Power-on Reset u 4 Channel comparator u Power edge-detector Reset u Sleep Mode for power saving u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option: RC－Low cost RC oscillator LFXT－Low frequency crystal oscillator XTAL－Standard crystal oscillator HFXT－High frequency crystal oscillator u 4 oscillator start-up time can be selected by programming option: 150 µs, 20 ms, 40 ms, 80 ms u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u 12 I/O(for 18 pins package),14 I/O(for 20 pins package),16 I/O(for 22/24 pins package) pins with their own independent direction control 3. Applications The application areas of this MDT10P23 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral … etc This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2005/6 Ver. 1.4 MDT10P23(CC ) 4. Pin Assignment ※ A1：20PINS, A2：22PINS, A3：24PINS, A5 :18 PINS ※ P－PDIP,S－SOP, K－SKINNY A1P,A1S A3S PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 NC PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A2K PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A5P,A5S PA2CIC2 1 PA3/CIC3 2 RTCC 3 /MCLR 4 Vss 5 PB0 6 PB1 7 PB2 8 PB3 9 18 17 16 15 14 13 12 11 10 PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2005/6 Ver. 1.4 MDT10P23(CC ) 5. Block Diagram S ta ck Tw o Le ve ls RAM 7 2 X8 E PR OM 1 KX1 4 (MDT1 0 P 2 3 ) P o rt P B0 ~P B7 8 b its P o rt B 1 0 b its 1 4 b its 1 0 b its P ro g ra m C o u n te rs OSC 2 O SC 1 In s tru ctio n Re g is te r S p e c ia l Re g is te r D0 ~ D 7 MC LR O s cilla to r Circu it In s tru ctio n De co d e r P o rt P A0 ~ P A7 (2 2 ,2 4 p in s P A0 ~ P A5 (2 0 p in s ) P A0 ~ P A3 (1 8 p in s ) P o rt A 8 b its Co n tro l C ircu it CMR 0 ~CMR 5 D a ta 8 -b it P o we r o n Re s e t P o w e r Do wn R e s e t W o rkin g R e g is te r S ta tu s R e g is te r ALU 8 -b it Tim e r/Co u n te r C o m p a ra t or mode R e g is te r W DT/O S T Tim e r P re s ca le R TCC This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2005/6 Ver. 1.4 MDT10P23(CC ) 6. Pin Function Description Pin Name I/O Function Description PA0~PA7 I/O PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output Vdd Power supply Vss Ground NC Unused ,do not connect 7. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07 Control register for comparator 08~0F Internal RAM, General Purpose Register 10~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2005/6 Ver. 1.4 MDT10P23(CC ) (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit 5 page ROM Page select bit : 00 : 000H --- 1FFH 01 : 200H --- 3FFH 7 —— General purpose bit This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2005/6 Ver. 1.4 MDT10P23(CC ) (5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only “1” Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) : R7 Bit 0 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 1 0: Define PA1 as TTL input 1: Define PA1 as comparator input 2 0: Define PA2 as TTL input 1: Define PA2 as comparator input 3 0: Define PA3 as TTL input 1: Define PA3 as comparator input 5:4 Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to input) 7:6 Register bits This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2005/6 Ver. 1.4 MDT10P23(CC ) 9) TMR (Time Mode Register) Bit Symbol Function Prescaler Value 2—0 PS2—0 3 PSC 4 TCE 5 TCS RTCC rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1 : 16 1:8 1 0 0 1 : 32 1 : 16 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin (10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (11) EPROM Option by writer programming : A. FIRST WORD Oscillator Type Oscillator Start-up Time Oscillator 150 µs LFXT Oscillator 20 ms XTAL Oscillator 40 ms HFXT Oscillator 80 ms RC Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2005/6 Ver. 1.4 MDT10P23(CC ) Power Edge Detect PED Security bit Disable Security Disable PED Enable Security Enable (B) Program Memory Address Description 000- 3FF Program memory The starting address of the power on, external reset or WDT 3FF 8. Reset Condition for all Registers Register Address Power-On Reset /MCLR Reset WDT Reset CPIO A －－ 1111 1111 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 1111 1111 TMR －－ --11 1111 --11 1111 --11 1111 IAR 00h － － － RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu PC 02h 1111 1111 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h 100x xxxx 100u uuuu 1uuu uuuu PORT A 05h xxxx xxxx uuuuuuuu uuuu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu CMR 07h 0000 0000 uuuu uuuu uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) U u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2005/6 Ver. 1.4 MDT10P23(CC ) 9. Instruction Set Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr NOP No operation None CLRWT Clear Watchdog timer 0→WT SLEEP Sleep mode 0→WT, stop OSC TF, PF TMODE Load W to TMODE register W→TMODE None RET Return Stack→PC None Control I/O port register W→CPIO 010001 1rrrrrrr STWR Store W to register W→R 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3)↔R(4~7)] →t None 011001 trrrrrrr INCR R, t R + 1→t Z 011010 trrrrrrr R + 1→t None 011011 trrrrrrr INCRSZ R, t Increment register, skip if zero ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t (R+/W+1→t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t Z 011110 trrrrrrr R ﹣1→t None 010010 trrrrrrr DECRSZ R, Decrement register, skip if t zero ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR R(n) →R(n-1), C →R(7), R(0)→C C Operating Status Instruction Code CPIO R R I i Increment register AND W and immediate Inclu. OR W and immediate i R, t Rotate right register Mnemonic Operands Function TF, PF r None None This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2005/6 Ver. 1.4 MDT10P23(CC ) 010101 trrrrrrr RLR R, t 010000 1xxxxxxx CLRW Rotate left register R(n)→r(n+1), C→R(0), R(7)→C C Clear working register 0→W Z 0→R Z 010001 0rrrrrrr CLRR R Clear register 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None n→PC, PC+1→ Stack n→PC None n→PC, PC+1→ Stack Stack→PC,i→W None n→PC None 100nnn nnnnnnnn LCALL n Long CALL subroutine 101nnn nnnnnnnn LJUMP n Long JUMP to address 110000 nnnnnnnn CALL n Call subroutine n Return, place immediate to W JUMP to address 110001 iiiiiiii RTWI i 11001n nnnnnnnn JUMP None None Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 10. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Vdd Operating voltage VIL Input Low Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V Min Typ Max Uni t 2.3 6.0 V -0.6 -0.6 1.0 1.0 V V This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2005/6 Ver. 1.4 MDT10P23(CC ) Sym Description VIH Input high Voltage PA, PB RTCC, /MCLR IIL Input leakage current VOL Output Low Voltage PA, PB VOH Output High Voltage PA, PB Islp Sleep current (WDT disable) Islp Sleep current (WDT enable) Condition Vdd=5V Vdd=5V Min Typ 2.0 3.3 Vdd=5V Max Uni t Vdd Vdd V V +/-1 µA Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA 0.5 0.1 V V Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vdd＝2.3 ~ 6.0 V 3.8 4.5 V V µA Vdd＝2.3 V Vdd＝3.0 V Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 1 3 6 11 17 Vpr Power Edge-detector Reset Voltage 0.1 1.0 µA µA µA µA µA 1.1 1.3 V Twdt The basic WDT time-out cycle time Vdd＝2.3 V Vdd＝3.0 V Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 25.2 22.4 20.4 18.8 18.0 mS mS mS mS mS TFLT /MCLR filter Vdd＝5.0 V 600 nS 15 µA Icc Comparator Supply current (one Vdd=5.0v comparator) Vref Input reference voltage --- Comparator Response time V-=Vdd/4, V+=V- ± 0.2v V-=Vdd/2, V+=V- ± 0.2v V-=Vdd3/4, V+=V- ± 0.2v V-=VDD-0.8,V+=V± 0.2v Vdd=2.5v ~6.0v Vdd=5.0v , V- = Vref V+ = (PA0~PA3) Vdd-0.8 V v 8 8 8 8 µS µS µS µS This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2005/6 Ver. 1.4 MDT10P23(CC ) 11. Operating Current Temperature＝25 ℃, the typical value as followings : 11.1 OSC Type＝RC (OSC1&OSC2 Internal Cap about 10P); WDT－Enable; Comparator － Disable ; PED=Disable Vdd＝5.0 V Cext. (F) 0P 3P 20P 100P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 7.76M 980 µA 10.0 K 3.82M 560 µA 47.0 K 848K 240 µA 100.0 K 404K 185 µA 300.0 K 135.6K 155 µA 470.0 K 86K 150 µA 4.7 K 6.8M 880 µA 10.0 K 3.34M 510 µA 47.0 K 740K 230 µA 100.0 K 356K 185 µA 300.0 K 119K 155 µA 470.0 K 75.2K 150 µA 4.7 K 4.16M 610 µA 10.0 K 2.04M 380 µA 47.0 K 452K 200 µA 100.0 K 214.8K 175 µA 300.0 K 75.2K 155 µA 470.0 K 45.6K 151 µA 4.7 K 1.57M 335 µA 10.0 K 764K 245 µA 47.0 K 167.2K 175 µA 100.0 K 76.8K 165 µA 300.0 K 26.6K 160 µA 470.0 K 16.8K 155 µA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2005/6 Ver. 1.4 MDT10P23(CC ) Cext. (F) 300P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 672K 235 µA 10.0 K 321.6K 195 µA 47.0 K 70.4K 165 µA 100.0 K 33.2K 160 µA 300.0 K 11.1K 158 µA 470.0 K 7.04K 156 µA 11.2 OSC Type＝LF (OSC1&OSC2 Internal Cap about 10P); WDT－Enable ; Comparator － Disable﹔PED=Disable Voltage/Frequency 32 K (EXT=50p) 455 K 1M Sleep 2.3 V 7.0µA 25µA 40µA ＜1.0 µA 3.0 V 15.0µA 45µA 65µA 3 µA 4.0 V 35.0µA 85µA 115µA 6 µA 5.0 V 70.0µA 140µA 180µA 11 µA 6.0 V 130µA 215µA 260µA 17 µA 11.3 OSC Type＝XT (OSC1&OSC2 Internal Cap about 10P); WDT－Enable ; Comparator － Disable ﹔PED=Enable Voltage/Frequency 1M 4M 10 M Sleep 2.1 V 50µA 120µA 290µA ＜1.0 µA 3.0 V 100µA 230µA 490µA 3 µA 4.0 V 210µA 400µA 650µA 6 µA 5.0 V 375µA 590µA 1.3mA 11 µA 6.0 V 645µA 850µA 1.6mA 17 µA 11.4 OSC Type＝HF (OSC1&OSC2 Internal Cap about 10P); WDT－Enable ; Comparator － Disable﹔PED=Enable Voltage/Frequency 4M 10 M 20 M Sleep 2.1 V 150µA 320µA X ＜1.0 µA 3.0 V 280µA 550µA 925µA 3 µA 4.0 V 510µA 910µA 1.5mA 6 µA 5.0 V 800µA 1.4mA 2.3mA 11 µA 6.0 V 1.3mA 1.9mA 3.2mA 17 µA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2005/6 Ver. 1.4 MDT10P23(CC ) 11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ V dd＝5.0 V Vpr≦1.8~2.2 V Vpr ﹕Vdd (Power Supply) 12. Port A Equivalent Circuit PA0-PA3 D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G QB Input Resistor Data Bus 0 TTL input level D QB Rea d Data I/P Latch G S 1 + VREF comparator level Compartor Control This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2005/6 Ver. 1.4 MDT10P23(CC ) PA4 D I/O Control Q I/O Control Latch C K Q B Port I/O Pin D Data O/P Latch Write Q B G Input Resistor Data Bus Data I/P Latch Rea d comparator enable D QB TTL Input Level G 3 3/4 VDD 1/2 VDD 1/4 VDD 2 Vref 1 S0 S1 0 CMR_4 CMR_5 PA5-PA7 D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G Data Bus Q B D QB Rea d G Data I/P Latch Input Resistor TTL Input Level This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 15 2005/6 Ver. 1.4 MDT10P23(CC ) Port B Equivalent Circuit D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G Data Bus Q B D QB Rea d Data I/P Latch Input Resistor TTL Input Level G This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 16 2005/6 Ver. 1.4 MDT10P23(CC ) 13. MCLRB and RTCC Input Equivalent Circuit R≒1K MCLRB Schmitt Trigger R≒1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 17 2005/6 Ver. 1.4 MDT10P23(CC ) 14. External Capacitor Selection For Crystal Oscillator @ V dd＝5.0 V Osc. Type Resonator Freq. Capacity Range 20 MHz 10 pF ~ 50 pF 10 MHz 20 pF ~ 50 pF 4 MHz 10 pF ~ 30 pF 10 MHz 10 pF ~ 50 pF 4 MHz 10 pF ~ 50 pF 1 MHz 20 pF ~50 pF 1 MHz 20 pF ~ 30 pF 455 K 20 pF ~30 pF 32 K 20 pF ~30 pF HF XT LF MDT10P23 OSC1 C1 OSC2 C2 To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 18 2005/6 Ver. 1.4