MDTIC MDT10P10BG

MDT10P10(BG)
1. General Description
This EPROM-Based 8-bit micro-controller
uses a fully static CMOS design
technology combines higher speeds and
smaller size with the low power and high
noise immunity.
On chip memory system includes 1.0 K
words of ROM, and 32 bytes of static
RAM.
2. Features
The followings are some of the features
on the hardware and software :
Fully CMOS static design
8-bit data bus
On chip ROM size : 1K words
Internal RAM size : 32 bytes
(25 general purpose registers, 7 special
registers)
36 single word instructions
14-bit instructions
2-level stacks
Operating voltage : 2.3V ~ 6.0 V
Operating frequency : 0 ~ 20 MHz
The most fast execution time is 200
ns under 20 MHz in all single cycle
instructions
except
the
branch
instructions
Addressing modes include direct,
indirect and relative addressing modes
Power-on Reset (POR), only available
with 8-bit programmable prescaler
4 types of oscillator can be selected
by programming option (Internal
Capacitor about 10p ):
RC-Low cost RC oscillator
LFXT-Low frequency crystal
oscillator
XTAL-Standard crystal oscillator
HFXT-High frequency crystal
oscillator
4 oscillator start-up time can be
selected by programming option:
150 µs, 20 ms, 40 ms, 80 ms
On-chip RC oscillator based
Watchdog Timer(WDT) can be operated
freely
12 I/O pins with their own independent
direction control
3. Applications
The application areas of this MDT10P10
range from appliance motor control and
high speed automotive to low power
remote transmitters/receivers, pointing
devices,
and
telecommunications
processors, such as Remote controller,
small
instruments,
chargers,
toy,
automobile and PC peripheral … etc.
while PED is Disable
Power edge-detector Reset (PED)
Sleep Mode for power saving
8-bit real time clock/counter(RTCC)
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P. 1
2006/4
VER1.1
MDT10P10(BG)
4. Pin Assignment
DIP / SOP
PA2
PA3
RTCC
/MCLR
Vss
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
SSOP
PA1
PA0
OSC1
OSC2
Vdd
PB7
PB6
PB5
PB4
PA2
PA3
RTCC
/MCLR
VSS
VSS
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA1
PA0
OSC1
OSC2
VDD
VDD
PB7
PB6
PB5
PB4
5. Pin Function Description
Pin Name
I/O
Function Description
PA0~PA3
I/O
Port A, TTL input level
PB0~PB7
I/O
Port B, TTL input level
RTCC
I
Real Time Clock/Counter, Schmitt Trigger input levels
/MCLR
I
Master Clear, Schmitt Trigger input levels
OSC1
I
Oscillator Input
OSC2
O
Oscillator Output
Vdd
Power supply
Vss
Ground
6. Memory Map
(A) Register Map
Address
Description
00
Indirect Addressing Register
01
RTCC
02
PC
03
STATUS
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P. 2
2006/4
VER1.1
MDT10P10(BG)
Address
Description
04
MSR
05
Port A
06
Port B
07~1F
Internal RAM, General Purpose Register
(1) IAR ( Indirect Address Register) : R0
(2) RTCC (Real Time Counter/Counter Register) : R1
(3) PC (Program Counter) : R2
Write PC, CALL --- always 0
LJUMP, JUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- always 0 (ROM 1.0K)
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTWI, RET --- from STACK
(4) STATUS (Status register) : R3
Bit
Symbol
Function
0
C
Carry bit
1
HC
Half Carry bit
2
Z
Zero bit
3
PF
Power loss Flag bit
4
TF
Time overflow Flag bit
5
page 0
Page select bit :
0 : 000H --- 1FFH
1 : 200H --- 3FFH
6—7
——
General purpose bit
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P. 3
2006/4
VER1.1
MDT10P10(BG)
(5) MSR (Memory Select Register) : R4
(6) PORT A : R5
PA3~PA0, I/O Register
(7) PORT B : R6
PB7~PB0, I/O Register
(8) TMR (Time Mode Register)
Bit
Symbol
Function
Prescaler Value
2—0
PS2—0
3
PSC
4
TCE
5
TCS
RTCC rate
WDT rate
0 0 0
1:2
1:1
0 0 1
1:4
1:2
0 1 0
1:8
1:4
0 1 1
1 : 16
1:8
1 0 0
1 : 32
1 : 16
1 0 1
1 : 64
1 : 32
1 1 0
1 : 128
1 : 64
1 1 1
1 : 256
1 : 128
Prescaler assignment bit :
0 — RTCC
1 — Watchdog Timer
RTCC signal Edge :
0 — Increment on low-to-high transition on RTCC pin
1 — Increment on high-to-low transition on RTCC pin
RTCC signal set :
0 — Internal instruction cycle clock
1 — Transition on RTCC pin
(9) CPIO A, CPIO B (Control Port I/O Mode Register)
The CPIO register is “write-only”
=“0”, I/O pin in output mode;
=“1”, I/O pin in input mode.
(10) EPROM Option by writer programming :
Oscillator Type
RC
Oscillator
Oscillator Start-up Time
150 µs,20ms,40ms,80ms
HFXT Oscillator
20 ms,40ms,80ms
XTAL Oscillator
20ms,40 ms,80ms
LFXT Oscillator
40 ms,80 ms
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P. 4
2006/4
VER1.1
MDT10P10(BG)
Watchdog Timer control
Watchdog timer disable all the time
Watchdog timer enable all the time
Power Edge Detect
Security bit
PED Disable
Security Disable
PED Enable
Security Enable
The default EPROM security is disable. Once the IC was set to enable, it can not set to
disable again.
(B) Program Memory
Address
000-3FF
3FF
Description
Program memory for MDT10P10
The starting address of the power on, external
reset or WDT time-out reset for MDT10P10
7. Reset Condition for all Registers
Register
Address
Power-On Reset
/MCLR or WDT Reset
CPIO A
--
1111 1111
1111 1111
CPIO B
--
1111 1111
1111 1111
TMR
--
- - 11 1111
- - 11 1111
IAR
00h
xxxx xxxx
uuuu uuuu
RTCC
01h
xxxx xxxx
uuuu uuuu
PC
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
000# #uuu
MSR
04h
111x xxxx
111u uuuu
PORT A
05h
- - - - xxxx
- - - - uuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
Note : u=unchanged, x=unknown, - =unimplemented, read as “0”
#=value depends on the condition of the following table
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P. 5
2006/4
VER1.1
MDT10P10(BG)
Condition
Status: bit 4
Status: bit 3
/MCLR reset (not during SLEEP)
u
u
/MCLR reset during SLEEP
1
0
WDT reset (not during SLEEP)
0
1
WDT reset during SLEEP
0
0
8. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010000 00000000
NOP
No operation
None
010000 00000001
CLRWT
Clear Watchdog timer
0→WT
010000 00000010
SLEEP
Sleep mode
0→WT, stop OSC TF, PF
010000 00000011
TMODE
Load W to TMODE register
W→TMODE
None
010000 00000100
RET
Return
Stack→PC
None
010000 00000rrr
CPIO
Control I/O port register
W→CPIO
010001 1rrrrrrr
STWR R
Store W to register
W→R
011000 trrrrrrr
LDR R, t
Load register
R→t
Z
111010 iiiiiiii
LDWI
Load immediate to W
I→W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3) ↔
R(4~7)]→t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1→t
Z
011010 trrrrrrr
INCRSZ R, t
Increment register, skip if zero
R + 1→t
None
011011 trrrrrrr
ADDWR R, t
Add W and register
W + R→t
C, HC, Z
011100 trrrrrrr
SUBWR R, t
Subtract W from register
R ﹣W→t
(R+/W+1→t)
C, HC, Z
011101 trrrrrrr
DECR R, t
Decrement register
R ﹣1→t
011110 trrrrrrr
DECRSZ R, t Decrement register, skip if zero R ﹣1→t
010010 trrrrrrr
ANDWR R, t
AND W and register
R ∩ W→t
Z
110100 iiiiiiii
ANDWI
AND W and immediate
i ∩ W→W
Z
010011 trrrrrrr
IORWR R, t
Inclu. OR W and register
R ∪ W→t
Z
110101 iiiiiiii
IORWI
Inclu. OR W and immediate
i ∪ W→W
Z
010100 trrrrrrr
XORWR R, t
Exclu. OR W and register
R ⊕ W→t
Z
110110 iiiiiiii
XORWI
Exclu. OR W and immediate
i ⊕ W→W
Z
011111 trrrrrrr
COMR R, t
Complement register
/R→t
Z
010110 trrrrrrr
RRR
Rotate right register
R(n) →R(n-1), C
→R(7), R(0)→C
C
R
I
i
i
i
R, t
TF, PF
None
r
None
Z
None
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P. 6
2006/4
VER1.1
MDT10P10(BG)
Mnemonic
Operands
Instruction Code
R, t
Function
Operating
Status
Rotate left register
R(n)→r(n+1),C→
R(0), R(7)→C
C
Clear working register
0→W
Z
Clear register
0→R
Z
010101 trrrrrrr
RLR
010000 1xxxxxxx
CLRW
010001 0rrrrrrr
CLRR
0000bb brrrrrrr
BCR
R, b
Bit clear
0→R(b)
None
0010bb brrrrrrr
BSR
R, b
Bit set
1→R(b)
None
0001bb brrrrrrr
BTSC R, b
Bit Test, skip if clear
Skip if R(b)=0
None
0011bb brrrrrrr
BTSS R, b
Bit Test, skip if set
Skip if R(b)=1
None
1000nn nnnnnnnn
LCALL n
Long CALL subroutine
n→PC,
PC+1→Stack
None
1010nn nnnnnnnn
LJUMP n
Long JUMP to address
n→PC
None
110000 nnnnnnnn
CALL
n
Call subroutine
n→PC,
PC+1→Stack
None
110001 iiiiiiii
RTWI
i
Return, place immediate to W
Stack→PC, i→W
None
11001n nnnnnnnn
JUMP
n
JUMP to address
n→PC
None
R
Note :
W
WT
TMODE
CPIO
TF
PF
PC
OSC
Inclu.
Exclu.
AND
:
:
:
:
:
:
:
:
:
:
:
Working register
Watchdog timer
TMODE mode register
Control I/O port register
Timer overflow flag
Power loss flag
Program Counter
Oscillator
Inclusive ‘∪’
Exclusive ‘♁’
Logic AND ‘∩’
b
t
:
:
R
C
HC
Z
/
x
i
n
:
:
:
:
:
:
:
:
Bit position
Target
0
: Working register
1
: General register
General register address
Carry flag
Half carry
Zero flag
Complement
Don’t care
Immediate data ( 8 bits )
Immediate address
9. Electrical Characteristics
(A) Operating Voltage & Frequency
Vdd ﹕2.3V ~ 6.0 V
Frequency﹕0 Hz ~ 20 MHz
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P. 7
2006/4
VER1.1
MDT10P10(BG)
(B) Input Voltage
@ Vdd=5.0 V, Temperature=25 ℃
Port
Min.
Max.
PA, PB
Vss
1.0 V
RTCC, /MCLR
Vss
1.0V
PA, PB
2.0 V
Vdd
RTCC, /MCLR
3.1 V
*Threshold Voltage :
Port A, Port B Vth=1.5V
RTCC/MCLR V Vil=1.2V, Vih=3.0V
Vdd
Vil
Vih
(Schmitt Trigger)
(C) Output Voltage﹕
@ Vdd=5.0 V, Temperature=25 ℃, the typical value as followings :
PA, PB Port
Ioh=-20.0 mA
Voh=3.6 V
Iol=20.0 mA
Vol=0.6 V
Ioh=-5.0 mA
Voh=4.6 V
Iol=5.0 mA
Vol=0.3 V
(D) Leakage Current
@ Vdd=5.0 V, Temperature=25 ℃, the typical value as followings :
Iil
- 0.1µA (Max.)
Iih
+ 0.1µA (Max.)
(E) Sleep Current
@WDT-Disable, PED-Disable Temperature=25 ℃, the typical value as followings :
Vdd=2.3 V
Idd<0.1 µA
Vdd=3.0 V
Idd<0.1 µA
Vdd=4.0 V
Idd<0.1 µA
Vdd=5.0 V
Idd<0.1 µA
Vdd=6.0V
Idd<0.1 µA
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P. 8
2006/4
VER1.1
MDT10P10(BG)
@WDT-Enable, PED-Disable Temperature=25 ℃, the typical value as followings :
Vdd=2.3 V
Idd<1.0 µA
Vdd=3.0 V
Idd=3.0 µA
Vdd=4.0 V
Idd=7.5 µA
Vdd=5.0 V
Idd=16.0 µA
Vdd=6.0 V
Idd=26.0 µA
(F) Typical Operating Current : (Temperature=25 ℃)
(i) OSC Type=RC (OSC1&OSC2 Internal Cap about 10P);
WDT-Enable;
The IC may not oscillate properly if the resistance of rext less than 4.7K.
The minimum resistance of rext must be more than 4.7K.
@ Vdd=5.0 V
Cext. (F)
0P
3P
20P
Rext. (Ohm)
Frequency (Hz)
Current (A)
4.7 K
11.5 M
1.2 mA
10.0 K
5.3 M
700 µA
47.0 K
1.3 M
250 µA
100.0 K
628 K
200 µA
300.0 K
215 K
140 µA
470.0 K
135 K
135 µA
4.7 K
9.3 M
1.1 mA
10.0 K
4.4 M
540 µA
47.0 K
1.05 M
225 µA
100.0 K
540 K
160 µA
300.0 K
170 K
130 µA
470.0 K
110 K
120 µA
4.7 K
5.4 M
630 µA
10.0 K
2.4 M
340 µA
47.0 K
600 K
170 µA
100.0 K
285 K
140 µA
300.0 K
110 K
120 µA
470.0 K
55 K
110 µA
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P. 9
2006/4
VER1.1
MDT10P10(BG)
Cext. (F)
100P
300P
Rext. (Ohm)
Frequency (Hz)
Current (A)
4.7 K
2.0 M
310 µA
10.0 K
1.0 M
220 µA
47.0 K
230 K
140 µA
100.0 K
110 K
130 µA
300.0 K
35 K
110 µA
470.0 K
20 K
100 µA
4.7 K
900 K
200 µA
10.0 K
400 K
180 µA
47.0 K
90 K
115 µA
100.0 K
40 K
110 µA
300.0 K
14 K
105 µA
470.0 K
9.2 K
100 µA
(ii) OSC Type=LF (OSC1 &OSC2 Internal Cap);
Voltage/Frequency
WDT-Disable ﹔PED=Enable
32 K
455 K
(Ext C=50P) (Ext C=50P)
1M
@2.4V 35 µA
Sleep
<0.1 µA
2.3 V
11 µA
22 µA
3.0 V
19 µA
40 µA
50 µA
<0.1 µA
4.0 V
40 µA
75 µA
85 µA
<0.1 µA
5.0 V
70µA
120 µA
140 µA
<0.1 µA
6.0 V
125 µA
200 µA
220 µA
<0.1 µA
(iii) OSC Type=XT(OSC1&OSC2 Internal Cap about 10P);
Voltage/Frequency
WDT-Enable
1M
4M
10 M
Sleep
2.3 V
32 µA
100 µA
230 µA
<1.0 µA
3.0 V
75 µA
180 µA
385 µA
3.0 µA
4.0 V
155 µA
300 µA
610 µA
7.5 µA
5.0 V
250 µA
440 µA
950 µA
16 µA
6.0 V
400 µA
650 µA
1.2 mA
27 µA
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P. 10
2006/4
VER1.1
MDT10P10(BG)
(iv) OSC Type=HF (OSC1& OSC2 Internal Cap about 10P)﹔ WDT-Enable
Voltage/Frequency
4M
10 M
20 M
Sleep
@2.5V 590 µA <1.0 µA
2.3 V
100 µA
230 µA
3.0 V
200 µA
420 µA
4.0 V
340 µA
650 µA
1.1 mA
7.5 µA
5.0 V
540 µA
900 µA
1.7 mA
16 µA
6.0 V
900 µA
1.25 mA
2.35 mA
27 µA
750 µA
3.0 µA
(G)The basic WDT time-out cycle time
@ Vdd=5.0v ,Temperature=25 ℃, the typical value as followings :
Voltage (V)
Basic WDT time-out cycle time (ms)
2.3
23.5
3.0
21.5
4.0
20.3
5.0
18.3
6.0
17.5
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P. 11
2006/4
VER1.1
MDT10P10(BG)
(H) Reset & Watchdog Timer Timing
/MCLR, WATCHDOG timer and internal POR timing
Vdd
/MCLR
Internal POR
Tost
OST Time-out
Internal Reset
WDT reset
Tmclr
I/O pin
Tost
Twdt
Tio
Symbol
Description
Tio
Min
Typ
Max
Unit
15
20
24
ms
100
ns
Tost
Oscillator start up time
Tio
I/O floating from /MCLR low
Tmclr
/MCLR pulse width
500
Twdt
Watchdog timer time-out period
(No postscaler)
15
ns
20
24
ms
(I) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd=5.0 V(PED:Enable)
Vpr≦1.6~1.9 V
Vpr ﹕Vdd (Power Supply)
PS.IF PED_Enable then Internal Power_on_reset will be off
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P. 12
2006/4
VER1.1
MDT10P10(BG)
(J) MCLRB Filter:@ Vdd=5.0v
Wm >1.2us
Wm : Filter pulse width (low) in /MCLR pin.
10. Port A and Port B Equivalent Circuit
Working Register
QB
D
Data I/P
I/O
Control
Latch
I/O Control
CK
Q
Port I/O Pin
D
Data O/P
Latch
Write
CK
Q
Data Bus
D
QB
Read
Data I/P
Latch
Input Resistor
TTL Input Level
CK
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P. 13
2006/4
VER1.1
MDT10P10(BG)
11. MCLRB and RTCC Input Equivalent Circuit
R≒1K
MCLRB
Schmitt Trigger
R≒1K
RTCC
Schmitt Trigger
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P. 14
2006/4
VER1.1
MDT10P10(BG)
12. Block Diagram
Stack Two Levels
RAM
25×8
EPROM
1024×14 (MDT10P10)
Port
PA0~PA3
4 bits
Port A
9 or10 bits
14 bits
9 or 10 bits
Program Counters
Instruction
Register
Special Register
D0~D7
OSC1
OSC2
MCLR
Port B
Oscillator Circuit
Instruction
Decoder
Port
PB0~PB7
8 bits
Control Circuit
Data 8-bit
Power on Reset
Power Down Reset
Working Register
Status Register
ALU
8-bit Timer/Counter
WDT/OST
Timer
Prescale
RTCC
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P. 15
2006/4
VER1.1
MDT10P10(BG)
13. Internal Capacitor Selection For Crystal Oscillator
@ Vdd=3.0V~5.0 V
Osc. Type Resonator Freq.
HF
XT
LF
C1
C2
20 MHz
0 pF ~10 pF
0 pF ~20 pF
10 MHz
0 pF ~50 pF
0 pF ~100 pF
4 MHz
0 pF ~30 pF
0 pF ~100 pF
10 MHz
0 pF ~30 pF
0 pF ~50 pF
4 MHz
0 pF ~50 pF
0 pF ~100 pF
1 MHz
0 pF ~30 pF
0 pF ~50 pF
1 MHz
5 pF ~10 pF
5 pF ~10 pF
455 K
10 pF ~50 pF
10 pF ~50 pF
32 K
10 pF ~30 pF
20 pF ~50 pF
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range
can be recommended for reference, but the higher capacitance also increases the start-up time.
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P. 16
2006/4
VER1.1