SN74AHCT244-EP OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCLS493A – MAY 2003 – REVISED JUNE 2003 D D D D D D D D D DW OR PW PACKAGE (TOP VIEW) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† EPIC (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 1000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. description/ordering information This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74AHCT244 is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE‡ TA –55°C 55°C to 125°C ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC – D Tape and reel SN74AHCT244MDWREP TSSOP – PW Tape and reel SN74AHCT244MPWREP AHCT244MEP AHT244EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AHCT244-EP OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCLS493A – MAY 2003 – REVISED JUNE 2003 FUNCTION TABLE (each 4-bit buffer/driver) INPUTS OE A OUTPUT Y L H H L L L H X Z logic symbol† 1OE 1A1 1A2 1A3 1A4 1 EN 2OE 18 2 4 16 6 14 12 8 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 EN 11 9 13 7 15 5 17 3 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 POST OFFICE BOX 655303 19 11 9 13 7 15 5 17 3 • DALLAS, TEXAS 75265 2Y1 2Y2 2Y3 2Y4 2Y1 2Y2 2Y3 2Y4 SN74AHCT244-EP OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCLS493A – MAY 2003 – REVISED JUNE 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7 recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage VO IOH Output voltage IOL TA Low-level output current MIN MAX 4.5 5.5 High-level input voltage 2 V V 0.8 V 0 5.5 V 0 VCC –8 mA 8 mA 125 °C High-level output current Operating free-air temperature UNIT –55 V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH IOH = –50 mA IOH = –8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 IOZ II VO = VCC or GND VI = 5.5 V or GND ICC VI = VCC or GND, One input at 3.4 V, Other inputs at VCC or GND ∆ICC‡ Ci IO = 0 VI = VCC or GND VO = VCC or GND MIN 4.4 TA = 25°C TYP MAX 4.5 MIN 4.4 3.94 UNIT V 3.8 0.1 0.1 0.36 0.44 5.5 V ±0.25 ±2.5 mA 0 V to 5.5 V V ±0.1 ±1 mA 5.5 V 4 40 mA 5.5 V 1.35 1.5 mA 5V 2.5 10 Co 5V 3 ‡ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 MAX • DALLAS, TEXAS 75265 pF pF 3 SN74AHCT244-EP OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCLS493A – MAY 2003 – REVISED JUNE 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF tsk(o) MIN TA = 25°C TYP MAX MIN MAX 5.4 7.4 1 8.5 5.4 7.4 1 8.5 7.7 10.4 1 12 7.7 10.4 1 12 5 9.4 1 10 5 9.4 1 10 5.9 8.4 1 9.5 5.9 8.4 1 9.5 8.2 11.4 1 13 8.2 11.4 1 13 8.8 11.4 1 13 8.8 11.4 1 13 CL = 50 pF 1 UNIT ns ns ns ns ns ns ns noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER VOH(V) VIH(D) MIN Quiet output, minimum dynamic VOH TYP MAX 4.1 High-level dynamic input voltage V 2 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. UNIT V 0.8 V TYP UNIT 8.2 pF operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz SN74AHCT244-EP OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCLS493A – MAY 2003 – REVISED JUNE 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CAHCT244MPWREPG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT244MDWREP ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT244MPWREP ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03657-01XE ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03657-01YE ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF SN74AHCT244-EP : SN74AHCT244 • Catalog: SN74AHCT244-Q1 • Automotive: • Military: SN54AHCT244 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Automotive • Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AHCT244MDWREP Package Package Pins Type Drawing SOIC SN74AHCT244MPWREP TSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHCT244MDWREP SOIC DW 20 2000 367.0 367.0 45.0 SN74AHCT244MPWREP TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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