TPS5402 www.ti.com SLVSBK4 – SEPTEMBER 2012 3.5-V TO 28-V INPUT VOLTAGE, 1.7-A OUTPUT CURRENT, NON-SYNCHRONOUS STEP-DOWN REGULATOR WITH INTEGRATED MOSFET Check for Samples: TPS5402 FEATURES 1 • • • • • • • • • • • 3.5-V to 28-V Wide Input Voltage Range Up to 1.7-A Maximum Continuous Output Loading Current Pulse Skipping Mode to Achieve High Light Load Efficiency High Light Load Efficiency Frequency Spread Spectrum to Reduce EMI Adjustable 50-kHz to 1.1-MHz Switching Frequency Set by an External Resistor (Leave pin ROSC floating. Set frequency to 120 kHz and ground connection to 70 kHz) Frequency Spread Spectrum to Ease EMI Issue Peak Current-Mode Control Cycle-by-Cycle Over Current Protection External Soft Start Available in SOIC8 Package APPLICATIONS • • • 5-V, 9-V, 12-V and 24-V Distributed Power Systems Consumer Applications Such as Home Appliances, Set-Top Boxes, CPE Equipment, LCD Displays, Peripherals, and Battery Chargers Industrial and Car Entertainment Power Supplies DESCRIPTION The TPS5402 is a monolithic non-synchronous buck regulator with wide operating input voltage range from 3.5 V to 28 V. Current mode control with internal slope compensation is implemented to reduce component count. TPS5402 also features a light load pulse skipping mode, which allows for a power loss reduction from the input power supply to the system at light loading. The switching frequency of the converters can be set from 50 kHz to 1.1 MHz with an external resistor. Frequency spread spectrum operation is introduced for EMI reduction. A cycle-by-cycle current limit with frequency fold back protects the IC at over loading condition. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS5402 SLVSBK4 – SEPTEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TYPICAL APPLICATION Cboot Lo Vout Cout D 8 1 BOOT LX Cin 7 2 Vin VIN GND TPS5402 3 Rc 6 ROSC Cc COMP Rfb1 Rosc 5 4 VSENSE SS Rfb2 Css FUNCTIONAL BLOCK DIAGRAM VIN 165C Thermal Shutdown Shutdown Logic Shutdown Boot Charge Boot UVLO Minimum Clamp VSENSE 2.1V PWM Comparator Gate Drive Logic 0.8V Voltage Reference SS Σ Discharge Logic BOOT PWM Latch gm 2uA 9A/V Current Sense R Q S Slope Compensation LX Shutdown VSENSE Frequency Shift Oscillator GND COMP Maximum Clamp ROSC 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 TPS5402 www.ti.com SLVSBK4 – SEPTEMBER 2012 PCB LAYOUT VOUT GROUND LX 8 1 BOOT VIN 2 VIN GND 7 3 ROSC 4 SS COMP 6 VSENSE 5 ORDERING INFORMATION (1) TA PACKAGE –40°C to 85°C (1) (2) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TPS5402DR TPS5402 8-pin SOIC (D) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. PIN OUT D PACKAGE (TOP VIEW) BOOT 1 8 LX VIN 2 7 GND ROSC 3 6 COMP SS 4 5 VSENSE TERMINAL FUNCTIONS NAME NO. DESCRIPTION BOOT 1 A 0.1-µF bootstrap capacitor is required between BOOT and LX. VIN 2 Input supply voltage, 3.5 V to 28 V ROSC 3 Switching frequency program pin. Connect a resistor to this pin to set the switching frequency. Connect the pin to ground for a default 70-kHz switching frequency. Leave the pin open for 120-kHz switching frequency. SS 4 Soft start pin. An external capacitor connected to this pin sets the output rise time. VSENSE 5 Output voltage feedback pin COMP 6 Error amplifier output and input to the PWM comparator. Connect frequency compensation components to this pin. GND 7 Ground LX 8 Switching node to external inductor Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 3 TPS5402 SLVSBK4 – SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Voltage range at VIN, LX –0.3 to 30 V Voltage range at LX (maximum withstand voltage transient < 20 ns) –5 to 30 V Voltage from BOOT to LX –0.3 to 7 V Voltage at VSENSE –0.3 to 7 V Voltage at SS –0.3 to 3 V Voltage at ROSC –0.3 to 3 V Voltage at COMP –0.3 to 3 V Voltage at GND –0.3 to 0.3 V TJ Operating junction temperature range –40 to 125 °C TSTG Storage temperature range –55 to 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 3.5 28 V TA Ambient temperature –40 85 °C THERMAL INFORMATION TPS5402 THERMAL METRIC (1) D UNITS 8 PINS θJA Junction-to-ambient thermal resistance (2) 116.7 θJCtop Junction-to-case (top) thermal resistance (3) 62.4 θJB Junction-to-board thermal resistance (4) 57.0 (5) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (6) 56.5 θJCbot Junction-to-case (bottom) thermal resistance (7) N/A (1) (2) (3) (4) (5) (6) (7) 4 14.5 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 TPS5402 www.ti.com SLVSBK4 – SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS TA = -40°C to 125°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input Voltage range IDDQ_nsw Non switching quiescent power supply current 3.5 UVLO VIN under voltage lockout VSENSE > 0.9 V 28 100 V µA Rising VIN 3.5 V Hysteresis 200 mV FEEDBACK AND ERROR AMPLIFIER VSENSE Regulated output voltage VIN = 12 V Gm_EA Error amplifier trans-conductance -2 µA < ICOMP < 2 µA, VCOMP = 1 V 0.776 0.8 0.824 V 92 µs Igm Error amplifier source/sink current VCOMP = 1 V, 100 mV overdrive ±7 µA Gm_SRC COMP voltage to inductor current Gm VIN = 12 V 9 A/V 300 mA 2 µA PFM MODE AND SOFT-START Ith Pulse skipping mode switch current threshold ISS Charge current OSCILLATOR fSW_BK Switching frequency range fSW Programmable frequency Set by external resistor ROSC 50 ROSC = GND 1100 kHz 70 ROSC = OPEN 120 ROSC = 85.5 kΩ 300 fjitter Frequency spread spectrum in percentage of fSW VIN = 12 V ±6 fswing Jittering swing frequency in percentage of fSW VIN = 12 V 1/512 tmin_on Minimum on time VIN = 12 V, TA = 25°C Dmax Maximum duty ratio VIN = 12 V kHz % 200 ns 93 % CURRENT LIMIT ILIMIT Peak inductor current limit VIN = 12 V 2.2 2.5 3.1 A VIN = 12 V 120 240 mΩ Rising temperature 165 MOSFET ON-RESISTANCE Rdson_HS On resistance of high side FET THERMAL SHUTDOWN TTRIP Thermal protection trip point Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 °C 5 TPS5402 SLVSBK4 – SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS TA = 25°C, VIN = 12 V, VOUT = 3.3 V, fSW = 120 kHz (unless otherwise noted) 90.00% 87.00% 86.00% 88.00% 85.00% 84.00% Efficiency (%) Efficiency (%) 86.00% 84.00% 82.00% 83.00% 82.00% 81.00% 80.00% 80.00% 79.00% 78.00% 78.00% 77.00% 76.00% 0 0 0.5 1 1.5 2 0.01 0.02 0.03 0.04 0.05 Iout (A) Iout (A) Figure 1. Efficiency VIN = 12 V, VOUT = 3.3 V Figure 2. Efficiency VIN = 12 V, VOUT = 3.3 V Vin=6.5V Io=0.1A 3.39 3.39 Io=2.0A Vin=12V 3.37 3.37 Vin=28V 3.35 3.35 Vout (V) Vout (V) 0.06 2.5 3.33 3.31 3.33 3.31 3.29 3.29 3.27 3.27 3.25 3.25 0 0.5 1 1.5 2 2.5 Iout (A) 0 5 10 15 Vin (V) 20 Figure 3. Load Regulation VIN = 12 V, VOUT = 3.3 V Figure 4. Line Regulation VOUT = 3.3 V 25 30 Vin Vin Vout Vout LX LX IL IL Figure 5. Startup 2-A Preset Loading 6 Figure 6. Steady State IO = 2 A Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 TPS5402 www.ti.com SLVSBK4 – SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, VOUT = 3.3 V, fSW = 120 kHz (unless otherwise noted) Vin Vin Vout Vout LX LX IL IL Figure 7. Steady State IO = 100 mA Figure 8. Load Transient IO = 0.1 A to 2 A Vin Vout Vin Vout IL IL Figure 9. Short Circuit Protection Figure 10. Short Circuit Recovery Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 7 TPS5402 SLVSBK4 – SEPTEMBER 2012 www.ti.com OVERVIEW The TPS5402 is a 28-V, 1.7-A, step-down (buck) converter with an integrated high-side N-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS5402’s switching frequency is adjustable with an external resistor or fixed by connecting the frequency program pin to GND or leaving it unconnected. The TPS5402 starts switching at VIN equal to 3.5 V. The operating current is 100 μA typically when not switching and under no load. When the device is disabled, the supply current is 1 μA typically. The integrated 120-mΩ high-side MOSFET allows for high efficiency power supply designs with continuous output currents up to 1.7 A. The TPS5402 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pins. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls below a preset threshold of 2.1 V typically. By adding an external capacitor, the slow start time of the TPS5402 can be adjustable which enables flexible output filter selection. To improve the efficiency at light load conditions, the TPS5402 enters a special pulse skipping mode when the peak inductor current drops below 300 mA typically. The frequency foldback reduces the switching frequency during startup and over current conditions to help control the inductor current. The thermal shut down gives the additional protection under fault conditions. DETAILED DESCRIPTION Adjustable Frequency PWM Control The TPS5402 uses an external resistor to adjust the switching frequency. Connecting the ROSC pin to ground fixes the switching frequency at 70 kHz, leaving it open gives 120-kHz switching frequency. Figure 11. ROSC vs Switching Frequency ROSC (kW) = 21.82 × fSW -1.167 (1) For operation at 300 kHz, an 85.5-kΩ resistor is required. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 TPS5402 www.ti.com SLVSBK4 – SEPTEMBER 2012 Pulse Skipping Mode The TPS5402 is designed to operate in pulse skipping mode at light load currents to boost light load efficiency. When the peak inductor current is lower than 300 mA typically, the COMP pin voltage falls to 0.5 V typically and the device enters pulse skipping mode. When the device is in pulse skipping mode, the COMP pin voltage is clamped at 0.5 V internally which prevents the high side integrated MOSFET from switching. The peak inductor current must rise above 300 mA for the COMP pin voltage to rise above 0.5 V and exit pulse skipping mode. Since the integrated current comparator catches the peak inductor current only, the average load current entering pulse skipping mode varies with the applications and external output filters. Voltage Reference (VSENSE) The voltage reference system produces a ±3% accuracy voltage reference by scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8 V. Bootstrap Voltage (BOOT) The TPS5402 has an integrated boot regulator and requires a 0.1-µF ceramic capacitor between the BOOT and LX pins to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS5402 is designed to operate at 100% duty cycle as long as the BOOT to LX pin voltage is greater than 2.1 V typically. Programmable Slow Start Using SS Pin It is recommended to program the slow start time externally because no slow start time is implemented internally. The TPS5402 effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output accordingly. A capacitor (CSS) on the SS pin to ground implements a slow start time. The TPS5402 has an internal pull-up current source of 2 μA that charges the external slow start capacitor. The equation for the slow start time (10% to 90%) is shown in Equation 2. The internal Vref is 0.8 V and the ISS current is 2 μA. C (nF) ´ Vref (V) t ss (ms) = ss Iss (mA) (2) The slow start time should be set between 1 ms to 10 ms to ensure good start-up behavior. The slow start capacitor should be no more than 27 nF. If during normal operation, the input voltage drops below the VIN UVLO threshold, or a thermal shutdown event occurs, the TPS5402 stops switching. Error Amplifier The TPS5402 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation components are connected between the COMP pin and ground. Slope Compensation To prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the TPS5402 adds a built-in slope compensation which is a compensating ramp to the switch current signal. Overcurrent Protection and Frequency Shift The TPS5402 implements current mode control that uses the COMP pin voltage to turn off the high-side MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared; when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limits the output current. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 9 TPS5402 SLVSBK4 – SEPTEMBER 2012 www.ti.com The TPS5402 provides robust protection during short circuits. There is potential for overcurrent runaway in the output inductor during a short circuit at the output. The TPS5402 solves this issue by increasing the off time during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 V to 0.8 V on the VSENSE pin. The relationship between the switching frequency and the VSENSE pin voltage is shown in Table 1. Table 1. Switching Frequency Conditions SWITCHING FREQUENCY VSENSE PIN VOLTAGE fSW VSENSE ≥ 0.6 V fSW/2 0.6 V > VSENSE ≥ 0.4 V fSW/4 0.4 V > VSENSE ≥ 0.2 V fSW/8 0.2 V > VSENSE Spread Spectrum In order to reduce EMI, TPS5402 introduces frequency spread spectrum. The jittering span is ±6% of the switching frequency with 1/512 swing frequency. Overvoltage Transient Protection The TPS5402 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin voltage goes above 109% × Vref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls below 107% × Vref, the high-side MOSFET will be enabled again. Inductor Selection The higher operating frequency allows the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of switching loss and MOSFET gate charge losses. In addition to this basic trade-off, the effect of the inductor value on ripple current and low current operation must also be considered. The ripple current depends on the inductor value. The inductor ripple current (iL) decreases with higher inductance or higher frequency and increases with higher input voltage (VIN). Accepting larger values of iL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. To calculate the value of the output inductor, use Equation 3. LIR is a coefficient that represents inductor peakto-peak ripple to DC load current. It is recommended to set LIR to 0.1 ~ 0.3 for most applications. Actual core loss of the inductor is independent of core size for a fixed inductor value, but it is very dependent on the inductance value selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. It results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate. It is important that the RMS current and saturation current ratings are not exceeding the inductor specification. The RMS and peak inductor current can be calculated from Equation 5 and Equation 6. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 TPS5402 www.ti.com L= SLVSBK4 – SEPTEMBER 2012 VIN - VOUT V × OUT IO × LIR VIN × fsw (3) V - VOUT V DiL = IN × OUT IO VIN × fsw (4) VOUT × (VINmax - VOUT ) 2 ) VINmax × L × fsw 2 = IO + 12 Di = IO + L 2 ( iLRMS ILpeak (5) (6) For this design example, use LIR = 0.3 and the inductor is calculated to be 5.40 µH with VIN = 12 V. Choose 4.7 µH value for the standard inductor and the peak to peak inductor ripple is about 34% of 1-A DC load current. Output Capacitor Selection There are two primary considerations for selecting the value of the output capacitor. The output capacitors are selected to meet load transient and output ripple’s requirements. Equation 7 gives the minimum output capacitance to meet the transient specification. For this example, L = 4.7 µH, ΔIOUT = 1 A – 0.0 A = 1 A and ΔVOUT = 500 mV (10% of regulated 5 V). Using these numbers gives a minimum capacitance of 1 µF. A standard 22-µF ceramic is chosen in the design. Co > DIOUT 2 × L 2 × VOUT × DVOUT (7) The selection of CO is driven by the effective series resistance (ESR). Equation 8 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fSW is the switching frequency, ΔVOUT is the maximum allowable output voltage ripple, and ΔiL is the inductor ripple current. In this case, the maximum output voltage ripple is 50 mV (1% of regulated 5 V). From Equation 4, the output current ripple is 1 A. From Equation 8, the minimum output capacitance meeting the output voltage ripple requirement is 2.5 µF with 3-mΩ ESR resistance. 1 1 Co > × D V 8 × fsw OUT - ESR DiL (8) After considering both requirements, for this example, one 22-µF, 6.3-V X7R ceramic capacitor with 3-mΩ ESR should be used. Input Capacitor Selection A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These capacitors should be connected as close as physically possible to the input pins of the converters as they handle the RMS ripple current shown in Equation 9. For this example, IOUT = 1 A, VOUT = 5 V, minimum VINmin = 9.6 V, from Equation 9, the input capacitors must support a ripple current of 1-A RMS. IINRMS = IOUT × VOUT (VINmin - VOUT ) × VINmin VINmin (9) The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 10. Using the design example values, IOUTmax = 1 A, CIN = 10 µF, fSW = 300 kHz, yields an input voltage ripple of 83 mV. I × 0.25 DVIN = OUT max CIN × fSW (10) To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 11 TPS5402 SLVSBK4 – SEPTEMBER 2012 www.ti.com Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 165°C, the device reinitiates the power up sequence. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS5402 PACKAGE OPTION ADDENDUM www.ti.com 13-Dec-2012 PACKAGING INFORMATION Orderable Device Status (1) TPS5402DR ACTIVE Package Type Package Pins Package Qty Drawing SOIC D 8 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) CU NIPDAU MSL Peak Temp Samples (3) (Requires Login) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5402DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5402DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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