User's Guide
SLVU523 – September 2011
TPS54519EVM-037, 5-A, SWIFT™ Regulator
Evaluation Module
The TPS54519EVM-037 evaluation module allows designers to evaluate the TPS54519 dc/dc converter.
This user's guide contains a description of the test setup and results and provides the schematic, board
art, and bill of materials of the EVM.
1
2
3
4
Contents
Introduction .................................................................................................................. 2
Test Setup and Results .................................................................................................... 4
Board Layout ............................................................................................................... 11
Schematic and Bill of Materials .......................................................................................... 13
List of Figures
1
TPS54519EVM-037 Efficiency ............................................................................................ 5
2
TPS54519EVM-037 Low Current Efficiency............................................................................. 5
3
TPS54519EVM-037 Load Regulation .................................................................................... 6
4
TPS54519EVM-037 Line Regulation ..................................................................................... 6
5
TPS54519EVM-037 Transient Response
6
TPS54519EVM-037 Loop Response
7
8
9
10
11
12
13
14
15
16
17
18
............................................................................... 7
.................................................................................... 7
TPS54519EVM-037 Output Ripple ...................................................................................... 8
TPS54519EVM-037 Input Ripple ........................................................................................ 8
TPS54519EVM-037 Start-Up Relative to VIN ........................................................................... 9
TPS54519EVM-037 Start-Up Relative to Enable ...................................................................... 9
TPS54519EVM-037 Shutdown Relative to VIN ........................................................................ 10
TPS54519EVM-037 Shutdown Relative to EN ........................................................................ 10
TPS54519EVM-037 Top-Side Layout .................................................................................. 11
TPS54519EVM-037 Bottom-Side Layout .............................................................................. 12
TPS54519EVM-037 Layout 2 ............................................................................................ 12
TPS54519EVM-037 Layout 3 ............................................................................................ 13
TPS54519EVM-037 Top-Side Assembly ............................................................................... 13
TPS54519EVM-037 Schematic.......................................................................................... 14
List of Tables
1
Input Voltage and Output Current Summary ............................................................................ 2
2
TPS54519EVM-037 Performance Specification Summary ............................................................ 2
3
Output Voltages Available ................................................................................................. 3
4
EVM Connectors and Test Points ........................................................................................ 4
5
TPS54519EVM-037 Bill of Materials .................................................................................... 15
6
Label Marking .............................................................................................................. 15
SWIFT is a trademark of Texas Instruments.
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1
Introduction
1
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Introduction
This user's guide contains background information for the TPS54519 as well as support documentation for
the TPS54519EVM-037 evaluation module (also called PWR037). Also included are the performance
specifications, the schematic, and the bill of materials for the TPS54519EVM-037.
1.1
Background
The TPS54519 dc/dc converter is designed to provide up to a 5-A output from an input voltage source of
2.95 V to 6 V. Rated input voltage and output current range for the evaluation module are given in
Table 1. This evaluation module is designed to demonstrate the small, printed-circuit-board areas that can
be achieved when designing with the TPS54519 regulator. The switching frequency is externally set at a
nominal 1000 kHz. The high-side and low-side MOSFETs are incorporated inside the TPS54519 package
along with the gate drive circuitry. The low, drain-to-source on-resistance of the MOSFETs allows the
TPS54519 to achieve high efficiencies and helps keep the junction temperature low at high output
currents. The compensation components are external to the integrated circuit (IC), and an external divider
allows for an adjustable output voltage. Additionally, the TPS54519 provides adjustable slow start and
undervoltage lockout inputs. The absolute maximum input voltage is 7 V for the TPS54519EVM-037.
Table 1. Input Voltage and Output Current Summary
1.2
EVM
INPUT VOLTAGE RANGE
OUTPUT CURRENT RANGE
TPS54519EVM-037
VIN = 3 V to 6 V
0 A to 5 A
Performance Specification Summary
A summary of the TPS54519EVM-037 performance specifications is provided in Table 2. Specifications
are given for an input voltage of VIN = 5 V and an output voltage of 1.8 V, unless otherwise specified. The
TPS54519EVM-037 is designed and tested for VIN = 3 V to 6 V. The ambient temperature is 25°C for all
measurements, unless otherwise noted.
Table 2. TPS54519EVM-037 Performance Specification Summary
SPECIFICATION
TEST CONDITIONS
VIN operating voltage range
MIN
TYP
MAX
3
5
6
V
VIN start voltage
2.794
V
VIN stop voltage
2.595
V
Output voltage set point
1.8
Output current range
VIN = 3 V to 6 V
Line regulation
IO = 2.5 A, VIN = 3 V to 6 V
±0.1%
Load regulation
VIN = 5 V, IO = 0 A to 5 A
0
±0.6%
V
5
A
IO = 1.25 A to 3.75 A,
slew rate = 0.5 A/µs
Voltage change
–72
Recovery time
100
μs
IO = 3.75 A to 1.25 A,
slew rate = 0.5 A/µs
Voltage change
72
mV
Recovery time
100
μs
73
kHz
Load transient response
mV
Loop bandwidth
VIN = 3.3 V, IO = 5 A
Phase margin
VIN = 3.3 V , IO = 5 A
54
°
Input ripple voltage
IO = 5 A
150
mVPP
Output ripple voltage
IO = 5 A
<10
mVPP
Output rise time
Operating frequency
Maximum efficiency
2
UNIT
TPS54519EVM-037, VIN = 3 V, IO = 0.5 A
TPS54519EVM-037, 5-A, SWIFT™ Regulator— Evaluation Module
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2.5
ms
1000
kHz
94.6%
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Introduction
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1.3
Modifications
These evaluation modules are designed to provide access to the features of the TPS54519. Some
modifications can be made to this module.
1.3.1
Output Voltage Set Point
The voltage divider R9 and R10 is used to set the output voltage. To change the output voltage of the
EVM, it is necessary to change the value of resistor R9. Changing the value of R9 can change the output
voltage above 0.6 V. The value of R9 for a specific output voltage can be calculated using Equation 1.
Use 10 kΩ for R10.
V
R9 = R10 ×( OUT - 1)
0.6 V
(1)
Table 3 lists the R9 and R10 values for some common output voltages. Note that VIN must be in a range
so that the minimum on-time is greater than 80 ns, and the maximum duty cycle is less than 92%. The
values given in Table 3 are standard values, not the exact value calculated using Equation 1.
Table 3. Output Voltages Available
1.3.2
Output Voltage (V)
R9 Value (kΩ)
R10 Value (kΩ)
1
6.65
10
1.2
10
10
1.5
15
10
1.8
20
10
2.5
31.6
10
Slow-Start Time
The slow-start time can be adjusted by changing the value of C7. Use Equation 2 to calculate the required
value of C7 for a desired slow-start time
C7(nF) =
2.4(mA ) ´ Tss (ms )
0.6( V )
(2)
C7 is set to 0.01 μF on the EVM for a default slow-start time of 2.5 msec.
1.3.3
Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R1 and R2. The EVM is set for a start
voltage of 2.794 V and a stop voltage of 2.595 V using R1 = 14.3 kΩ and R2 = 11.5 kΩ. Use Equation 3
and Equation 4 to calculate required resistor values for different start and stop voltages.
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
è VENRISING ø
R1 =
æ
ö
V
Ip ç 1 - ENFALLING ÷ + Ih
V
ENRISING ø
è
(3)
R2 =
R1´ VENFALLING
VSTOP - VENFALLING + R1 Ip + Ih
(
)
(4)
Where:
• VENRISING = 1.25 V
• VENFALLING = 1.18 V
• Ih = 2.9 µA
• Ip = 0.7 µA
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Test Setup and Results
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Test Setup and Results
This section describes how to properly connect, set up, and use the TPS54519EVM-037 evaluation
module. The section also includes test results typical for the evaluation module and covers efficiency,
output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up.
2.1
Input/Output Connections
The TPS54519EVM-037 is provided with input/output connectors and test points as shown in Table 4. A
power supply capable of supplying 3 A must be connected to J1 through a pair of 20 AWG wires. The load
must be connected to J4 through a pair of 20 AWG wires. The maximum load current capability must be at
least 4 A to use the full capability of this EVM. Wire lengths must be minimized to reduce losses in the
wires. Test-point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient
ground reference. TP6 is used to monitor the output voltage with TP7 as the ground reference.
Table 4. EVM Connectors and Test Points
Reference Designator
4
Function
J1
VIN (see Table 1 for VIN range).
J2
2-pin header to allow connection of an external track in voltage to SS/TR. Use with optional resistor
divider of R5 and R6
J3
VOUT, 1.8 V at 5 A maximum
JP1
2-pin header for enable. Connect EN to ground to disable, open to enable.
JP2
2-pin header for to allow pullup of PWRGD to VIN
TP1
VIN test point at VIN connector
TP2
GND test point at VIN
TP3
Slow-start monitor test point
TP4
PH test point
TP5
PWRGD test point
TP6
GND test point
TP7
Test point between voltage divider network and output. Used for loop response measurements.
TP8
Output voltage test point at OUT connector
TP9
GND test point at OUT connector
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2.2
Efficiency
The efficiency of this EVM peaks at a load current of about 0.5 A – 1 A and then decreases as the load
current increases towards full load. Figure 1 shows the efficiency for the TPS54519EVM-037 at an
ambient temperature of 25°C.
100
90
80
Efficiency (%)
70
60
50
40
30
20
VIN = 3.3 V
VIN = 5 V
10
0
0
0.5
1
1.5
2
2.5
3
Output Current (A)
3.5
4
4.5
5
G001
Figure 1. TPS54519EVM-037 Efficiency
Figure 2 shows the efficiency for the TPS54519EVM-037 at lower output currents between 0.02 A and
0.20 A at an ambient temperature of 25°C.
100
90
80
Efficiency (%)
70
60
50
40
30
20
VIN = 3.3 V
VIN = 5 V
10
0
0.001
0.01
0.1
1
Output Current (A)
G002
Figure 2. TPS54519EVM-037 Low Current Efficiency
The efficiency may be lower at higher ambient temperatures, due to temperature variation in the
drain-to-source resistance of the internal MOSFET.
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Test Setup and Results
2.3
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Output Voltage Load Regulation
Figure 3 shows the load regulation for the TPS54519EVM-037.
1
VIN = 3.3 V
VIN = 5 V
0.8
Output Voltage Deviation (%)
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
0.5
1
1.5
2
2.5
3
Output Current (A)
3.5
4
4.5
5
G003
Figure 3. TPS54519EVM-037 Load Regulation
Measurements are given for an ambient temperature of 25°C.
2.4
Output Voltage Line Regulation
Figure 4 shows the line regulation for the TPS54519EVM-037.
0.4
Output Voltage Deviation (%)
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
IOUT = 2.5 A
−0.4
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
G004
Figure 4. TPS54519EVM-037 Line Regulation
6
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2.5
Load Transients
Figure 5 shows the TPS54519EVM-037 response to load transients. The current step is from 25% to 75%
of maximum rated load at 5 V input. Total peak-to-peak voltage variation is as shown, including ripple and
noise on the output.
VOUT = 50 mV / div (ac coupled)
IOUT = 2 A / div
Load step = 1.25 A - 3.75 A, slew rate = 0.5 A / µsec
Time = 200 µsec / div
Figure 5. TPS54519EVM-037 Transient Response
2.6
Loop Characteristics
50
180
Gain
Phase 150
40
120
30
90
20
60
10
30
0
0
Gain (dB)
60
−10
−30
−20
−60
−30
−90
−40
−120
−50
−150
−60
100
1000
10000
Frequency (Hz)
100000
Phase (°)
Figure 6 shows the TPS54519EVM-037 loop-response characteristics. Gain and phase plots are shown
for VIN voltage of 5 V. Load current for the measurement is 5 A.
−180
1000000
G005
Figure 6. TPS54519EVM-037 Loop Response
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Test Setup and Results
2.7
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Output Voltage Ripple
Figure 7 shows the TPS54519EVM-037 output voltage ripple. The output current is the rated full load of 5
A and VIN = 5 V. The ripple voltage is measured directly across the output capacitors.
VOUT = 20 mV / div (ac coupled)
PH = 2 V / div
Time = 500 nsec / div
Figure 7. TPS54519EVM-037 Output Ripple
2.8
Input Voltage Ripple
Figure 8 shows the TPS54519EVM-037 input voltage ripple. The output current is the rated full load of 5 A
and VIN = 5 V. The ripple voltage is measured directly across the input capacitors.
VIN = 100 mV / div (ac coupled)
PH = 2 V / div
Time = 500 nsec / div
Figure 8. TPS54519EVM-037 Input Ripple
8
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2.9
Powering Up
Figure 9 and Figure 10 show the start-up waveforms for the TPS54519EVM-037. In Figure 9, the output
voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2
resistor divider network. In Figure 10, the input voltage is initially applied and the output is inhibited by
using a jumper at JP1 to tie EN to GND. When the jumper is removed, EN is released. When the EN
voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps
up to the externally set value of 1.8 V. The input voltage for these plots is 5 V and the load is 1Ω.
VIN = 5 V / div
EN = 2 V / div
PWRGD = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 9. TPS54519EVM-037 Start-Up Relative to VIN
VIN = 5 V / div
EN = 2 V / div
PWRGD = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 10. TPS54519EVM-037 Start-Up Relative to Enable
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Test Setup and Results
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2.10 Powering Down
Figure 11 and Figure 12 show the start-up waveforms for the TPS54519EVM-037. In Figure 11, the output
voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R1
and R2 resistor divider network. In Figure 12, the output is inhibited by using a jumper at JP1 to tie EN to
GND. The input voltage for these plots is 5 V and the load is 1 Ω.
VIN = 5 V / div
EN = 2 V / div
PWRGD = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 11. TPS54519EVM-037 Shutdown Relative to VIN
VIN = 5 V / div
EN = 2 V / div
PWRGD = 5 V / div
VOUT = 1 V / div
Time = 100 µsec / div
Figure 12. TPS54519EVM-037 Shutdown Relative to EN
10
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Board Layout
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3
Board Layout
This section provides a description of the TPS54519EVM-037, board layout, and layer illustrations.
3.1
Layout
Figure 13 through Figure 17 shows the board layout for the TPS54519EVM-037. The top-side layer of the
EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz.
copper.
The top layer contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54519 and a large area filled with ground. The bottom and
internal layers contain ground planes only. The top-side ground areas are connected to the bottom and
internal ground planes with multiple vias placed around the board including four vias directly under the
TPS54519 device to provide a thermal path from the top-side ground area to the bottom-side and internal
ground planes.
The input decoupling capacitors (C2 and C3) and bootstrap capacitor (C6) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace near
the output connector J4. For the TPS54519, an additional input bulk capacitor may be required, depending
on the EVM connection to the input supply.
Figure 13. TPS54519EVM-037 Top-Side Layout
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Board Layout
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Figure 14. TPS54519EVM-037 Bottom-Side Layout
Figure 15. TPS54519EVM-037 Layout 2
12
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Schematic and Bill of Materials
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Figure 16. TPS54519EVM-037 Layout 3
Figure 17. TPS54519EVM-037 Top-Side Assembly
3.2
Estimated Circuit Area
The estimated printed-circuit board area for the components used in this design is 0.37 in2 (239 mm2).
This area does not include test point or connectors.
4
Schematic and Bill of Materials
This section presents the TPS54519EVM-037 schematic and bill of materials.
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13
14
JP1
1 NOT INSTALLED
GND
EN
1
2
1
10uF
C2
C3
R1
VSNS
TPS54519EVM-037, 5-A, SWIFT™ Regulator— Evaluation Module
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C6
1
1000pF
23.7k
R3
11.5k
R2
14.3k
C5
220pF
C4
0.1uF
R4
35.7k
9
8
7
6
15
2
1
C1
2
VIN
16
VIN= 3-6V
1
TP2
TP1
0.01uF
C7
TP3
SS/TR
RT/CLK
COMP
VSNS
EN
VIN
VIN
VIN
1
R5
R6
17
PWPD
BOOT
PH
PH
PH
1
AGND
GND
GND
PWRGD
U1
TPS54519
2
1
5
4
3
14
13
12
11
10
J2
1
PG
VIN
C9
2
47uF
L1
1.2 uH
R7 100k
TP5
0.1uF
C8
TP4
2
1
JP2
TP6
VIN
PG-PU
47uF
C10
TP7
10.0k
R10
20k
R9
51.1
R8
VOUT= 1.8 V, 5 A
220pF
C11
TP9
TP8
1
2
VSNS
J3
VOUT
GND
4.1
GND
VIN
J1
Schematic and Bill of Materials
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Schematic
Figure 18 is the schematic for the TPS54519EVM-037.
Figure 18. TPS54519EVM-037 Schematic
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Schematic and Bill of Materials
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4.2
Bill of Materials
Table 5 presents the bill of materials for the TPS54519EVM-037.
Table 5. TPS54519EVM-037 Bill of Materials
Count
RefDes
Value
Description
Size
Part Number
MFR
0
C1
Open
Capacitor
Multi sizes
Engineering Only
Std
1
C2
10μF
Capacitor, Ceramic, 16V, X5R, 20%
1206
Std
Std
2
C3, C8
0.1μF
Capacitor, Ceramic, 25V, X5R, 10%
0603
Std
Std
2
C4. C11
220pF
Capacitor, Ceramic, 50V, C0G, 5%
0603
Std
Std
0
C5
Open
Capacitor, Ceramic,
0603
Std
Std
1
C6
1000pF
Capacitor, Ceramic, 50V, X7R, 10%
0603
Std
Std
1
C7
0.01μF
Capacitor, Ceramic, 25V, X7R, 10%
0603
Std
Std
2
C9, C10
47 μF
Capacitor, Ceramic, 10V, X5R, 20%
1210
Std
Std
2
J1, J3
ED555/2DS
Terminal Block, 2-pin, 6-A, 3.5mm
0.27 x 0.25 inch
ED555/2DS
OST
1
J2
PEC02SAAN
Header, Male 2-pin, 100mil spacing
0.100 inch x 2
PEC02SAAN
Sullins
2
JP1, JP2
PEC02SAAN
Header, Male 2-pin, 100mil spacing
0.100 inch x 2
PEC02SAAN
Sullins
1
L1
1.2μH
Inductor, SMD Shielded Power, 11.8 A, 7.4 mΩ
5.3x5.5 mm
XAL5030-122ME
Coilcraft
1
R1
14.3k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R2
11.5k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R3
23.7k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R4
35.7k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
0
R5, R6
Open
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R7
100k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R8
51.1
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R9
20.0
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R10
10.0
Resistor, Chip, 1/16W, 1%
0603
Std
Std
7
TP1, TP3,
TP4, TP5,
TP6, TP7,
TP8
5000
Test Point, Red, Thru Hole Color Keyed
0.100 x 0.100 inch
5000
Keystone
2
TP2, TP9
5001
Test Point, Black, Thru Hole Color Keyed
0.100 x 0.100 inch
5001
Keystone
1
U1
TPS54519RTE
IC, DC-DC Converter, 2.95-6 V, 5A
QFN-16
TPS54519RTE
TI
2
–
Shunt, 100-mil, Black
0.100
929950-00
3M
1
–
Label
1.25 x 0.25 inch
THT-13-457-10
Brady
1
–
PCB, 2.5 x 2.5 x 0.062 inch
HPA375
Any
Notes 1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
5. Install label in silkscreened box after final wash. Text shall be 8 pt font. Text shall be per Table 6
Table 6. Label Marking
Text
TPS54519EVM-037
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Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety and environmental measures typically found in end products that incorporate such semiconductor
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
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EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of 3 V to 6 V and the output voltage range of 0.6 V to 2.5 V .
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
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During normal operation, some circuit components may have case temperatures greater than 85°C. The EVM is designed to
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include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
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