TI TMS29F002RB

 SMJS849B − MARCH 1997 − REVISED JUNE 1998
D Single Power Supply Supports 5-V "10%
D
D
D
D
D
D
D
D
D
D
D
A12
A15
A16
RESET
VCC
WE
A17
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
D
D
Read/Write Operation
Organization : . . . 262 144 by 8 Bits
Array-Blocking Architecture
− One 16K-Byte Boot Sector
− Two 8K-Byte Parameter Sectors
− One 32K-Byte Sector
− Three 64K-Byte Sectors
− Any Combination of Sectors Can Be
Erased. Support Full-Chip Erase
− Any Combination of Sectors Can Be
Marked as Read-Only
Boot-Code Sector Architecture
− T = Top Sector
− B = Bottom Sector
Sector Protection
− Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
Embedded Program/Erase Algorithms
− Automatically Pre-Programs and Erases
Any Sector
− Automatically Programs and Verifies the
Program Data at Specified Address
JEDEC Standards
− Compatible With JEDEC Byte Pinouts
− Compatible With JEDEC EEPROM
Command Set
Fully Automated On-Chip Erase and
Program Operations
100 000 Program/Erase Cycles
Low Power Dissipation
Low Current Consumption
− 25-mA Typical Active Read
− 30-mA Typical Program/Erase Current
− Less Than 100-µA Standby Current
All Inputs/Outputs TTL-Compatible
Erase Suspend/Resume
− Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
FM PACKAGE
32-PIN PLCC
(TOP VIEW)
PIN NOMENCLATURE
A[0:17]
DQ[0:7]
CE
OE
RESET
VCC
VSS
WE
Address Inputs
Data In / Data out
Chip Enable
Output Enable
Reset / Deep Power Down
Power Supply
Ground
Write Enable
D 32-Pin Plastic Leaded Chip Carrier (PLCC)
(FM Suffix)
D Detection Of Program/Erase Operation
D
− Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
High-Speed Data Access at 5-V VCC"10%
− 90 ns Commercial . . . 0°C to 70°C
− 100 ns Extended . . . −40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
description
The TMS29F002RT/B is a 262144 by 8-bit (2097 152-bit), 5-V single-supply, programmable read-only memory
device that can be electrically erased and reprogrammed. This device is organized as 262144 by 8 bits, divided
into seven sectors:
−
One 16K-byte boot sector
−
Two 8K-byte sectors
−
One 32K-byte sector
−
Three 64K-byte sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported.
Sector data protection is afforded by methods that can disable any combination of sectors from write or read
operations using standard programming equipment. An on-chip state machine provides an on-board algorithm
that automatically pre-programs and erases any sector before it automatically programs and verifies program
data at any specified address. The command set is compatible with the JEDEC 2M-bit electrically erasable,
programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to
unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible.
Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector
that is not being erased.
Device operations are selected by writing JEDEC-standard commands into the command register using
standard microprocessor write timings. The command register acts as an input to an internal-state machine
which interprets the commands, controls the erase and programming operations, outputs the status of the
device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power
up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read
operation.
The device has low power dissipation with a 25-mA typical active read for the byte mode, 30-mA typical
program/erase current mode, and less than 100-mA standby current with a 15-mA deep-power-down mode.
These devices are offered with 90-, 100-, and 120-ns access times. Table 1 and Table 2 show the
sector-address ranges. The TMS29F002RT/B is offered in a 32-pin plastic leaded chip carrier (PLCC) (FM
suffix).
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
device symbol nomenclature
TMS29F002R
T
−90
C
FM
L
Temperature Range
L = Commercial (0°C to 70°C)
E = Extended (−40°C to 85°C)
Package Type
FM = 32-Pin Plastic Leaded Chip Carrier
Program/Erase Endurance
C = 100 000 Cycle
B = 10 000 Cycles
Speed Option
90 = 90 ns
10 = 100 ns
12 = 120 ns
Boot Code Selection Architecture
T = Top Sector
B = Bottom Sector
Device Number / Description
2M Bits
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
RESET
CE
OE
WE
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
0
A
0
262 143
17
1
22
24
31
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Flash
MEMORY
262 144 × 8
A, Z4
13
14
15
17
18
19
20
21
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
block diagram
DQ0 −DQ7
Erase Voltage
Generator
Input/Output Buffers
WE
State Control
RESET
Command Registers
PGM Voltage
Generator
STB
Data Latch
CE
Chip-Enable
Output-Enable
Logic
OE
VSS
VCC
VCC Detector
Timer
STB
A0 −A17
L
a
t
c
h
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Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A
d
d
r
e
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
operation
See Table 1 and Table 2 for the sector-address ranges of the TMS29F002RT/B.
Table 1. Top-Boot Sector-Address Ranges†‡
A17
A16
A15
A14
A13
SECTOR SIZE
(x8) ADDRESS RANGE
SA6
1
1
1
1
X
16K-Byte
3C000H−3FFFFH
SA5
1
1
1
0
1
8K-Byte
3A000H−3BFFFH
SA4
1
1
1
0
0
8K-Byte
38000H−39FFFH
SA3
1
1
0
X
X
32K-Byte
30000H−37FFFH
SA2
1
0
X
X
X
64K-Byte
20000H−2FFFFH
SA1
0
1
X
X
X
64K-Byte
10000H−1FFFFH
SA0
0
0
X
X
X
64K-Byte
00000H−0FFFFH
† The address range is A0−A17
‡ X can be 0 or 1.
Table 2. Bottom-Boot Sector-Address Ranges†‡
A17
A16
A15
A14
A13
SECTOR SIZE
(x8) ADDRESS RANGE
SA6
1
1
X
X
X
64K-Byte
30000H−3FFFFH
SA5
1
0
X
X
X
64K-Byte
20000H−2FFFFH
SA4
0
1
X
X
X
64K-Byte
10000H−1FFFFH
SA3
0
0
1
X
X
32K-Byte
08000H−0FFFFH
SA2
0
0
0
1
1
8K-Byte
06000H−07FFFH
SA1
0
0
0
1
0
8K-Byte
04000H−05FFFH
0
X
16K-Byte
00000H−03FFFH
SA0
0
0
0
† The address range is A0−A17
‡ X can be 0 or 1.
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
operation (continued)
See Table 3 for the operation modes of the TMS29F002RT/B.
Table 3. Operation Modes
FUNCTIONS†
MODE
DQ0−DQ7
CE
OE
WE
A0
A1
A6
A9
RESET
VIL
VIL
VIH
VIL
VIL
VIL
VID
VIH
Manufacturer-Equivalent Code 01h
(TMS29F002RT/B − Byte)
VIL
VIL
VIH
VIH
VIL
VIL
VID
VIH
Device-Equivalent Code B0h
(TMS29F002RT − Byte)
VIL
VIL
VIH
VIH
VIL
VIL
VID
VIH
Device-Equivalent Code 34h
(TMS29F002RB − Byte)
VIL
VIH
VIH
VIH
A0
A1
A6
A9
X
X
X
X
VIH
VIH
Data out
Output disable
VIL
VIL
Standby and write inhibit
Write‡
VIH
VIL
X
X
X
X
X
X
Hi-Z
VIL
X
A0
A1
A6
A9
X
VIH
X
VIH
VIH
X
X
X
X
X
VIL
X
VIL
X
VIH
X
VIL
X
VIH
X
VIL
X
VID
X
VID
VIH
VIL
Hi-Z
Algorithm-selection mode
5-V power supply
Read
Temporary sector unprotect
Verify sector protect
Hardware reset
Hi-Z
Data in
Data out
Legend:
VIL = Logic 0
VIH = Logic 1
VID = 12.0 V ± 0.5 V
† X can be VIL or VIH.
‡ See Table 5 for valid address and data during write.
read mode
A logic-low signal applied to the CE and OE pins allows the output of the TMS29F002RT/B to be read. When
two or more ’29F002RT/B devices are connected in parallel, the output of any one device can be read without
interference. The CE pin is for power control and must be used for device selection. The OE pin is for output
control, and is used to gate the data output onto the bus from the selected device.
The address-access time (tAVQV) is the delay from stable address to valid output data. The chip-enable (CE)
access time (tELQV) is the delay from CE low and stable addresses to valid output data. The output-enable
access time (tGLQV) is the delay from OE low to valid output data when CE equals logic low and addresses are
stable for at least the duration of tAVQV−tGLQV.
standby mode
ICC supply current is reduced by applying a logic-high level on CE and RESET to enter the standby mode. In
the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on
CE and RESET reduces the current to 100 µA. Applying a TTL logic-high level on CE and RESET reduces the
current to 1 mA. If the ’29F002RT/B is deselected during erasure or programming, the device continues to draw
active current until the operation is complete.
output disable
When OE equals VIH or CE equals VIH, output from the device is disabled and the output pins (DQ0−DQ7) are
placed in the high-impedance state.
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
automatic-sleep mode
The ’29F002RT/B has a built-in feature called automatic-sleep mode to minimize device energy consumption.
The automatic-sleep mode, which is independent of CE, WE, and OE, is enabled when addresses remain stable
for 300 ns. Typical sleep-mode current is 100 µA. Sleep mode does not affect output data, which remains latched
and available to the system.
algorithm selection
The algorithm-selection mode provides access to a binary code that matches the device with its proper
programming and erase command operations. This mode is activated when VID (11.5 V to 12.5 V) is placed on
address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling address
pin A0 from VIL to VIH. Address pins other than A0, A1, and A6 can be at logic low or at logic high.
The algorithm-selection mode can also be read by using the command register, which is useful when VID is not
available to be placed on address pin A9. Table 4 shows the binary algorithm-selection codes.
Table 4. Algorithm-Selection Codes (5-V Single Power Supply)†
CODE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacturer-equivalent code
01H
0
0
0
0
0
0
0
1
TMS29F002RT
B0H
1
0
1
1
0
0
0
0
TMS29F002RB
34H
0
0
1
1
0
1
0
0
01H
0
0
0
0
0
0
0
1
Sector protection
† A1 = VIL, A6 = VIL, CE =VIL, OE = VIL
erasure and programming
Erasure and programming of the ’29F002RT/B are accomplished by writing a sequence of commands using
standard microprocessor write timing. The commands are written to a command register and input to the
command-state machine (CSM). The CSM interprets the command entered and initiates program, erase,
suspend, and resume operations as instructed. The CSM acts as the interface between the write-state machine
(WSM) and external chip operations. The WSM controls all voltage generation, pulse generation,
preconditioning, and verification of memory contents. Program and block-/chip-erase functions are fully
automatic. Once the end of a program or erase operation has been reached, the device resets internally to the
read mode. If VCC drops below the low-voltage-detect level (VLKO), any programming or erase operation is
aborted and subsequent writes are ignored until the VCC level is greater than VLKO. The control pins must be
logically correct to prevent unintentional command writes or programming or erasing.
command definitions
Device operating modes are selected by writing specific address and data sequences into the command
register. Table 5 defines the valid command sequences. Writing incorrect address and data values or writing
them in the incorrect sequence causes the device to reset to the read mode. The command register does not
occupy an addressable memory location. The register is used to store the command sequence, along with the
address and data needed by the memory array. Commands are written by setting CE = VIL, OE = VIH, and
bringing WE from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched
on the rising edge of WE. Holding WE = VIL and toggling CE is an alternative method. See the switching
characteristics of the write/erase/program-operations section for specific timing information.
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
command definitions (continued)
Table 5. Command Definitions
COMMAND
Read/reset
BUS
CYCLES
1ST CYCLE
ADDR
DATA
1
XXXH
F0H
3
555H
AAH
2ND CYCLE
ADDR
DATA
3RD CYCLE
ADDR
DATA
2AAH
555H
55H
F0H
4TH CYCLE
ADDR
DATA
RA
5TH CYCLE
ADDR
DATA
6TH CYCLE
ADDR
DATA
RD
B0H
T
Algorithm
selection
3
555H
AAH
2AAH
55H
555H
90H
Program
4
555H
AAH
2AAH
55H
555H
A0H
PA
PD
Chip erase
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
10H
Sector erase
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
SA
30H
Sector-erase
suspend
1
XXXH
B0H
Erase suspend valid during sector-erase operation
Sector-erase
resume
1
XXXH
30H
Erase resume valid only after erase-suspend operation
01H
34H
B
LEGEND:
RA = Address of the location to be read
PA = Address of the location to be programmed
SA = Address of the sector to be erased
Addresses A13−A17 select one to seven sectors.
RD = Data to be read at selected address location
PD = Data to be programmed at selected address location
read/reset command
The read or reset mode is activated by writing either of the two read/reset command sequences into the
command register. The device remains in this mode until another valid command sequence is input in the
command register. Memory data is available in the read mode and can be read with standard microprocessor
read-cycle timing.
On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and
memory data is available.
algorithm-selection command
The algorithm-selection command allows access to a binary code that matches the device with the proper
programming and erase command operations. After writing the three-bus-cycle command sequence, the first
byte of the algorithm-selection code can be read from address XX00h. The second byte of the code can be read
from address XX01h (see Table 5). This mode remains in effect until another valid command sequence is written
to the device.
program command
Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the
program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the
device. The addresses are latched on the falling edge of WE and the data is latched on the rising edge of WE
in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming
function automatically provides needed voltage and timing to program and verify the cell margin. Any further
commands written to the device during the program operation are ignored.
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
program command (continued)
Programming can be performed at any address location in any sequence. When erased, all bits are in a
logic-high state. Logic lows are programmed into the device and only an erase operation can change bits from
logic lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes
the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to
a logic-high state. The automatic-programming operation is complete when the data on DQ7 is equivalent to
the data written to this bit, at which time the device returns to the read mode and addresses are no longer
latched. Figure 1 shows a flow chart of the typical device-programming operation.
chip-erase command
Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup
state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This
command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge
of WE starts the chip-erase operation. Any further commands written to the device during the chip-erase
operation are ignored.
The embedded chip-erase function automatically provides the voltage and timing needed to program and to
verify all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically
without programming the memory cells prior to erase.
Figure 2 shows a flow chart of the typical chip-erase operation.
sector-erase command
Sector-erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the
erase-setup state. The next two bus cycles unlock the erase mode and the sixth bus cycle loads the sector-erase
command and the sector-address location to be erased. Any address location within the desired sector can be
used. The addresses are latched on the falling edge of WE and the sector-erase command (30h) is latched on
the rising edge of WE in the sixth bus cycle. After a delay of 50 µs from the rising edge of WE, the sector-erase
operation begins on the selected sector(s).
Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For
each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next
sector-address location and the sector-erase command. The time between the end of the previous bus cycle
and the start of the next bus cycle must be less than 50 µs; otherwise, the new sector location is not loaded.
A time delay of 50 µs from the rising edge of the last WE starts the sector-erase operation. If there is a falling
edge of WE within the 50-µs time delay, the timer is reset.
One to seven sector-address locations can be loaded in any sequence. The state of the delay timer can be
monitored using the sector-erase delay indicator (DQ3). If DQ3 is at logic low, the time delay has not expired.
See the operation status section for a description.
Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the
sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s)
selected for erase are no longer valid. To complete the sector-erase operation, reissue the sector-erase
command sequence.
The embedded sector-erase function automatically provides needed voltage and timing to program and to verify
all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically.
Programming the memory cells prior to erase is not required.
See the operation status section for a full description. Figure 3 shows a flow chart of the typical sector-erase
operation.
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erase-suspend command
The erase-suspend command (B0h) allows interruption of a sector-erase operation to read data from unaltered
sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be VIL or VIH and the
erase-suspend command (B0h) is latched on the rising edge of WE. Once the sector-erase operation is in
progress, the erase-suspend command requests the internal write-state machine to halt operation at
predetermined breakpoints. The erase-suspend command is valid only during the sector-erase operation and
is invalid during programming and chip-erase operations. The sector-erase delay timer expires immediately if
the erase-suspend command is issued while the delay is active.
After the erase-suspend command is issued, the device takes between 0.1 µs and 15 µs to suspend the
operation. The toggle bit must be monitored to determine when the suspend has been executed. When the
toggle bit stops toggling, data can be read from sectors that are not selected for erase. Reading from a sector
selected for erase can result in invalid data. See the operation status section for a full description.
Once the sector-erase operation is suspended, reads or programs to a sector that is not being erased can be
performed. This command is applicable only during sector-erase operations. Any other command written during
the erase-suspend mode to the suspended sector is ignored.
erase-resume command
The erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was
halted. Erase resume is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-resume
command (30h) is latched on the rising edge of WE. When an erase-suspend/erase-resume command
combination is written, the internal-pulse counter (exceed timing limit) is reset. The erase-resume command
is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to
the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has
resumed the sector-erase operation, another erase-suspend command can be issued to the device.
operation status
The status of the device during an automatic-programming algorithm, chip-erase command, or sector-erase
command can be determined in two ways:
D DQ6: Toggle bit
D DQ7: Data polling
status-bit definitions
During operation of the automatic embedded program and erase functions, the status of the device can be
determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle bit (DQ6)
require multiple successive reads to observe a change in the state of the designated output. Table 6 defines
the values of the status flags.
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
status-bit definitions (continued)
Table 6. Operation Status Flags†
DEVICE OPERATION‡
Programming
Program/erase in auto-erase mode
In progress
Exceeded time limits
DQ6
DQ5
DQ3
DQ2
DQ7
T
0
0
0
T
0
1
No Tog
§
Erase-sector address
1
1
0
0
T
Non-erase sector address
D
D
D
D
Program in erase-suspend mode
DQ7¶
T
0
0
D
1§
Programming
DQ7
T
1
0
0
T
1
1
No Tog
#
DQ7
T
1
0
No Tog
Programming complete
D
D
D
D
D
Sector-/chip-erase complete
1
1
1
1
1
Erase-suspend mode
Program/erase in auto-erase mode
Program in erase-suspend mode
Successful operation
complete
DQ7
† T= toggle, D= data, No Tog= no toggle
‡ DQ4, DQ1, DQ0 are reserved for future use.
§ DQ2 can be toggled when the sector address applied is an erasing sector. DQ2 cannot be toggled when the sector address applied is a
non-erasing sector. DQ2 is used to determine which sectors are erasing and which are not.
¶ Status flags apply when outputs are read from the address of a non-erase-suspend operation.
# If DQ5 is high (exceeded timing limits), successive reads from a problem sector causes DQ2 to toggle.
data-polling (DQ7)
The data-polling-status function outputs the complement of the data latched into the DQ7 data register while
the write-state machine is engaged in a program or erase operation. Data bit DQ7 changes from complement
to true to indicate the end of an operation. Data-polling is available only during programming, chip-erase,
sector-erase, and sector-erase-timing delay. Data-polling is valid after the rising edge of WE in the last bus cycle
of the command sequence loaded into the command register. Figure 4 shows a flow chart of data-polling.
During a program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the
selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the
program-data register. During the erase operations, reading DQ7 outputs a logic low. Upon completion, reading
DQ7 outputs a logic high. Also, data-polling must be performed at a sector address that is within a sector that
is being erased. Otherwise, the status is invalid. When using data-polling, the address should remain stable
throughout the operation.
During a data-polling read, while OE is logic low, data bit DQ7 can change asynchronously. Depending on the
read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. A subsequent read
of the device is valid. See Figure 17 for the data-polling timing diagram.
toggle bit (DQ6)
The toggle-bit status function outputs data on DQ6, which toggles between logic high and logic low while the
write-state machine is engaged in a program or erase operation. When DQ6 stops toggling at a logic high after
two consecutive reads to the same address, the operation is complete. The toggle bit is available only during
programming, chip erase, sector erase, and sector-erase-timing delay. Toggle bit data is valid after the rising
edge of WE in the last bus cycle of the command sequence loaded into the command register. Figure 5 shows
a flow chart of the toggle-bit status-read algorithm. Depending on the read timing, DQ6 can stop toggling while
other DQ pins are still invalid and a subsequent read of the device is valid. See Figure 18 for the toggle-bit timing
diagram.
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMJS849B − MARCH 1997 − REVISED JUNE 1998
toggle bit (DQ6) (continued)
In instances where program operation is issued to a protected sector, toggle bit (DQ6) toggles for approximately
2 µs, after which it reverts back to read mode. On the other hand, if an erase operation is attempted on protected
sectors, DQ6 toggles for approximately 100 µs, then returns to read mode. Both instances do not alter the
contents of the protected sectors.
exceed time limit (DQ5)
The program and erase operations use an internal-pulse counter to limit the number of pulses applied. If the
pulse-count limit is exceeded, DQ5 is set to a logic-high data state. This indicates that the program or erase
operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop
toggling when read. To continue operation, the device must be reset.
The exceed-time-limit condition occurs when attempting to program a logic-high state into a bit that has been
programmed previously to a logic low. Only an erase operation can change bits from logic low to logic high. After
reset, the device is functional and can be erased and reprogrammed.
sector-load-timer (DQ3)
The sector-load-timer status bit, DQ3, is used to determine whether the time to load additional sector addresses
has expired. This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic
high, it indicates that the delay has expired and attempts to issue additional sector-erase commands are
ignored. See the sector-erase command section for a description.
The data-polling and toggle bit are valid during the 50-µs time delay and can be used to determine if a valid
sector-erase command has been issued. To ensure additional sector-erase commands have been accepted,
the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic
low on both reads, the additional sector-erase command was accepted.
toggle bit 2 (DQ2)
The state of DQ2 determines whether the device is in algorithmic-erase mode or erase-suspend mode. DQ2
toggles if successive reads are issued to the erasing or erase-suspended sector, assuming in case of the latter
that the device is in erase-suspend-read mode. It also toggles when DQ5 becomes a logic high due to the
timer-exceed limit, and reads are issued to the failed sector. DQ2 does not toggle in any other sector due to DQ5
failure. When the device is in erase-suspend-program mode, successive reads from the non-erase-suspended
sector causes a logic high on DQ2.
hardware-reset bit (RESET)
When the RESET pin is driven to a logic low, it forces the device out of the currently active mode and into a reset
state. It also avoids bus contention by placing the outputs into the high-impedance state for the duration of the
RESET pulse.
During any operation, if RESET is asserted to logic low, the on-going operation is terminated and it can take
from 1 µs − to 20 µs to sense reset completion; or the user can allow a maximum reset completion time of
20 µs.
The RESET pin also can be used to drive the device into deep power-down (standby) mode by applying
VSS ± 0.3 V to it. ICC4 reads <1 µA typical, and 15 µA maximum for CMOS inputs. Standby mode can be entered
anytime, regardless of the condition on CE.
Asserting RESET during program or erase can leave erroneous data in the address locations. These locations
need to be updated after the device resumes normal operations.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
13
SMJS849B − MARCH 1997 − REVISED JUNE 1998
temporary hardware-sector unprotect feature
This feature temporarily enables both programming and erase operations on any combination of one to seven
sectors that were previously protected. This feature is enabled using high voltage VID (11.5 V to 12.5 V) on the
RESET pin, using standard command sequences.
Normally, the device is delivered with all sectors unprotected.
sector-protect programming
The sector-protect programming mode is activated when A6, A0, and CE are at VIL, and address pin A9 and
control pin OE are forced to VID. Address pin A1 is set to VIH.The sector-select address pins A13 − A17 are used
to select the sector to be protected. Address pins A0−A12 and the I/O pins must be stable and can be either
VIL or VIH. Once the addresses are stable, WE is pulsed low for 100 µs, causing programming to begin on the
falling edge of WE and to terminate on the rising edge of WE. Figure 6 is a flow chart of the sector-protect
algorithm and Figure 19 shows a timing diagram of the sector-protect operation.
Commands to program or erase a protected sector do not change the data contained in the sector. Attempts
to program and erase a protected sector cause the data-polling bit (DQ7) and toggle bit (DQ6) to operate from
2 µs to 100 µs and then return to valid data.
sector-protect verify
Verification of the sector-protection programming is activated when WE = VIH, OE = VIL, CE = VIL, and address
pin A9 = VID. Address pins A0 and A6 are set to VIL, and A1 is set to VIH. Sector-address pins A13−A17 select
the sector that is to be verified. The other addresses can be VIH or VIL. If the sector that was selected is protected,
the DQs output 01h. If the sector is not protected, the DQs output 00h.
Sector-protect verify can also be read using the algorithm-selection command. After issuing the three-bus-cycle
command sequence, the sector-protection status can be read on DQ0. The sector address pins A13 −A17
select the sector to be verified when address pins A0 = VIL, A1 = VIH, and A6 = VIL are set. The remaining
addresses are set to VIL. If the sector selected is protected, DQ0 outputs a logic-high state. If the sector selected
is not protected, DQ0 outputs a logic-low state. This mode remains in effect until another valid command
sequence is written to the device. Figure 6 is a flow chart of the sector-protect algorithm and Figure 19 shows
a timing diagram of the sector-protect operation.
sector unprotect
Prior to sector unprotect, all sectors must be protected using the sector-protect programming mode. The sector
unprotect is activated when address pin A9 and control pin OE are forced to VID. Address pins A1 and A6 are
set to VIH while CE and A0 are set to VIL. Sector-select address pins A13−A17 can be VIL or VIH. All sectors
are unprotected in parallel and once the inputs are stable, WE is pulsed low for 10 ms, causing the unprotect
operation to begin on the falling edge of WE and to terminate on the rising edge of WE. Figure 7 is a flow chart
of the sector-unprotect algorithm and Figure 20 shows a timing diagram of the sector-unprotect operation.
sector-unprotect verify
Verification of the sector unprotect is accomplished when WE = VIH, OE = VIL, CE =VIL, and A9 = VID, and then
select the sector to be verified. Address pins A1 and A6 are set to VIH, and A0 is set to VIL. The other addresses
can be VIH or VIL. If the sector selected is protected, the DQs output 01h. If the sector is not protected, the DQs
output 00h. Sector unprotect can also be read using the algorithm-selection command.
low VCC write lockout
During power-up and power-down operations, write cycles are locked out for VCC less than VLKO. If VCC < VLKO,
the command input is disabled and the device is reset to the read mode. On power up, if CE = VIL, WE = VIL,
and OE = VIH, the device does not accept commands on the rising edge of WE. The device automatically powers
up in the read mode.
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMJS849B − MARCH 1997 − REVISED JUNE 1998
glitching
Pulses of less than 5 ns (typical) on OE, WE, or CE do not issue a write cycle.
power supply considerations
Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise.
Printed circuit traces to VCC should be appropriate to handle the current demand and minimize inductance.
flow charts
Start
Write Bus Cycle
555H / AAH
Write Bus Cycle
2AAH / 55H
Write Bus Cycle
555H / A0H
Write Bus Cycle
Program Address / Program Data
Poll Device Status
Operation
Complete
?
No
Yes
No
Next Address
Last
Address
?
Yes
End
Figure 1. Program Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
15
SMJS849B − MARCH 1997 − REVISED JUNE 1998
flow charts (continued)
Start
Write Bus Cycle
555H / AAH
Write Bus Cycle
2AAH / 55H
Write Bus Cycle
555H /80H
Write Bus Cycle
555H / AAH
Write Bus Cycle
2AAH / 55H
Write Bus Cycle
555H / 10H
Poll Device Status
Operation
Complete
?
No
Yes
End
Figure 2. Chip-Erase Algorithm
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMJS849B − MARCH 1997 − REVISED JUNE 1998
flow charts (continued)
Start
Write Bus Cycle
555H /AAH
Write Bus Cycle
2AAH / 55H
Write Bus Cycle
555H / 80H
Write Bus Cycle
555H/AAH
Write Bus Cycle
2AAH / 55H
Write Bus Cycle
Sector Address / 30H
No
DQ3 = 0
?
Yes
Load
Additional
Sectors
?
Yes
No
Poll Device Status
No
Operation
Complete
?
Yes
End
Figure 3. Sector-Erase Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
17
SMJS849B − MARCH 1997 − REVISED JUNE 1998
flow charts (continued)
Start
Read DQ0 −DQ7
Addr = VA
DQ7 =
Data
?
Yes
No
No
DQ5 = 1
?
Yes
Read DQ0 −DQ7
Addr = VA
DQ7 =
Data
?
Yes
No
Fail
Pass
NOTES: A. Polling status bits DQ7 and DQ5 may change asynchronously.
Read DQ7 after DQ5 changes states.
B. VA = Program address for byte-programming
= Selected sector address for sector erase
= Any valid address for chip erase
Figure 4. Data-Polling Algorithm
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMJS849B − MARCH 1997 − REVISED JUNE 1998
flow charts (continued)
Start
Read DQ0 −DQ7
Addr = VA
Read DQ0 −DQ7
Addr = VA
DQ6 =
Toggle
?
No
Yes
No
DQ5 = 1
?
Yes
Read DQ0 −DQ7
DQ6 =
Toggle
?
No
Yes
Fail
Pass
NOTES: A. Polling status bits DQ6 and DQ5 can change asynchronously.
Read DQ6 after DQ5 changes states.
B. After an erase operation is complete, DQ6 stops toggling at a
logic high state.
Figure 5. Toggle-Bit Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
19
SMJS849B − MARCH 1997 − REVISED JUNE 1998
flow charts (continued)
Start
Select Sector Address
A13 −A17
X=1
OE and A9 = VID,
CE, A0, and A6 = VIL,
A1 = VIH
Apply One 100-µs
Pulse
X = X+1
CE, OE, A0, A6 = VIL,
A1 = VIH,
A9 = VID
Read Data
No
X = 25
?
No
Data = 01H
?
Yes
Yes
Sector Protect
Failed
Protect
Additional
Sectors
?
No
A9 = VIH or VIL
Write Reset Command
End
Figure 6. Sector-Protect Algorithm
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
Yes
SMJS849B − MARCH 1997 − REVISED JUNE 1998
flow charts (continued)
Start
Protect All Sectors
X=1
OE, A9 = VID,
CE and A0 = VIL,
A6 and A1 = VIH
Apply One
10-ms Pulse
CE, OE, A0 = VIL,
A6 and A1 = VIH,
A9 = VID
Select Sector Address
X = X+1
Read Data
No
No
X = 1000
?
Next Sector
Address
Data = 00H
?
Yes
Yes
Sector Unprotect
Failed
Last
Sector
?
No
Yes
A9 = VIH or VIL
Write Reset Command
End
Figure 7. Sector-Unprotect Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
21
SMJS849B − MARCH 1997 − REVISED JUNE 1998
flow charts (continued)
Start
RESET = VID (see
Note A)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotect Completed
(see Note B)
NOTES: A. All protected sectors unprotected
B. All previously protected sectors are protected once again
Figure 8. Temporary Sector-Unprotect Algorithm
22
POST OFFICE BOX 1443
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
Input voltage range: All inputs except A9, CE, OE (see Note 2) . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
A9, CE, OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
Ambient temperature range during read / erase / program, TA
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. The voltage on any input pin can undershoot to −2 V for periods less than 20 ns (see Figure 10).
3. The voltage on any output pin can overshoot to VCC + 2 V for periods less than 20 ns (see Figure 11).
recommended operating conditions
VCC
Supply voltage
VIH
High-level dc input voltage
VIL
Low-level dc input voltage
VID
VLKO
Algorithm-selection and sector-protect input voltage
TA
Ambient temperature
MIN
MAX
4.5
5.5
V
0.7 * VCC
VCC + 0.5
VCC + 0.5
V
TTL
−0.5
0.8
CMOS
−0.5
0.2
11.5
12.5
V
3.2
4.2
V
−40
85
0
70
TTL
CMOS
Low VCC lock-out voltage (see Note 4)
Extended
Commercial
2
UNIT
V
°C
NOTE 4: TA = 25°C
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
23
SMJS849B − MARCH 1997 − REVISED JUNE 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
PARAMETER
TEST CONDITIONS
TTL-input level
VOH
High-level output voltage
CMOS-input level
CMOS-input level
VOL
II
Low-level output voltage
IO
IID
Output current (leakage)
Input current (leakage)
MIN
VCC = VCC MIN,
VCC = VCC MIN,
IOH = −2.5 mA
IOH = − 100 µA
VCC = VCC MIN,
VCC = VCC MIN,
IOH = − 2.5 mA
IOL = 5.8 mA
MAX
2.4 V
VCC − 0.4
0.85 * VCC
VCC = VCC MAX, VIN = VSS to VCC
VO =VSS to VCC, CE = VIH
A9 or CE or OE = VID MAX
High-voltage current (standby)
TTL-input level
UNIT
CE = VIH, VCC = VCC MAX
CE = VCC ± 0.2,
VCC = VCC MAX
V
0.45
V
±1
µA
±1
µA
35
µA
1
mA
ICC1
VCC supply current (standby)
100
µA
ICC2
VCC supply current (see Notes 5 and 6)
CE = VIL, OE = VIH
40
mA
ICC3
VCC supply current (see Note 7)
CE = VIL, OE = VIH
60
mA
VCC supply current (standby during reset)
VCC = VCC MAX,
RESET = VSS ± 0.3 V
15
µA
100
µA
MAX
UNIT
ICC4
CMOS-input level
ICC5
Automatic sleep mode (see Notes 6 and 8)
VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V
NOTES: 5. ICC current in the read mode, switching at 6 MHz.
6. IOUT = 0 mA
7. ICC current while erase or program operation is in progress.
8. Automatic sleep mode is entered when addresses remain stable for 300 ns.
capacitance over recommended ranges of supply voltage and ambient temperature
PARAMETER
TEST CONDITIONS
MIN
Ci1
Input capacitance (All inputs except A9, CE, OE)
7.5
pF
Input capacitance (A9, CE, OE)
VI = 0 V,
VI = 0 V,
f = 1 MHz
Ci2
f = 1 MHz
9
pF
Co
Output capacitance
VO = 0 V,
f = 1 MHz
12
pF
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMJS849B − MARCH 1997 − REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
0.5 mA
IOL
Output
Under
Test
1.5 V
CL = 30 pF
(see Note A and Note B)
− 0.5 mA
2.4 V
IOH
2V
0.8 V
0.45 V
NOTES: A. CL includes probe and fixture capacitance.
B. The ac testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made at 2 V for logic high
and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-µF ceramic capacitor connected between VCC
and VSS as closely as possible to the device pins.
Figure 9. AC Test Output Load Circuit
20 ns
20 ns
+0.8 V
−0.5 V
−2.0 V
20 ns
Figure 10. Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns
20 ns
Figure 11. Maximum Positive Overshoot Waveform
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
25
SMJS849B − MARCH 1997 − REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
switching characteristics over recommended ranges of supply voltage and ambient temperature,
read-only operation (see Figure 12, Figure 17, Figure 18, Figure 19, and Figure 20)
ALTERNATE
SYMBOL
PARAMETER
tc(R)
ta(A)
Cycle time, read
ta(E)
ta(G)
Access time, CE
tdis(E)
tdis(G)
Disable time, CE to high impedance
ten(E)
ten(G)
Enable time, CE to low impedance
th(D)
Hold time, output from address CE or OE change
26
tAVAV
tAVQV
tELQV
Access time, address
Access time, OE
Disable time, OE to high impedance
Enable time, OE to low impedance
POST OFFICE BOX 1443
’29F002R-90
MIN
MAX
90
tGLQV
tEHQZ
tGHQZ
tELQX
tGLQX
tAXQX
’29F002R-100
MIN
MAX
100
’29F002R-120
MIN
MAX
120
UNIT
ns
90
100
120
ns
90
100
120
ns
35
45
50
ns
20
25
30
ns
30
ns
20
25
0
0
0
ns
0
0
0
ns
0
0
0
ns
• HOUSTON, TEXAS 77251−1443
SMJS849B − MARCH 1997 − REVISED JUNE 1998
switching characteristics over recommended ranges of supply voltage and ambient temperature,
controlled by WE (see Figure 13, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20,
and Figure 21)
PARAMETER
ALTERNATE
SYMBOL
’29F002R-90
MIN
TYP
’29F002R-100
MAX
MIN
TYP
’29F002R-120
MAX
MIN
TYP
MAX
UNIT
tc(W)
Cycle time, write
tAVAV
90
100
120
ns
tsu(A)
Setup time, address
tAVWL
0
0
0
ns
th(A)
Hold time, address
tWLAX
45
50
50
ns
tsu(D)
Setup time, data
tDVWH
45
50
50
ns
th(D)
Hold time, data valid after
WE high
tWHDX
0
0
0
ns
tsu(E)
Setup time, CE
tELWL
0
0
0
ns
th(E)
Hold time, WE
tWHEH
0
0
0
ns
th(E)
Hold time, CE
tEHWH
0
0
0
ns
tw(WL)
Pulse duration, WE low
tWLWH1
45
45
50
ns
tw(WH)
Pulse duration, WE high
tWHWL
20
20
20
ns
trec(R)
Recovery time, read before
write
tGHWL
0
0
0
ns
Hold time, OE read
tWHGL1
0
0
0
ns
Hold time, OE toggle, data
tWHGL2
10
10
10
ns
tVCEL
50
50
50
µs
tHVT
4
4
4
µs
4
4
4
µs
Setup time, VCC
Transition time, VID
(see Notes 9 and 10)
tRSP
Reset setup time for
temporary sector unprotect
Pulse duration, WE low
(see Note 9)
tWLWH2
100
100
100
µs
Pulse duration, WE low
(see Note 10)
tWLWH3
10
10
10
ms
Setup time, CE VID to WE
(see Note 10)
tEHVWL
4
4
4
µs
Setup time, OE VID to WE
(see Notes 9 and 10)
tGHVWL
4
4
4
µs
tc(W)PR
Cycle time, programming
operation
tWHWH1
7
7
7
µs
tc(W)ER
Cycle time, sector-erase
operation
tWHWH2
7
7
7
s
Cycle time, chip-erase
operation
tWHWH3
7
30
7
30
7
30
s
NOTES: 9. Sector-protect timing
10. Sector-unprotect timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
27
SMJS849B − MARCH 1997 − REVISED JUNE 1998
switching characteristics over recommended ranges of supply voltage and ambient temperature,
controlled by CE (see Figure 14)
PARAMETER
tc(W)
Cycle time, write
ALTERNATE
SYMBOL
’29F002R-90
MIN
TYP
’29F002R-100
MAX
MIN
TYP
’29F002R-120
MAX
MIN
TYP
MAX
UNIT
tAVAV
90
100
120
ns
Cycle time, sector-erase
operation
tEHEH2
1
1
1
s
Cycle time, chip-erase
operation
tEHEH3
7
7
60
7
60
60
s
th(A)
Hold time, address
tELAX
45
50
50
ns
th(D)
Hold time, data
tEHDX
45
50
50
ns
th(W)
Hold time, WE
tEHWH
0
0
0
ns
th(C)
Hold time, OE read
tEHGL1
0
0
0
ns
Hold time, OE toggle, data
tEHGL2
10
10
10
ns
Pulse duration, CE low
tELEH1
45
45
45
ns
tw(EH) Pulse duration, CE high
tEHEL
20
20
20
ns
Recovery time, read before
trec(R)
write
tGHEL
0
0
0
ns
tsu(A)
Setup time, address
tAVEL
0
0
0
ns
tsu(D)
Setup time, data
tDVEH
45
50
50
ns
tsu(W)
Setup time, WE
tWLEL
0
0
0
ns
tGLEL
0
tw(EL)
Setup time, OE
Programming operation
28
tEHEH1
POST OFFICE BOX 1443
0
7
• HOUSTON, TEXAS 77251−1443
0
7
ns
7
µs
SMJS849B − MARCH 1997 − REVISED JUNE 1998
erase and program performance†
PARAMETER
TEST CONDITIONS
MIN
Sector-erase time
Excludes 00H programming prior to
erasure
Program time
Excludes system-level overhead
Chip-programming time
TYP
MAX
UNIT
1‡
15§
s
9
3 600§
µs
6‡
50§
s
9
Excludes system-level overhead
Erase/program cycles
10 000 100 000 cycles
† The internal algorithms allow for 2.5-ms/byte program time. DQ5 = 1 only after a byte takes the theoretical maximum time to program. A minimal
number of bytes can require signficantly more programming pulses than the typical byte. The majority of the bytes program within one or two
pulses. This is demonstrated by the typical and maximum programming time listed above.
‡ 25°C, 5-V VCC,100 000 cycles, typical pattern
§ Under worst-case conditions: 90°C, 5-V VCC, 100 000 cycles
latchup characteristics (see Note 11)
PARAMETER
MIN
MAX
UNIT
Input voltage with respect to VSS on all pins except I/O pins (including A9 and OE)
−1
13
V
Input voltage with respect to VSS on all I/O pins
−1
VCC + 1
100
V
Current
− 100
mA
NOTE 11: Includes all pins except VCC test conditions: VCC = 5 V, one pin at a time
pin capacitance, all packages (see Note 12)
PARAMETER
CIN
Input capacitance
COUT
Output capacitance
TEST CONDITIONS
VIN = 0
VOUT = 0
CIN2
Control pin capacitance
NOTE 12: Test conditions: TA = 25°C, f = 1 MHz
VIN = 0
TYP
MAX
6
7.5
UNIT
pF
8.5
12
pF
8
10
pF
MIN
MAX
data retention
PARAMETER
Minimum pattern data retention time
POST OFFICE BOX 1443
TEST CONDITIONS
150°C
10
125°C
20
• HOUSTON, TEXAS 77251−1443
UNIT
Years
29
SMJS849B − MARCH 1997 − REVISED JUNE 1998
read operation
tAVAV
Valid Addresses
Addresses
tAVQV
CE
tEHQZ
tELQV
OE
tGHQZ
tGLQV
WE
tGLQX
tAXQX
tELQX
Valid Data
DQ
Figure 12. AC Waveform for Read Operation
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SMJS849B − MARCH 1997 − REVISED JUNE 1998
write operation
tAVAV
555H
Addresses
2AAH
555H
PA
PA
tWLAX
tAVWL
CE
tELWL
tWHEH
OE
tWHDX
tGHWL
tWHWL
tWLWH1
WE
tWHWH1
tDVWH
DQ
AAH
55H
A0H
PD
DQ7
DOUT
NOTES: A. PA = Address to be programmed
B. PD = Data to be programmed
C. DQ7 = Complement of data written to DQ7
Figure 13. AC Waveform for Program Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
31
SMJS849B − MARCH 1997 − REVISED JUNE 1998
write operation (continued)
tAVAV
555H
Addresses
2AAH
555H
PA
PA
tAVEL
tELAX
tELEH1
CE
tEHEL
tGHEL
OE
tDVEH
tWLEL
tEHWH
tEHEH1
WE
tEHDX
DQ
AAH
55H
A0H
PD
DQ7
NOTES: A. PA = Address to be programmed
B. PD = Data to be programmed
C. DQ7 = Complement of data written to DQ7
Figure 14. AC Waveform for Alternate CE-Controlled Write Operation
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DOUT
SMJS849B − MARCH 1997 − REVISED JUNE 1998
chip-erase operation
tAVAV
555H
555H
Addresses
2AAH
555H
VA
tWLAX
tAVWL
CE
tELWL
tWHEH
OE
tWHDX
tGHWL
tWHWL
tWLWH1
WE
tWHWH3
tDVWH
DQ
80H
AAH
55H
10H
DQ7=0
DOUT=FFH
NOTES: A. VA = any valid address
B. Figure details the last four bus cycles in a six-bus-cycle operation.
Figure 15. AC Waveform for Chip-Erase Operation
POST OFFICE BOX 1443
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33
SMJS849B − MARCH 1997 − REVISED JUNE 1998
sector-erase operation
tAVAV
555H
555H
Addresses
2AAH
SA
SA
tWLAX
tAVWL
CE
tELWL
tWHEH
OE
tWHDX
tGHWL
tWHWL
tWLWH1
WE
tWHWH2
tDVWH
DQ
80H
AAH
55H
30H
NOTES: A. SA = Sector address to be erased
B. Figure details the last four bus cycles in a six-bus-cycle operation.
Figure 16. AC Waveform for Sector-Erase Operation
34
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DQ7=0
DOUT=FFH
SMJS849B − MARCH 1997 − REVISED JUNE 1998
data-polling operation
AIN
Addresses
AIN
AIN
tAVQV
tAVQV
tELQV
tAXQX
tELQV
CE
tGLQV
tGLQV
OE
tGHQZ
tWHGL1
WE
tWHWH1, 2, or 3
DQ
DIN
NOTES: A.
B.
C.
D.
DIN
DQ7
DOUT
AIN
DQ7
=
=
=
=
DQ7
DQ7
DOUT
Last command data written to the device
Complement of data written to DQ7
Valid data output
Valid address for byte-program, sector-erase, or chip-erase operation
Figure 17. AC Waveform for Data-Polling Operation
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35
SMJS849B − MARCH 1997 − REVISED JUNE 1998
toggle-bit operation
AIN
Addresses
tAVQV
tELQV
tELQV
CE
tGLQV
tGLQV
OE
tWHGL2
WE
tWHWH1, 2 or 3
DQ
DIN
DOUT
DQ6 = TOGGLE
NOTES: A.
B.
C.
D.
DIN
DQ6
DOUT
AIN
=
=
=
=
DQ6 = TOGGLE
DQ6 = TOGGLE
Last command data written to the device
Toggle bit output
Valid data output
Valid address for byte-program, sector-erase, or chip-erase operation
Figure 18. AC Waveforms for Toggle-Bit Operation
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DQ6 = STOP
TOGGLE
SMJS849B − MARCH 1997 − REVISED JUNE 1998
sector-protect operation
Sector Address
A13 −A17
VID
A9
tHVT
A6
A1
A0
CE
VID
OE
tGHVWL
tHVT
tHVT
tWLWH2
WE
tGLQV
DQ
DOUT
NOTES: A. DOUT = 00H if the selected sector is not protected,
01H if the sector is protected.
B. VCC = 5 V, TA = 25°C
Figure 19. AC Waveform for Sector-Protect Operation
POST OFFICE BOX 1443
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37
SMJS849B − MARCH 1997 − REVISED JUNE 1998
sector-unprotect operation
Sector Address
A13 −A17
VID
tAVQV
A9
tHVT
A6
A1
A0
CE
VID
OE
tGHVWL
tHVT
tWLWH3
WE
tGLQV
DQ
DOUT
NOTES: A. DOUT = 00H if the selected sector is not protected,
01H if the sector is protected.
B. VCC = 5 V, TA = 25°C
Figure 20. AC Waveform for Sector-Unprotect Operation
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMJS849B − MARCH 1997 − REVISED JUNE 1998
temporary sector-unprotect operation
12 V
5V
RESET
tHVT
CE
WE
tRSP
Program or Erase Command Sequence
Figure 21. Temporary Sector-Unprotect Timing Diagram
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
39
SMJS849B − MARCH 1997 − REVISED JUNE 1998
MECHANICAL DATA
FM (R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane
0.004 (0,10)
0.140 (3,56)
0.132 (3,35)
0.495 (12,57)
4
0.485 (12,32)
0.129 (3,28)
0.123 (3,12)
0.453 (11,51)
0.447 (11,35)
0.049 (1,24)
0.043 (1,09)
1
0.008 (0,20) NOM
30
29
5
0.020 (0,51)
0.015 (0,38)
0.595 (15,11)
0.585 (14,86)
0.553 (14,05)
0.547 (13,89)
0.030 (0,76)
TYP
21
13
14
20
0.050 (1,27)
4040201-4 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
40
POST OFFICE BOX 1443
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