SN74LVC1G79-EP www.ti.com....................................................................................................................................................... SCES646A – AUGUST 2005 – REVISED APRIL 2009 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP FEATURES 1 • • • • • • • • Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability • • • DCK PACKAGE (TOP VIEW) D 1 CLK 2 GND 3 5 VCC 4 Q See mechanical drawings for dimensions. (1) Additional temperature ranges are available - contact factory DESCRIPTION/ORDERING INFORMATION This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA –55°C to 115°C (1) (2) PACKAGE SOT (SC-70) – DCK (1) ORDERABLE PART NUMBER Reel of 3000 SN74LVC1G79WDCKREP TOP-SIDE MARKING (2) CR_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCK: The actual top-side marking has one additional character that designates the assembly/test site. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2009, Texas Instruments Incorporated SN74LVC1G79-EP SCES646A – AUGUST 2005 – REVISED APRIL 2009....................................................................................................................................................... www.ti.com FUNCTION TABLE INPUTS CLK D ↑ H OUTPUT Q H ↑ L L L X Q0 LOGIC DIAGRAM (POSITIVE LOGIC) CLK 2 C C C 4 TG C C Q C C D 1 TG TG TG C C C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 2 DCK package –65 ±100 mA 252 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79-EP SN74LVC1G79-EP www.ti.com....................................................................................................................................................... SCES646A – AUGUST 2005 – REVISED APRIL 2009 Recommended Operating Conditions (1) MIN VCC Operating Supply voltage 1.65 Data retention only 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage 1.7 VCC = 3 V to 3.6 V 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V 2 VCC = 4.5 V to 5.5 V VIL UNIT V 1.5 VCC = 1.65 V to 1.95 V VIH MAX 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V VCC = 4.5 V –32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current Δt/Δv 8 16 VCC = 3 V Input transition rise or fall rate 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 4.5 V VCC = 5 V ± 0.5 V TA mA –24 ns/V 5 –55 115 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79-EP Submit Documentation Feedback 3 SN74LVC1G79-EP SCES646A – AUGUST 2005 – REVISED APRIL 2009....................................................................................................................................................... www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA CLK or D inputs 0.4 VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND V 0.55 4.5 V 0.55 0 to 5.5 V ±10 µA 0 ±10 µA 1.65 V to 5.5 V 10 µA 500 µA VI = 5.5 V or GND Ioff (1) 3.8 3V IOL = 24 mA II 2.3 IOH = –32 mA IOL = 16 mA UNIT V 2.4 3V IOH = –24 mA MAX VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN TYP (1) VCC 3 V to 5.5 V 3.3 V 4 pF All typical values are at VCC = 3.3 V, TA = 25°C. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time before CLK↑ th Hold time, data after CLK↑ MAX VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V MAX 160 MIN VCC = 5 V ± 0.5 V MAX 160 MIN UNIT MAX 160 160 2.5 2.5 2.5 2.5 Data high 2.2 1.4 1.3 1.2 Data low 2.6 1.4 1.3 1.2 0.3 0.4 0.5 0.5 MHz ns ns ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) CLK Q fmax VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX 160 tpd 3.9 MIN VCC = 3.3 V ± 0.3 V MAX 160 10.1 MIN VCC = 5 V ± 0.5 V MAX 160 2 7 MIN 160 1.7 5 1 UNIT MAX MHz 4.5 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance Submit Documentation Feedback TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 26 26 27 30 UNIT pF Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79-EP SN74LVC1G79-EP www.ti.com....................................................................................................................................................... SCES646A – AUGUST 2005 – REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G79-EP Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC1G79WDCKREP ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/05621-01XE ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN74LVC1G79-EP : • Catalog: SN74LVC1G79 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC1G79WDCKRE P Package Package Pins Type Drawing SC70 DCK 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 2.25 B0 (mm) K0 (mm) P1 (mm) 2.4 1.22 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G79WDCKREP SC70 DCK 5 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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