TLC59212 www.ti.com .................................................................................................................................................................................................. SCLS713 – MARCH 2009 8-BIT OPEN-COLLECTOR SINK DRIVER WITH LATCH FEATURES 1 • • • • • N OR PW PACKAGE (TOP VIEW) LBC3S (Lin BiCMOS) Process High Voltage Output (VOUT = 24 V) Output Current (IOL Max = 40 mA) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22 – 2000-V Human Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged Device Model (C101) CLR D1 D2 D3 D4 D5 D6 D7 D8 CLK 1 20 VCC 2 19 3 18 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND 4 17 5 16 6 15 7 14 8 13 9 12 10 11 DESCRIPTION The TLC59212 is an 8-bit open-collector driver with latch designed for 5-V VCC operation. These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) input meeting the setup time requirements is transferred to the Y output on the positive-going edge of the clock (CLK) pulse. Clock triggering occcurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D-input has no effect at the output. The TLC59212 is characterized for operation from –40°C to 85°C. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Reel of 1000 TLC59212IN Y59212 TSSOP – PW Reel of 2000 TLC59212IPWR Y59212 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE (EACH LATCH) (1) INPUTS OUTPUT Y CLR CLK D L X X H* H ↑ L H* H ↑ H L H L X Y0 H ↓ X Y0 (1) L: Low-level H: High-level H*: with pullup resistor X: Irrelevant ↑: Rising edge ↓: Falling edge Z : High-impedance (OFF) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TLC59212 SCLS713 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com LOGIC SYMBOL(1) Y2 Y1 19 Y3 18 Y4 Y5 16 17 Y6 15 Y7 Y8 13 14 12 CLK 10 D D D D D D D D CK CK CK CK CK CK CK CK R R R R R R R R CLR 1 3 2 D1 (1) 5 4 D2 D3 6 D4 D5 7 8 9 11 D7 D8 GND D6 This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V D Input voltage range D, CLK, CLR –0.5 7 V VO Output voltage range H output –0.5 30 V IO Output current range 1 bit for output low 40 mA IIK Input clamp current VI < 0 V –20 mA N package 69 PW package 83 θJA Package thermal impedance (2) TA Operating free-air temperature range –40 85 °C Tstg Storage temperature range –65 150 °C (1) (2) °C/W Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS VCC = 4.5 V to 5.5 V CONDITIONS MIN MAX 4.5 5.5 V High-level input voltage VCC × 0.7 VCC V VIL Low-level input voltage 0 VCC × 0.3 V VO Output voltage 0 24 V IO Output current 0 40 mA TA Operating free-air temperature –40 85 °C VCC Supply voltage VIH 2 Duty cycle < 100% Submit Documentation Feedback UNIT Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59212 TLC59212 www.ti.com .................................................................................................................................................................................................. SCLS713 – MARCH 2009 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Vt+ Positive-going input threshold D, CLR, CLK Vt– Negative-going input threshold D, CLR, CLK 1.5 Vt Hysteresis D, CLR, CLK 0.5 VO(off) Output tr sustain voltage Ice = 1 mA 24 IOZ Output tr leakage current VO = 24 V 0 IIH High-level input current VCC = 5.5 V, VI = 5.5 V IIL Low-level input current VCC = 5.5 V, VI = 0 V Ioff Leakage current VI = 0 to 5 V, VO = 0 to 30 V, VCC = 0 ICC Supply current VI = 0 to 5 V, VO = 0 to 30 V, VCC = 0 VOL Low-level output voltage rON ON-state resistance Ci Input capacitance MAX UNIT 3.5 V V 2 V 5 µA 0 1 µA 0 –1 µA 0 5 µA V Output = all OFF 0 5 Output = all ON 8 20 VCC = 4.5 V, IO = 40 mA 0.32 0.55 V VCC = 4.5 V, IO = 10 mA 8 13 Ω VI = VCC or GND 5 µA pF SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted), see Figure 1 TEST CONDITIONS PARAMETER LOAD CAPACITANCE TA = 25°C MIN TA = –40°C to 85°C TYP MAX MIN UNIT MAX tTLH Output = low to high CL = 50 pF, RL = 500 Ω 60 185 185 ns tTHL Output = high to low CL = 50 pF, RL = 500 Ω 10 185 185 ns tPLH Output = low to high CL = 50 pF, RL = 500 Ω 70 210 250 ns tPHL Output = high to low CL = 50 pF, RL = 500 Ω 45 210 250 ns tPHLR CLR-Y CL = 50 pF, RL = 500 Ω 70 210 250 ns TIMING REQUIREMENTS over recommended operating free-air temperature range, VCC = 4.5 V to 5.5 V, O/C to Y (unless otherwise noted) PARAMETER TEST CONDITIONS TA = –40°C to 85°C MIN MAX UNIT tsu Setup time CLK VDD = 4.5 V to 5.5 V 5 ns th Hold time CLK VDD = 4.5 V to 5.5 V 15 ns tw Pulse width CLK, CLR VDD = 4.5 V to 5.5 V 20 ns Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59212 3 TLC59212 SCLS713 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION VCC RL = 500 Ω From Output Under Test CL (see Note A) Open VCC LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUT 5V 50% tsu D 50% th GND tf tr 90% 50% 10% tw 5V 90% 50% 50% CLK 10% tPHL GND tPLH 90% 90% 50% 10% 50% 10% tTHL VCC Y GND tTLH VOLTAGE WAVEFORMS A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, and tf ≤ 3 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Test Circuit and Voltage Waveforms 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59212 PACKAGE OPTION ADDENDUM www.ti.com 21-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC59212IN ACTIVE PDIP N 20 TLC59212IPWR ACTIVE TSSOP PW 20 20 Pb-Free (RoHS) 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC59212IPWR Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.95 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC59212IPWR TSSOP PW 20 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 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