NEC UPD16635N

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16635
240-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64 GRAY SCALES)
The µPD16635 is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because
the output dynamic range is as large as 11.5 VP-P, level inversion operation of the LCD’s common electrode is rendered
unnecessary. Also, to be able to deal with full-dot inversion when mounted on a single side, this source driver is
equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output
gray scale voltages of differing polarity.
Assuring a maximum clock frequency of 33 MHz when driving
at 3.0 V, this driver is applicable to SVGA-standard TFT-LCD panels.
FEATURES
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Output dynamic range 11.5 VP-P min. (@ VDD2 = 13.5 V)
• CMOS level input
• Input of 6 bits (gradation data) by 6 dots
• High-speed data transfer: fmax. = 33 MHz (internal data transfer speed when operating at 3.0 V)
• 240 outputs
• Dedicaded full-dot inversion driver
• Single-sided mounting possible (loaded with slim TCP)
ORDERING INFORMATION
Part Number
µPD16635N-×××
Package
TCP (TAB package)
The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson.
Document No. S11420EJ1V0DS00 (1st edition)
Date Published September 1996 P
Printed in Japan
©
1996
µPD16635
1.
BLOCK DIAGRAM
STHR
R/L
CLK
STB
STHL
VDD1
VSS1
40-bit bidirectional shift register
C1 C 2
C39 C40
D00 - 05
D10 - 15
D20 - 25
D30 - 35
D40 - 45
D50 - 55
Data register
POL
Latch
VDD2
Level shifter
VSS2
V0 - V 9
D/A converter
Voltage follower output
S1
2
S2
S3
S240
µPD16635
RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
S239
S240
5
·····
V0
S2
V4
Multiplexer
V5
6-bit D/A converter
5
·····
2.
V9
POL
POL
S2n–1
S2n
L
V0 to V4
V5 to V9
H
V5 to V9
V0 to V4
S 2n–1 (odd output), S2n (even output) n = 1, 2, ·····, 120
3
µPD16635
3.
PIN CONFIGURATION (µPD16635N-×××)
VSS2
VDD2
VSS1
R/L
POL
STB
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
STHL
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
CLK
STHR
D30
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
TEST
VDD1
VDD2
VSS2
This figure shows the pin connection, not a TCP package.
4
S240
S239
S238
S237
S4
S3
S2
S1
µPD16635
4.
PIN FUNCTIONS
Pin Symbol
Pin Name
Description
S1 to S240
Driver output
The D/A converted 64-gray-scale analog voltage is output.
D00 to D05
Display data input
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by
6 dots (2 pixels).
DX0: LSB, DX5: MSB
R/L
Shift direction
switching input
These refer to the start pulse input/output pins when cascades are connected.
The shift directions of the shift registers are as follows.
R/L = H: STHR input, S1 → S240, STHL output
R/L = L : STHL input, S240 → S1, STHR output
STHR
Right shift start
pulse input/output
R/L = H: Becomes the start pulse input pin.
R/L = L : Becomes the start pulse output pin.
STHL
Left shift start
pulse input/output
R/L = H: Becomes the start pulse output pin.
R/L = L : Becomes the start pulse input pin.
CLK
Shift clock input
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 40th clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-stage driver. The initial-stage driver’s 40th clock becomes
valid as the next-stage driver’s start pulse is input. If 42 clock pulses are input
after input of the start pulse, input of display data is halted automatically. The
contents of the shift register are cleared at the STB’s rising edge.
STB
Latch input
The contents of the data register are transferred to the latch at the rising edge.
And, at the falling edge, the gray scale voltage is supplied to the driver. It is
necessary to ensure input of one pulse per horizontal period.
POL
Polarity input
POL = L; The S2n–1 output uses V0 to V4 as the reference supply; and the S2n
output uses V5 to V9 as the reference supply.
POL = H; The S2n–1 output uses V5 to V9 as the reference supply; and the S2n
output uses V0 to V4 as the reference supply.
S2n – 1 indicates the odd output; and S2n indicates the even output.
Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s
rising edge.
V0 to V9
γ -corrected power
supplies
Input the γ -corrected power supplies from outside. Make sure to maintain the
following relationships. During the gray scale voltage output, be sure to keep the
gray scale level power supply at a constant level.
VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2
TEST
Test pin
Set it to “OPEN”.
VDD1
Logic power supply
3.3 V ± 0.3 V
VDD2
Driver power supply
11.0 V to 13.5 V
VSS1
Logic ground
Grounding
VSS2
Driver ground
Grounding
D10 to D15
D20 to D25
D31 to D35
D40 to D45
D50 to D55
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse
this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V0, V1, V2, ···, V9) and VSS2.
5
µPD16635
5.
RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output
respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common
electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors r0 to r 62
are so designed that the ratios between the LCD panel’s γ -corrected voltages and V 0’ to V 63’ and V0” to V 63” are
roughly equal; and their respective resistance values are as shown on page 9. Among the 5-by-2 γ -corrected
voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective
five γ -corrected voltages of V 0 to V 4 and V5 to V 9. If fine gray scale voltage precision is not necessary, the voltage
follower circuit supplied to the γ -corrected power supplies V 1 to V3 and V 6 to V 8 can be deleted.
Figure 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and
V SS2, common electrode potential VCOM, and γ -corrected voltages V 0 to V 9 and the input data. Be sure to maintain
the voltage relationships of V DD2 > V 0 > V 1 > V2 > V 3 > V 4 > V5 > V 6 > V7 > V 8 > V 9 > VSS2. Figures 2-1 and 22 show the relationship between the input data and the output data. Table 1 shows the resistance values of
the resistor strings.
This driver IC is designed for single-sided dot inversion mounting. Therefore, it cannot be used in doublesided mounting.
Figure 1. Relationship Between Input Data and Output Voltage
0.2 V
VDD2
Split interval
V0
8
V1
24
V2
24
V3
7
V4
VCOM
V5
7
V6
24
V7
24
V8
8
V9
0.2 V
VSS2
00
08
10
18
20
28
30
38
3F
Input data (HEX)
6
µPD16635
Resistor Strings
Figure 2-1. Relationship Between Input Data and Output Voltage: VDD2 > V0 > V1 > V2 > V3 > V4 > V5
V0
V0’
Data
V1’
00H
01H
02H
03H
04H
05H
06H
07H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V0’
V1’
V2’
V3’
V4’
V5’
V6’
V7’
V0
V1 + (V0 – V1) × 4500/5300
V1 + (V0 – V1) × 3700/5300
V1 + (V0 – V1) × 2900/5300
V1 + (V0 – V1) × 2200/5300
V1 + (V0 – V1) × 1500/5300
V1 + (V0 – V1) × 900/5300
V1 + (V0 – V1) × 400/5300
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V8’
V9’
V10’
V11’
V12’
V13’
V14’
V15’
V1
V2 + (V1 – V2) × 3600/4000
V2 + (V1 – V2) × 3300/4000
V2 + (V1 – V2) × 3000/4000
V2 + (V1 – V2) × 2700/4000
V2 + (V1 – V2) × 2400/4000
V2 + (V1 – V2) × 2200/4000
V2 + (V1 – V2) × 2000/4000
10H
11H
12H
13H
14H
15H
16H
17H
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V16’
V17’
V18’
V19’
V20’
V21’
V22’
V23’
V2 + (V1 – V2) × 1800/4000
V2 + (V1 – V2) × 1600/4000
V2 + (V1 – V2) × 1400/4000
V2 + (V1 – V2) × 1300/4000
V2 + (V1 – V2) × 1200/4000
V2 + (V1 – V2) × 1100/4000
V2 + (V1 – V2) × 1000/4000
V2 + (V1 – V2) × 900/4000
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V24’
V25’
V26’
V27’
V28’
V29’
V30’
V31’
V2 + (V1 – V2) ×
V2 + (V1 – V2) ×
V2 + (V1 – V2) ×
V2 + (V1 – V2) ×
V2 + (V1 – V2) ×
V2 + (V1 – V2) ×
V2 + (V1 – V2) ×
V2 + (V1 – V2) ×
20H
21H
22H
23H
24H
25H
26H
27H
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V32’
V33’
V34’
V35’
V36’
V37’
V38’
V39’
V2
V3 + (V2 – V3) × 2600/2700
V3 + (V2 – V3) × 2500/2700
V3 + (V2 – V3) × 2400/2700
V3 + (V2 – V3) × 2300/2700
V3 + (V2 – V3) × 2200/2700
V3 + (V2 – V3) × 2100/2700
V3 + (V2 – V3) × 2000/2700
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V40’
V41’
V42’
V43’
V44’
V45’
V46’
V47’
V3 + (V2 – V3) × 1900/2700
V3 + (V2 – V3) × 1800/2700
V3 + (V2 – V3) × 1700/2700
V3 + (V2 – V3) × 1600/2700
V3 + (V2 – V3) × 1500/2700
V3 + (V2 – V3) × 1400/2700
V3 + (V2 – V3) × 1300/2700
V3 + (V2 – V3) × 1200/2700
30H
31H
32H
33H
34H
35H
36H
37H
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V48’
V49’
V50’
V51’
V52’
V53’
V54’
V55’
V3 + (V2 – V3) × 1100/2700
V3 + (V2 – V3) × 1000/2700
V3 + (V2 – V3) × 900/2700
V3 + (V2 – V3) × 800/2700
V3 + (V2 – V3) × 700/2700
V3 + (V2 – V3) × 600/2700
V3 + (V2 – V3) × 400/2700
V3 + (V2 – V3) × 200/2700
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V56’
V57’
V58’
V59’
V60’
V61’
V62’
V63’
V3
V4 + (V3 – V4) × 2300/2500
V4 + (V3 – V4) × 2100/2500
V4 + (V3 – V4) × 1800/2500
V4 + (V3 – V4) × 1500/2500
V4 + (V3 – V4) × 1200/2500
V4 + (V3 – V4) × 800/2500
V4
r0
r1
V2’
r2
V3’
r3
V4’
r4
V5’
r5
V6’
r6
V7’
r7
V8’
V1
r8
V9’
r9
r30
V31’
r31
V32’
V2
r32
V33’
r33
r54
V55’
r55
V56’
V3
r56
V57’
r57
V58’
r58
V59’
r59
V60’
r60
V61’
r61
V62’
r62
V63’
V4
r4–5
V5
Caution
9 kΩ
V63’’
DX5 DX4 DX3 DX2 DX1 DX0
Output Voltage
800/4000
700/4000
600/4000
500/4000
400/4000
300/4000
200/4000
100/4000
V4 and V5 are interconnected inside the IC by resistors r4-5 (9 kΩ).
7
µPD16635
Resistor Strings
Figure 2-1. Relationship Between Input Data and Output Voltage: V4 > V5 > V6 > V7 > V8 > V9 > VSS2
Data
V4
V63’
r4–5
9 kΩ
V63’’
V5
r62
V62’’
r61
V61’’
r60
V60’’
r59
V59’’
r58
V58’’
r57
V57’’
r56
V56’’
V6
r55
V55’’
r54
r33
V33’’
r32
V32’’
V7
r31
V31’’
r30
r9
V9’’
r8
V8’’
V8
r7
V7’’
r6
V6’’
r5
V5’’
r4
V4’’
r3
V3’’
r2
V2’’
r1
V1’’
r0
V9
Caution
8
V0’’
DX5 DX4 DX3 DX2 DX1 DX0
Output Voltage
00H
01H
02H
03H
04H
05H
06H
07H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V0’’
V1’’
V2’’
V3’’
V4’’
V5’’
V6’’
V7’’
V9
V9 + (V8 – V9) × 800/5300
V9 + (V8 – V9) × 1600/5300
V9 + (V8 – V9) × 2400/5300
V9 + (V8 – V9) × 3100/5300
V9 + (V8 – V9) × 3800/5300
V9 + (V8 – V9) × 4400/5300
V9 + (V8 – V9) × 4900/5300
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V8’’
V9’’
V10’’
V11’’
V12’’
V13’’
V14’’
V15’’
V8
V8 + (V7 – V8) × 400/4000
V8 + (V7 – V8) × 700/4000
V8 + (V7 – V8) × 1000/4000
V8 + (V7 – V8) × 1300/4000
V8 + (V7 – V8) × 1600/4000
V8 + (V7 – V8) × 1800/4000
V8 + (V7 – V8) × 2000/4000
10H
11H
12H
13H
14H
15H
16H
17H
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V16’’
V17’’
V18’’
V19’’
V20’’
V21’’
V22’’
V23’’
V8 + (V7 – V8) × 2200/4000
V8 + (V7 – V8) × 2400/4000
V8 + (V7 – V8) × 2600/4000
V8 + (V7 – V8) × 2700/4000
V8 + (V7 – V8) × 2800/4000
V8 + (V7 – V8) × 2900/4000
V8 + (V7 – V8) × 3000/4000
V8 + (V7 – V8) × 3100/4000
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V24’’
V25’’
V26’’
V27’’
V28’’
V29’’
V30’’
V31’’
V8 + (V7 – V8) × 3200/4000
V8 + (V7 – V8) × 3300/4000
V8 + (V7 – V8) × 3400/4000
V8 + (V7 – V8) × 3500/4000
V8 + (V7 – V8) × 3600/4000
V8 + (V7 – V8) × 3700/4000
V8 + (V7 – V8) × 3800/4000
V8 + (V7 – V8) × 3900/4000
20H
21H
22H
23H
24H
25H
26H
27H
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V32’’
V33’’
V34’’
V35’’
V36’’
V37’’
V38’’
V39’’
V7
V7 + (V6 – V7) ×
V7 + (V6 – V7) ×
V7 + (V6 – V7) ×
V7 + (V6 – V7) ×
V7 + (V6 – V7) ×
V7 + (V6 – V7) ×
V7 + (V6 – V7) ×
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V40’’
V41’’
V42’’
V43’’
V44’’
V45’’
V46’’
V47’’
V7 + (V6 – V7) × 800/2700
V7 + (V6 – V7) × 900/2700
V7 + (V6 – V7) × 1000/2700
V7 + (V6 – V7) × 1100/2700
V7 + (V6 – V7) × 1200/2700
V7 + (V6 – V7) × 1300/2700
V7 + (V6 – V7) × 1400/2700
V7 + (V6 – V7) × 1500/2700
30H
31H
32H
33H
34H
35H
36H
37H
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V48’’
V49’’
V50’’
V51’’
V52’’
V53’’
V54’’
V55’’
V7 + (V6 – V7) × 1600/2700
V7 + (V6 – V7) × 1700/2700
V7 + (V6 – V7) × 1800/2700
V7 + (V6 – V7) × 1900/2700
V7 + (V6 – V7) × 2000/2700
V7 + (V6 – V7) × 2100/2700
V7 + (V6 – V7) × 2300/2700
V7 + (V6 – V7) × 2500/2700
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V56’’
V57’’
V58’’
V59’’
V60’’
V61’’
V62’’
V63’’
V6
V6 + (V5 – V6) × 200/2500
V6 + (V5 – V6) × 400/2500
V6 + (V5 – V6) × 700/2500
V6 + (V5 – V6) × 1000/2500
V6 + (V5 – V6) × 1300/2500
V6 + (V5 – V6) × 1700/2500
V5
V4 and V5 are interconnected inside the IC by resistors r4-5 (9 kΩ).
100/2700
200/2700
300/2700
400/2700
500/2700
600/2700
700/2700
µPD16635
Ladder Resistance Values (r0 to r62): Reference Value
V0, V9
V1, V8
V2, V7
Resistor
Name
Resistance
Value (Ω)
Resistor
Name
Resistance
Value (Ω)
r0
800
r32
100
r1
800
r33
100
r2
800
r34
100
r3
700
r35
100
r4
700
r36
100
r5
600
r37
100
r6
500
r38
100
r7
400
r39
100
r8
400
r40
100
r9
300
r41
100
r10
300
r42
100
r11
300
r43
100
r12
300
r44
100
r13
200
r45
100
r14
200
r46
100
r15
200
r47
100
r16
200
r48
100
r17
200
r49
100
r18
100
r50
100
r19
100
r51
100
r20
100
r52
100
r21
100
r53
200
r22
100
r54
200
r23
100
r55
200
r24
100
r56
200
r25
100
r57
200
r26
100
r58
300
r27
100
r59
300
r28
100
r60
300
r29
100
r61
400
r30
100
r62
r31
100
Total
800
14500
V2 , V 7
V3 , V 6
V4 , V 5
9
µPD16635
6.
RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits × 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
R/L = H (Right shift)
Output
Data
S1
S2
S3
S4
S5
···
S239
S240
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
···
D40 to D45
D50 to D55
S1
S2
S3
S4
S5
···
S239
S240
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
···
D40 to D45
D50 to D55
R/L = L (Left shift)
Output
Data
POL
S2n–1
S2n
L
V0 to V4
V5 to V9
H
V5 to V9
V0 to V4
S 2n–1 (Odd output), S 2n (Even output) n = 1, 2, ·····, 120
7.
RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB rising edge.
STB
POL
S2n–1
Selected voltage of V0 to V4
Selected voltage of V5 to V9
Selected voltage of V0 to V4
S2n
Selected voltage of V5 to V9
Hi-Z
10
Selected voltage of V0 to V4
Hi-Z
Selected voltage of V5 to V9
Hi-Z
µPD16635
Absolute Maximum Ratings (TA = 25 ˚C, V
Parameter
SS1
= VSS2 = 0 V)
Symbol
Rating
Unit
Logic Part Supply Voltage
VDD1
–0.5 to +6.5
V
Driver Part Supply Voltage
VDD2
–0.5 to +15.0
V
Logic Part Input Voltage
VI1
–0.5 to VDD1 + 0.5
V
Driver Part Input Voltage
VI2
–0.5 to VDD2 + 0.5
V
Logic Part Output Voltage
VO1
–0.5 to VDD1 + 0.5
V
Driver Part Output Voltage
VO2
–0.5 to VDD2 + 0.5
V
Operating Temperature Range
TA
–10 to +75
°C
Storage Temperature Range
Tstg.
–55 to +125
°C
Recommended Operating Range (TA = –10 to +75 ˚C, V
Parameter
SS1
= VSS2 = 0 V)
Symbol
MIN.
TYP.
MAX.
Unit
Logic Part Supply Voltage
VDD1
3.0
3.3
3.6
V
Driver Part Supply Voltage
VDD2
11.0
13.0
13.5
V
High-Level Input Voltage
VIH
0.8 VDD1
VDD1
V
Low-Level Input Voltage
VIL
0
0.2 VDD1
V
VSS2 + 0.1
VDD2 – 0.1
V
VDD2 – 0.2
V
γ -Corrected Voltage
V0 to V9
Driver Part Output Voltage
VO
VSS2 + 0.2
Maximum Clock Frequency
fmax.
33
MHz
Electrical Specifications (TA = –10 to +75 °C, VDD1 = 3.3 V ±0.3 V, VDD2 = 13.0 V ±0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
Input Leak Current
IL
High-Level Output Voltage
VOH
STHR (STHL), IO = 0 mA
Low-level Output Voltage
VOL
STHR (STHL), IO = 0 mA
γ -Corrected Supply Current
Driver Output Current
V0 – V9 = 10 V
IVOH
VX – VOUT = 6 V
IVOL
VX – VOUT = –6 V
MIN.
TYP.
MAX.
Unit
±1.0
µA
VDD1 – 0.1
V0 , V9
V
0.3
0.3
0.1
V
0.6
mA
–0.3
mA
mA
V X refers to the output voltage of analog output pins S1 to S 240 .
V OUT refers to the voltage applied to analog output pins S1 to S 240 .
11
µPD16635
Electrical Specifications (TA = –10 to +75 °C, VDD1 = 3.3 V ±0.3 V, VDD2 = 13.0 V ±0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
±20
mV
∆VO
Input data: 00H to 3FH
±5
Average Output Voltage
VariationNote 2
∆VAV
Input data: 00H to 3FH
±10
Output Voltage Range
VO
Input data: 00H to 3FH
Output Voltage
DeviationNote 1
loadNotes 3, 4
Logic Part Dynamic Current
Consumption
IDD1
VDD1; when with no
Driver Part Dynamic Current
Consumption
IDD2
VDD2; when with no loadNotes 3, 4
0.2
mV
VDD2 – 0.2
V
1.0
6.0
mA
3.5
9.0
mA
Notes 1. The output voltage deviation refers to the voltage difference between adjoining output pins when the
display data is the same (within the chip).
2. The average output voltage variation refers to the average output voltage difference between chips.
The average output voltage refers to the average voltage between chips when the display data is the
same.
3. The STB cycle is defined to be 30 µs at fCLK = 25 MHz.
The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured
values in the dot checkerboard input pattern.
4. Refers to the current consumption per driver when cascades are connected under the assumption of
SVGA single-sided mounting (10 units).
Switching Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ±0.3 V, VDD2 = 13.0 V ±0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Start Pulse Delay Time
tPLH1
CL = 25 pF
10
15
ns
Driver Output Delay Time 1
tPHL2
CL = 50 pF, R = 50 kΩ
7
11
µs
Driver Output Delay Time 2
tPHL3
CL = 50 pF, R = 50 kΩ
13
17
µs
Driver Output Delay Time 3
tPLH2
CL = 50 pF, R = 50 kΩ
7
11
µs
Driver Output Delay Time 4
tPLH3
CL = 50 pF, R = 50 kΩ
13
17
µs
Input Capacitance 1
C1
STHR, STHL excluded
5
15
pF
5
15
pF
TA = 25 °C
Input Capacitance 2
12
C2
STHR, STHL
TA = 25 °C
µPD16635
Conditions Required for Timing
(TA = –10 to +75 °C, VDD1 = 3.3 V ±0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock Pulse Width
PWCLK
30
ns
Clock Pulse Low Period
PWCLK(L)
6
ns
Clock Pulse High Period
PWCLK(H)
6
ns
Data Setup Time
tSETUP1
6
ns
Data Hold Time
tHOLD1
6
ns
Start Pulse Setup Time
tSETUP2
6
ns
Start Pulse Hold Time
tHOLD2
6
ns
Start Pulse Low Period
tSPL
6
ns
STB Pulse Width
PWSTB
1
µs
Data Invalid Period
tINV
1
CLK
Final Data Timing
tLDT
2
CLK
CLK-STB Time
tCLK-STB
CLK ↑ → STB ↓
6
ns
STB-CLK Time
tSTB-CLK
STB ↓ → CLK ↑
6
ns
Time Between STB and
Start Pulse
tSTB-STH
STB ↓ → STHR ↑
60
ns
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–5
ns
STB-POL Time
tSTB-POL
STB ↓ → POL ↑ or ↓
6
ns
13
µPD16635
Switching Characteristics Waveform (R/L = H)
In ( ): R/L = L
Unless otherwise specified, the input level is defined to be 0.5 VDD1 .
(1) Initial-Level Driver’s Input/Output Waveform
PWCLK
PWCLK (H)
tf
PWCLK (L)
1
CLK
2
tr
90 % 90 %
VDD1
3
10 % 10 %
tSETUP1
INVALID
DXX
INVALID
VSS1
tHOLD1
1
VDD1
2
VSS1
tHOLD2
tSETUP2
tHOLD2
VDD1
STHR (IN)
(STHL)
VSS1
(2) Second- to Final-Level Drivers’s Input/Output Timing
40
41
1
1
CLK
2
3
40
41
VDD1
VSS1
VDD1
Dxx
39
40
1
2
39
40
VSS1
tPLH1
Initial-level
output
STHR (IN)
(STHL)
tSETUP2
VDD1
tPLH1
tSETUP2
VSS1
VDD1
STHL (OUT)
(STHR)
14
VSS1
µPD16635
(3) Driver Output Timing
VDD1
DXX
40
INVALID
VSS1
tHOLD2
CLK
42
41
43
1
VDD1
VSS1
tINV
tCLK-STB tSTB-CLK
PWSTB
tLDT
VDD1
STB
VSS1
tPOL-STB
tSTB-POL
VDD1
POL
VSS1
tSTB-STH
tSETUP2
tHOLD2
VDD1
STHR (IN)
(STHL)
VSS1
tSPL
Hi-Z
tPHL3
tPHL2
VDD2
Sn
VX
tPLH3
tPLH2
VX
Sm
Hi-Z
VSS2
V X refers to the final output voltage. t PLH2 and tPHL2 refer to the time required to reach an output precision
level of 10 % (0.1 V X); and t PLH3 and tPHL3 refer to the time required to reach an output precision level of 6 bits.
15
µPD16635
RECOMMENDED CONDITIONS FOR INSTALLATION
This product should be installed under the following recommended conditions. Consult one of our sales
representatives for installation under conditions other than those recommended.
Installation
condition
Thermocompression bonding
Caution
Installation method
Condition
Soldering
Heat with heating tool at 300 °C to 350 °C under pressure of
100 g (per pin) for 2 to 3 seconds
ACF (sheet-type adhesive agent)
Temporary adhesion at 70 °C to 100 °C under pressure of 3 to
8 kg/cm2 for 3 to 5 seconds
Permanent adhesion at 165 °C to 180 °C under pressure of 25
to 45 kg/cm2 for 30 to 40 seconds
(when aeolotropic conductive film SUMIZAC1003 from Sumitomo
Bakelite Co., Ltd. is used)
For installation conditions for the ACF part, contact the ACF manufacturer beforehand. Do not
mix different installation methods.
REFERENCE
Document name
Document No.
NEC semiconductor device reliability/quality control system
IEI-1212
Quality grade on NEC semiconductor devices
C11531E
Semiconductor device package manual
IEI-1213
Guide to quality assurance for semiconductor devices
MEI-1202
Semiconductor selection guide
X10679E
16
µPD16635
[MEMO]
17
µPD16635
[MEMO]
18
µPD16635
[MEMO]
19