NEC UPD16715A

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16715A
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µPD16715A is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values γ-corrected by an internal D/A converter and 5-by-2 external power modules. Because the
output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side,
this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins
respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 55 MHz when
driving at 3.0 V, this driver is applicable to XGA/SXGA-standard TFT-LCD panels.
FEATURES
• CMOS level input
• 384 outputs
• Input of 6 bits (gradation data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
Logic power supply (VDD1): 3.3 V ± 0.3 V
+2.5 V
• Driver power supply (VDD2): 11.0 V –
2.0
• High-speed data transfer: f CLK = 55 MHz (internal data transfer speed when operating at 3.0 V)
•
• Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V
• Apply for only dot-line inversion
• Single bank arrangement is possible (POL)
• Display data inversion function (POL2)
•
•
Low power control function (LPC)
•
Single-sided mounting (Slim TCP)
ORDERING INFORMATION
Part Number
Package
µPD16715AN- xxx
Remark
TCP (TAB package)
The TCP’s external shape is customized. To order your TCP’s external shape, please contact an
NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13944EJ2V0DS00 (2nd edition)
Date Published December 1999 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1998,1999
µ PD16715A
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
STHL
VDD1
VSS1
64-bit bidirectional shift register
C1 C2
C63 C64
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
Data register
POL2
Latch
POL
VDD2
Level shifter
VSS2
V0 to V9
D/A converter
Voltage follower output
LPC
S1
S2
S3
S384
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
V4
Multiplexer
6-bit D/A converter
5
·····
V5
S383
5
·····
V0
S2
V9
POL
2
Data Sheet S13944EJ2V0DS00
S384
µ PD16715A
3. PIN CONFIGURATION (µPD16715AN-×××
×××)
×××
VSS2
VDD2
R,/L
POL
STB
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
D30
STHL
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
VDD1
CLK
VSS1
POL2
STHR
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
LPC
TEST
VDD2
VSS2
S384
S383
S382
S381
Copper Foil
Surface
S4
S3
S2
S1
Remark This figure does not specify the TCP package.
Data Sheet S13944EJ2V0DS00
3
µ PD16715A
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
Description
S1 to S384
Driver output
The D/A converted 64-gray scale analog voltage is output.
D00 to D05
Display data input
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
by 6 dots (2 pixels).
DX0 : LSB, DX5: MSB
R,/L
Shift direction control
input
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R,/L = H: STHR input, S1 → S384, STHL output
R,/L = L : STHL input, S384 → S1, STHR output
STHR
Right shift start pulse
input/output
R,/L = H: Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
STHL
Left shift start pulse
input/output
R,/L = H: Becomes the start pulse output pin.
R,/L = L : Becomes the start pulse input pin.
CLK
Shift clock input
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 64th clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-level driver. The initial-level driver’s 64th clock becomes
valid as the next-level driver’s start pulse is input. If 66 clock pulses are input after
input of the start pulse, input of display data is halted automatically. The contents
of the shift register are cleared at the STB’s rising edge.
STB
Latch input
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is
necessary to ensure input of one pulse per horizontal period.
POL
Polarity input
POL = L: The S2n–1 output uses V0 to V4 as the reference supply ;
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
The S2n output uses V5 to V9 as the reference supply.
POL = H : The S2n–1 output uses V5 to V9 as the reference supply ;
The S2n output uses V0 to V4 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL
signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
POL2
Data inversion
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted
LPC
Driver voltage selection
The output buffer constant current source is blocked, reducing current consumption.
Low power mode (LPC = ‘H’: DC-level input possible). The condition that low power
mode can be used is that the load constant is at least 10 kΩ + 50 pF.
4
V0 to V9
γ -corrected power
supplies
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
TEST
Test pin
Test pin. Please input H or Open.
VDD1
Logic power supply
3.3 V ± 0.3 V
VDD2
Driver power supply
VSS1
Logic ground
Grounding
VSS2
Driver ground
Grounding
11.0 V
+ 2.5
− 2.0
V
Data Sheet S13944EJ2V0DS00
µ PD16715A
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse
this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.47 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a
bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V0, V1, V2, ···, V9) and VSS2.
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The µPD16715A incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD's counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches. The ladder resistors r0 to r62 are so designed that the ratios
between the LCD panel's γ - corrected voltages and V0' to V63' and V0" to V63" are roughly equal; and their respective
resistance values are as shown on next page. Among the 5-by-2 γ -corrected voltages, input gray scale voltages of
the same polarity with respect to the common voltage, for the respective five γ -corrected voltages of V0 to V4 and V5
to V9
Figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,
common electrode potential VCOM, and γ - corrected voltages V0 to V9 and the input data. Be sure to maintain the
voltage relationships of
VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V.
Figures 5-2 and 5-3 show the relationship between the input data and the output voltage. Therefore, please do not
use it for γ - corrected power supply level inversion in double-sided mounting.
−1. Relationship Between Input Data and γ - corrected Power Supply
Figure 5−
VDD2
0.1 V
V0
8
V1
24
V2
24
V3
7
V4
VCOM
Split interval
V5
7
V6
24
V7
24
V8
8
V9
0.1 V
VSS2
00
08
20
38
3F
Input Data (HEX)
Data Sheet S13944EJ2V0DS00
5
µ PD16715A
−2. Relationship between Input Data and Output Voltage (1/2)
Figure 5−
VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4
V0
V0’
r0
V1’
r1
V2’
r2
V3’
r3
V4’
r4
V5’
r5
V6’
r6
V7’
r7
V1
V8’
r8
V9’
r9
r30
V31’
r31
V2
V32’
r32
V33’
r33
r54
V55’
r55
V3
V56’
r56
V57’
r57
V58’
r58
V59’
r59
V60’
r60
V61’
r61
V62’
r62
V4
V63’
V5
V63’’
r62
V62’’
r61
V61’’
r60
6
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V0'
V1'
V2'
V3'
V4'
V5'
V6'
V7'
V8'
V9'
V10'
V11'
V12'
V13'
V14'
V15'
V16'
V17'
V18'
V19'
V20'
V21'
V22'
V23'
V24'
V25'
V26'
V27'
V28'
V29'
V30'
V31'
V32'
V33'
V34'
V35'
V36'
V37'
V38'
V39'
V40'
V41'
V42'
V43'
V44'
V45'
V46'
V47'
V48'
V49'
V50'
V51'
V52'
V53'
V54'
V55'
V56'
V57'
V58'
V59'
V60'
V61'
V62'
V63'
Output Voltage
V0
V1+(V0-V1)×
4300
V1+(V0-V1)×
3550
V1+(V0-V1)×
2850
V1+(V0-V1)×
2200
V1+(V0-V1)×
1600
V1+(V0-V1)×
1050
V1+(V0-V1)×
500
V1
V1+(V0-V1)×
5200
V1+(V0-V1)×
4800
V1+(V0-V1)×
4400
V1+(V0-V1)×
4050
V1+(V0-V1)×
3700
V1+(V0-V1)×
3350
V1+(V0-V1)×
3050
V1+(V0-V1)×
2750
V2+(V1-V2)×
2450
V2+(V1-V2)×
2200
V2+(V1-V2)×
1950
V2+(V1-V2)×
1700
V2+(V1-V2)×
1500
V2+(V1-V2)×
1300
V2+(V1-V2)×
1100
V2+(V1-V2)×
950
V2+(V1-V2)×
800
V2+(V1-V2)×
650
V2+(V1-V2)×
500
V2+(V1-V2)×
400
V2+(V1-V2)×
300
V2+(V1-V2)×
200
V2+(V1-V2)×
100
V2
V3+(V2-V3)×
2450
V3+(V2-V3)×
2350
V3+(V2-V3)×
2250
V3+(V2-V3)×
2150
V3+(V2-V3)×
2050
V3+(V2-V3)×
1950
V3+(V2-V3)×
1850
V3+(V2-V3)×
1750
V3+(V2-V3)×
1650
V3+(V2-V3)×
1550
V3+(V2-V3)×
1450
V3+(V2-V3)×
1350
V3+(V2-V3)×
1250
V3+(V2-V3)×
1150
V3+(V2-V3)×
1050
V3+(V2-V3)×
950
V4+(V3-V4)×
850
V4+(V3-V4)×
750
V4+(V3-V4)×
650
V4+(V3-V4)×
550
V4+(V3-V4)×
450
V4+(V3-V4)×
300
V4+(V3-V4)×
150
V3
V4+(V3-V4)×
2300
V4+(V3-V4)×
2100
V4+(V3-V4)×
1850
V4+(V3-V4)×
1600
V4+(V3-V4)×
1300
V4+(V3-V4)×
800
V4
Data Sheet S13944EJ2V0DS00
/
/
/
/
/
/
/
5100
5100
5100
5100
5100
5100
5100
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
/
/
/
/
/
/
2500
2500
2500
2500
2500
2500
r n(Ω)
r0
800
r1
750
r2
700
r3
650
r4
600
r5
550
r6
550
r7
500
r8
500
r9
400
r10 400
r11 350
r12 350
r13 350
r14 300
r15 300
r16 300
r17 250
r18 250
r19 250
r20 200
r21 200
r22 200
r23 150
r24 150
r25 150
r26 150
r27 100
r28 100
r29 100
r30 100
r31 100
r32 100
r33 100
r34 100
r35 100
r36 100
r37 100
r38 100
r39 100
r40 100
r41 100
r42 100
r43 100
r44 100
r45 100
r46 100
r47 100
r48 100
r49 100
r50 100
r51 100
r52 100
r53 150
r54 150
r55 150
r56 200
r57 200
r58 250
r59 250
r60 300
r61 500
r62 800
rtotal 15850
µ PD16715A
−3. Relationship between Input Data and Output Voltage (2/2)
Figure 5−
V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
r60
V61’
r61
V62’
r62
V4
V63’
V5
V63’’
r62
V62’’
r61
V61’’
r60
V60’’
r59
V59’’
r58
V58’’
r57
V57’’
r56
V56’’
V6
r55
V55’’
r54
r33
V33’’
r32
V32’’
V7
r31
V31’’
r30
r9
V9’’
r8
V8’’
V8
r7
V7’’
r6
V6’’
r5
V5’’
r4
V4’’
r3
V3’’
r2
V2’’
r1
V1’’
r0
V9
V0’’
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V0''
V1''
V2''
V3''
V4''
V5''
V6''
V7''
V8''
V9''
V10''
V11''
V12''
V13''
V14''
V15''
V16''
V17''
V18''
V19''
V20''
V21''
V22''
V23''
V24''
V25''
V26''
V27''
V28''
V29''
V30''
V31''
V32''
V33''
V34''
V35''
V36''
V37''
V38''
V39''
V40''
V41''
V42''
V43''
V44''
V45''
V46''
V47''
V48''
V49''
V50''
V51''
V52''
V53''
V54''
V55''
V56''
V57''
V58''
V59''
V60''
V61''
V62''
V63''
Output Voltage
V9
V9+(V8-V9)×
800
V9+(V8-V9)×
1550
V9+(V8-V9)×
2250
V9+(V8-V9)×
2900
V9+(V8-V9)×
3500
V9+(V8-V9)×
4050
V9+(V8-V9)×
4600
V8
V9+(V8-V9)×
500
V9+(V8-V9)×
900
V9+(V8-V9)×
1300
V9+(V8-V9)×
1650
V9+(V8-V9)×
2000
V9+(V8-V9)×
2350
V9+(V8-V9)×
2650
V9+(V8-V9)×
2950
V8+(V7-V8)×
3250
V8+(V7-V8)×
3500
V8+(V7-V8)×
3750
V8+(V7-V8)×
4000
V8+(V7-V8)×
4200
V8+(V7-V8)×
4400
V8+(V7-V8)×
4600
V8+(V7-V8)×
4750
V8+(V7-V8)×
4900
V8+(V7-V8)×
5050
V8+(V7-V8)×
5200
V8+(V7-V8)×
5300
V8+(V7-V8)×
5400
V8+(V7-V8)×
5500
V8+(V7-V8)×
5600
V7
V7+(V6-V7)×
100
V7+(V6-V7)×
200
V7+(V6-V7)×
300
V7+(V6-V7)×
400
V7+(V6-V7)×
500
V7+(V6-V7)×
600
V7+(V6-V7)×
700
V7+(V6-V7)×
800
V7+(V6-V7)×
900
V7+(V6-V7)×
1000
V7+(V6-V7)×
1100
V7+(V6-V7)×
1200
V7+(V6-V7)×
1300
V7+(V6-V7)×
1400
V7+(V6-V7)×
1500
V7+(V6-V7)×
1600
V6+(V5-V6)×
1700
V6+(V5-V6)×
1800
V6+(V5-V6)×
1900
V6+(V5-V6)×
2000
V6+(V5-V6)×
2100
V6+(V5-V6)×
2250
V6+(V5-V6)×
2400
V6
V6+(V5-V6)×
200
V6+(V5-V6)×
400
V6+(V5-V6)×
650
V6+(V5-V6)×
900
V6+(V5-V6)×
1200
V6+(V5-V6)×
1700
V5
Data Sheet S13944EJ2V0DS00
/
/
/
/
/
/
/
5100
5100
5100
5100
5100
5100
5100
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
5700
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
2550
/
/
/
/
/
/
2500
2500
2500
2500
2500
2500
rn(Ω)
r0
800
r1
750
r2
700
r3
650
r4
600
r5
550
r6
550
r7
500
r8
500
r9
400
r10 400
r11 350
r12 350
r13 350
r14 300
r15 300
r16 300
r17 250
r18 250
r19 250
r20 200
r21 200
r22 200
r23 150
r24 150
r25 150
r26 150
r27 100
r28 100
r29 100
r30 100
r31 100
r32 100
r33 100
r34 100
r35 100
r36 100
r37 100
r38 100
r39 100
r40 100
r41 100
r42 100
r43 100
r44 100
r45 100
r46 100
r47 100
r48 100
r49 100
r50 100
r51 100
r52 100
r53 150
r54 150
r55 150
r56 200
r57 200
r58 250
r59 250
r60 300
r61 500
r62 800
rtotal 15850
7
µ PD16715A
6. RELATIONSHIP BETWEEN OUTPUT DATA AND D/A CONVERTER
Data format : 6 bits × 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
R,/L = H (Right shift)
Output
S1
S2
S3
S4
xxx
S383
S384
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
xxx
D40 to D45
D50 to D55
R,/L = L (Left shift)
Output
S1
S2
S3
S4
xxx
S383
S384
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
xxx
D40 to D45
D50 to D55
POL
S2n–1
Note
Note
S2n
L
V0 to V4
V5 to V9
H
V5 to V9
V0 to V4
Note S2n-1 (Odd output), S2n (Even output), n = 1,2,⋅⋅⋅,192
7. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S2n–1
Selected voltage of V0 to V4
Selected voltage of V0 to V4
Selected Voltage of V5 to V9
S2n
Selected Voltage of V5 to V9
Hi-Z
8
Selected voltage of V0 to V4
Hi-Z
Data Sheet S13944EJ2V0DS00
Selected Voltage of V5 to V9
Hi-Z
µ PD16715A
8. RELATIONSHIP BETWEEN OUTPUT DATA AND D/A CONVERTER
The µPD16715A is a dot inversion and inverts dots by alternately using a charging output buffer and a discharging
output buffer. Therefore, the output voltage of the first line may not be correctly written because the last line’s output
polarity of frame n (n + 1) and the first line’s output polarity are the same (refer to Figure 8-1).
Consequently, polarity inversion and write operation must be performed between frames (vertical blanking period)
in order to invert (clear) the polarity of the wiring level of the liquid crystal panel by using the last line output of the
previous frame (refer to Figure 8-2).
Figure 8-1. Incase of the output voltage may not be correctly written
,,,
,,,
,,,
,,,
,,,
,,,
Vertical blanking period
Last line of frame n
STB
First line of frame
(n + 1)
Second line of frame
(n + 1)
Charging output
buffer
Discharging output
buffer
POL
S2N
Hi-Z
VCOM
Hi-Z
Hi-Z
If the write voltage of the first line of the last (n + 1) frame is greater than the
write voltage of
the last line of frame n, the targeted voltage cannot be correctly written with the
Figure 8-2. Polarity inversion and write operation
,,,
,,,
,,,
,,,
,,,
,,,
,,,
Vertical blanking period
Last line of frame n
STB
POL
S2N
Hi-Z
Hi-Z
First line of frame
(n + 1)
Hi-Z
Second line of frame
(n + 1)
VCOM
Hi-Z
Because data of negative polarity is to be written on the first line of
frame (n + 1),
Data Sheet S13944EJ2V0DS00
9
µ PD16715A
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Ratings
Unit
Logic Part Supply Voltage
VDD1
–0.3 to + 6.5
V
Driver Part Supply Voltage
VDD2
–0.5 to + 15.0
V
Logic Part Input Voltage
VI1
–0.3 to VDD1 + 0.3
V
Driver Part Input Voltage
VI2
–0.3 to VDD2 + 0.3
V
Logic Part Output Voltage
VO1
–0.3 to VDD1 + 0.3
V
Driver Part Output Voltage
VO2
–0.3 to VDD2 + 0.3
V
Operating Ambient Temperature
TA
–10 to +75
°C
Storage Temperature
Tstg
–55 to +125
°C
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily,
the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values
exceeding which the product may be physically damaged. Be sure to use the product within the
range of the absolute maximum ratings.
Recommended Operating Range (TA = –10 to +75 °C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Logic Supply Voltage
VDD1
3.0
3.3
3.6
V
Driver Supply Voltage
VDD2
9.0
11.0
13.5
V
High-Level Input Voltage
VIH
0.7 VDD1
VDD1
V
Low-Level Input Voltage
VIL
0
0.3 VDD1
V
V0 to V9
VSS2 + 0.1
VDD2 − 0.1
V
Driver Part Output Voltage
VO
VSS2 + 0.1
VDD2 − 0.1
V
Clock Frequency
fCLK
55
MHz
γ -Corrected Voltage
10
Data Sheet S13944EJ2V0DS00
µ PD16715A
+2.5
–2.0 V,
Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 11.0 V
Parameter
Input Leak Current
•
Symbol
Condition
VOH
STHR (STHL), IOH = 0 mA
Low-Level Output Voltage
VOL
STHR (STHL), IOL = 0 mA
Driver Output Current
TYP.
IIL
High-Level Output Voltage
γ -Corrected Supply Current
VSS1 = VSS2 = 0 V)
MIN.
Iγ
VDD1 − 0.1
VDD2 = 13 V,
V0 pin, V5 pin
V0 to V4 = V5 to V9 = 6.0 V
V4 pin, V9 pin
0.31
–0.8
MAX.
Unit
±1.0
µA
VDD1
V
0.1
V
0.8
mA
–0.31
mA
IVOH
VX = 8.0 V, VOUT = 6.0 V
–0.25
IVOL
VX = 1.0 V, VOUT = 3.0 V
Output Voltage Deviation
∆VO
Input data
Average Output Voltage
Variation
∆VAV
Input data
Output Voltage Range
VO
Input data
Logic Part Dynamic Current
Consumption
IDD1
VDD1 = 3.6 V, TA = 25°C
1.5
8
mA
Driver Part Dynamic Current
Consumption
IDD2
VDD1 = 3.0 V, VDD2 = 13.5 V, No loads,
3.5
8
mA
0.25
mA
mA
±20
±10
VDD2 +0.1
mV
mV
VDD2 – 0.1
V
TA = 25°C
Cautions 1. The output voltage deviation refers to the voltage difference between adjoining output pins when
the display data is the same (within the chip).
2. The average output voltage variation refers to the average output voltage difference between
chips. The average output voltage refers to the average voltage between chips when the
display data is the same.
3. The STB cycle is defined to be 20 µ s at fCLK = 33 MHz.
4. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the
measured values in the dot checkerboard input pattern.
5. Refers to the current consumption per driver when cascades are connected under the
assumption of XGA single-sided mounting (8 units).
Switching Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 11.0 V
Parameter
Symbol
Condition
+2.5
–2.0 V,
MIN.
VSS1 = VSS2 = 0 V)
TYP.
MAX.
Unit
Start Pulse Delay Time
tPLH1
CL = 25 pF
9.1
14
ns
Driver Output Delay Time
tPLH2
CL = 50 pF, RL = 50 kΩ
5.2
11
µs
tPLH3
9.9
17
µs
tPHL2
5.3
11
µs
tPHL3
10.4
17
µs
Input Capacitance
CI1
STHR (STHL) excluded, TA = 25°C
5.8
15
pF
CI2
STHR (STHL),TA = 25°C
5.7
15
pF
Data Sheet S13944EJ2V0DS00
11
µ PD16715A
Timing Requirement (TA = –10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter
Clock Pulse Width
Symbol
Condition
MIN.
TYP.
MAX.
Unit
PWCLK
18
ns
Clock Pulse High Period
PWCLK(H)
5
ns
Clock Pulse Low Period
PWCLK(L)
5
ns
Data Setup Time
tSETUP1
0
ns
Data Hold Time
tHOLD1
8
ns
Start Pulse Setup Time
tSETUP2
4
ns
Start Pulse Hold Time
tHOLD2
5
ns
POL2 Setup Time
tSETUP3
0
ns
POL2 Hold Time
tHOLD3
8
ns
STB Pulse Width
PWSTB
500
ns
Data Invalid Period
tINV
1
CLK
Last Data Timing
tLDT
2
CLK
CLK-STB Time
tCLK-STB
CLK ↑ → STB ↑
5
ns
STB-CLK Time
tSTB-CLK
STB ↑ → CLK ↑
5
ns
Time Between STB and Start
Pulse
tSTB-STH
STB ↑ → STHR(STHL) ↑
50
ns
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–7
ns
STB-POL Time
tSTB-POL
STB ↓ → POL ↓ or ↑
9
ns
12
Data Sheet S13944EJ2V0DS00
•
tr
2
1
CLK
t SETUP2
2
3
64
65
66
1025
1026
10%
t CLK-STB
t HOLD2
t STB-CLK
VSS1
t SETUP1
INVALID
D1 - D6
t HOLD1
D7 - D12
t SETUP3
POL2
VSS1
VDD1
STHR
(1st Dr.)
Dn0 - Dn5
tf
VDD1
90%
t STB-STH
D373 D378
D379 D384
D385 D390
VDD1
D3067 D3072
INVALID
D1 - D6
D7 - D12
VSS1
t HOLD3
VDD1
INVALID
INVALID
Data Sheet S13944EJ2V0DS00
VSS1
t PLH1
VDD1
STHL
(1st Dr.)
VSS1
t LDT
t INV
PWSTB
VDD1
STB
VSS1
t POL-STB
t STB-POL
VDD1
POL
VSS1
Hi-Z
(Unless otherwise specified, the input level is defined to be VIH =0.5 VDD1.)
1
9. SWITCHING CHARACTERISTICS WAVEFORM (R,/L = H)
PWCLK(L) PWCLK PWCLK(H)
t PLH3
t PLH2
t PHL2
t PHL3
13
µ PD16715A
Target Voltage ±0.1VDD2
6-bit accuracy
V out
µ PD16715A
7. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the µPD16715A.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
Type of Surface Mount Device
××× : TCP (TAB package)
µPD16715AN-×××
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C, heating for 2 to 3 seconds: pressure 100g
(per solder)
ACF
(Adhesive
Conductive Film)
2
Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm : time 3 to 5
seconds.
2
Real bonding 165 to 180°C: pressure 25 to 45 kg/cm : time 30 to 40
seconds. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more packaging methods at a time.
14
Data Sheet S13944EJ2V0DS00
µ PD16715A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S13944EJ2V0DS00
15
µ PD16715A
Reference Documents
NEC Semiconductor Device Reliability / Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8