Preliminary
NJU6010
24 keys input key-scan IC
! GENERAL DESCRIPTION
! PACKAGE OUTLINE
The NJU6010 is 24 keys input key-scan IC with internal
oscillation.
It scans the maximum 4x6 key matrix. And the key data
transmit to CPU.
The microprocessor interface circuits that operate
2MHz(Max.) frequency, can be connected directly to serial
microprocessor.
NJU6010
! FEATURES
#
#
#
#
#
#
#
Key-scan Function (Maximum matrix 4 x 6 = 24-key)
Serial Data Transmission (Shift Clock 2MHz max.)
Oscillation Circuit On-chip
Power On Reset Function
Operating Voltage
2.4 to 5.5V
C-MOS Technology
P-Sub
Package Outline
SSOP16
! BLOCK DIAGRAM
K0~K5
S0~S3
VDD
Key-scan circuit
VSS
OSC
Circuit
TEST
Key register
DATA
Serial
I/F
CSb
SCL
Power ON Reset
Circuit
•
SSOP16
TEST
CSb
SCL
DATA
S0
S1
S2
S3
Ver.2009-08-20
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
K0
K1
K2
K3
K4
K5
VSS
-1-
NJU6010
!
Preliminary
TERMINAL DESCRIPTION
No.
SYMBOL
1
TEST
Oscillation Circuit Test Terminal
2
CSb
Data output is available by "L".
3
SCL
4
DATA
5~8
S0 ~ S3
Serial Clock Input Terminal
Serial Data Output Terminal (This terminal outputs both the serial data
and REQ signals.)
CSb=”H” : Request signal output, CSb=”L” : Key data output
Key Scanning Output Terminals
9
VSS
10 ~ 15
K0 ~ K5
16
VDD
FUNCTION
GND Terminal
Key Scanning Input Terminals
Power Source Terminal
! FUNCTIONAL DESCRIPTION
(1) Description for Each Blocks
•
Serial I/F
The Serial I/F operates control of output signal.
•
•
Power ON Reset Circuit
The Power ON Reset Circuit initializes the key register automatically at Power ON.
Key-scan Circuit
When the key pressed, the Key-scan Circuit output the request signal from DATA terminal. The key data is
kept in the key register until CPU starts reading key data.
•
Key Register
The Key Register keeps the read key data.
•
Oscillation Circuit
The oscillation circuit is built-in.
(2) Key-scan Circuit
The Key-scan Circuit consists of a detector block of key pressing (S0~S3) and a fetching block of key
status (K0~K5). The Key-scan Circuit connects the 4x6 key-matrix and reads the data of 24 keys
maximum as shown in Fig1. Furthermore, it operates correctly against the multiple key inputs.
(Conditional)
NJU6010
K5 K4 K3 K2 K1 K0
S3 S2 S1 S0
ON
OFF
SW
KEY
Fig. 1 Key-scan Matrix
-2-
Ver.2009-08-20
Preliminary
NJU6010
(2-1) Timing of Key-scan
The key-scan cycle is 512 x T[s] (T=1/fosc). The key data is detected by executing key-scan operation
of 2 times. This operation prevents the miss-recognition. (Refer to Fig. 2)
The key-scan operation is available by status of CSb=”H”. The key-scan operation is not executed at
status of CSb=”L”.
If the key data of 2-time is same, the NJU6010 recognizes that the key was pressed. Then, the DATA
terminal outputs “H” as request (REQ signal) to CPU after 1408 x T[s] maximum from key input. When the
DATA terminal outputs "H", the key data is kept in the internal register until CPU starts reading key data.
The key-scan is not executed until reading the key data finishes.
Key input
Key recognition
Key-scan start
Key data fixed
REQ signal output
Key input
fosc (Internal osc.)
128×T[s]
Key-scan clock
(Internal signal)
S0
0
0
T=1/fosc
S1
S2
1
1
2
S3
3
1st key-scan
DATA
2
3
2nd key-scan
512×T[s]
Maximum1408×
×T[s]
Fig. 2 Key-scan Timing
Ver.2009-08-20
-3-
NJU6010
Preliminary
(2-2) Method of Checking the key
The method of checking the key judges the key pressed by fetching the key scanning output signal
(S0~S3) with terminal K0~K5 (Refer to Fig. 2). S0~S3 are fixed at "L" level usually. K0~K5 are input
terminals in the state of the pull-up.
When the key between S1 and K0 is pressed as an example, the K0 is changed from "H" to "L" (Refer
to Fig. 3). NJU6010 detects the pressed key by the change in this K0 signal. And which key was pressed
is checked, the key-scan signal is output from S0~S3 (Refer to Fig. 4).
The scan signal of S1 is input to the terminal K0 by this scan operation (Dot-line in Fig. 3). As a result,
NJU6010 is checked as the key was pressed between S1 and K0.
NJU6010
K5 K4 K3 K2 K1 K0
S3 S2 S1 S0
ON
OFF
SW
KEY
Fig. 3 Key-scan Checking (Example 1)
Key data fixed
Key input
Key-scan
KEY
K0
1
1
K1~K5
Key checking
(Pull-up)
S0
S1
S2
S3
0
0
1
1
2
2
3
3
DATA
CSb
Fig. 4 Key-scan Checking (Example 2)
-4-
Ver.2009-08-20
Preliminary
NJU6010
(2-3) Example of Key-scan Data Output
When CSb="L", the key data is output in order of "dummy → KD1~KD24 → dummy" from DATA
terminal by the falling edge of SCL (Refer to Fig. 5). Therefore, the key data reading with CPU is fetched
by the rising edge of SCL. When the CSb is falling edge, NJU6010 reads the key data regardless of the
state of SCL ("H" or "L") (Refer to Fig. 5 (1) (2)). In case of (1), the 1st dummy data is not read with CPU.
In case of (2), it is necessary to read the 1st dummy data. Therefore, the setting to read the dummy data
with CPU is necessary.
The key data is output as 24-bit of KD1~KD24. The bit corresponding to the pressed key is output as
"H", and the other bits are output as "L". (Refer to (2-4) The Relation Between Key Matrix and Key Data.)
When the CSb="H", NJU6010 outputs the key data reading request as becoming the DATA="H" (REQ
flag). After this REQ flag is checked, the key data requires reading. In case of reading the key data in the
state of the CSb="H" and DATA="L", the unexpected data is output.
After finished reading of the key data in CPU, read-out of key data is released by CSb="H", and
NJU6010 waits for the next key input. When the CSb="H" before reading 24 bits of all the key data, the
key data in a register is lost, a REQ flag is also released, and NJU6010 waits for the next key input.
(1) In case of SCL=”H”
CSb
SCL
DATA REQ
*
KD1
KD2
KD3
KD21
KD22
KD23
KD24
*
* : Dummy data
This dummy data cannot be read in CPU.
(2) In case of SCL=”L”
CSb
SCL
DATA REQ
*
KD1
KD2
KD3
KD21
KD22
KD23
KD24
*
* : Dummy data
This dummy data cannot be read in CPU.
Fig. 5 Key Data Transfer Timing
Ver.2009-08-20
-5-
NJU6010
Preliminary
(2-4) The Relation Between Key Matrix and Key Data
The relation between key matrix and key data is shown in Fig. 6.
NJU6010
K5 K4 K3 K2 K1 K0
S3 S2 S1 S0
ON
OFF
SW
K0
K1
K2
K3
K4
K5
S0
KD1
KD2
KD3
KD4
KD5
KD6
S1
KD7
KD8
KD9
KD10
KD11
KD12
S2
KD13
KD14
KD15
KD16
KD17
KD18
S3
KD19
KD20
KD21
KD22
KD23
KD24
KEY
Fig. 6 Relation Between Key Matrix and Key Data
(2-5) The Relation Between Key Matrix and Key Data
No-pressed key data may change pressed key data in triple or more key input as shown in Fig. 7, and
incorrect key data may be output to external CPU. For prevention of miss-recognition by incorrect key
data, diodes should be inserted in front of keys as shown in Fig. 8 or control program of CPU should
ignore the combination of key data miss-recognition.
In case of the key input as shown in Fig. 9, the recognition of multiple key inputs is realized without a
diode.
In case of 3 keys operation in left
picture, if S3 terminal outputs "L" signal,
this signal goes around on the dotted
line
and
no-pressed
key
is
miss-recognized as pressed key.
NJU6010
NJU6541
K5
K0
K6 K4
K5 K3
K4 K2
K3 K1
K2 K1
S5 S3
S4 S2
S3 S1
S2 S0
S1
Pressed key
Miss-recognized key
SW
KEY
Fig. 7 Multiple Key Inputs
-6-
Ver.2009-08-20
Preliminary
NJU6010
NJU6541
K5 K5
K4 K4
K3 K3
K2 K2
K1 K0
K6
K1
S3 S2 S3 S2
S1 S0
S1
Pressed key
NJU6010
In order to prevent miss-recognition of
Fig. 7, a diode is inserted as shown in
the left picture.
As a result, the miss-recognition route
of Fig. 7 is improved and the exact key
recognition is realized.
Recognition route
SW
KEY
Fig. 8 Example of Connection for Miss-recognition Prevention Diodes at Fig. 7
NJU6010
NJU6541
K5 K5
K4 K4
K3 K3
K2 K2
K1 K0
K6
K1
NJU6010
NJU6541
S3 S3
S2 S2
S1 S0
S5 S4
S1
K5 K5
K4 K4
K3 K3
K2 K1
K0
K2 K1
K6
S3 S3
S2 S1
S5 S4
S2 S0
S1
Pressed key
Pressed key
SW
KEY
(a)
SW
(b)
NJU6010
NJU6541
K5 K5
K4 K4
K3 K3
K2 K2
K1 K0
K6
K1
S3 S3
S2 S2
S1 S1
S0
S5 S4
Pressed key
SW
KEY
(c)
Fig. 9 Recognized multiple key inputs pattern
Ver.2009-08-20
-7-
KEY
NJU6010
Preliminary
(2-6) Example of Key-scan Operating
Example of key-scan operating is shown in Fig. 10.
(1) Normal key-scan
The key input is detected and the key-scan starts. After checking the key data, the DATA becomes "H"
(REQ flag).
After a REQ flag becomes effective even if the key is input, the key-scan is not executed.
The key data is read by CSb="L", and the read-out of key data is released by CSb="H".
(2) The key-scan after the key data reading is released (CSb=”H”)
When the key input continues after reading the key data finishes, NJU6010 executes the key-scan
again.
(3) The key-scan as CSb="L”
When the CSb="L", the key-scan is not working even if there is no REQ flag.
The key-scan is effective at the CSb="H" and state of no REQ flag.
(4) Unexpected data
When the key data is read without REQ flag, the key data is unexpected data.
End of key data transfer
End of key data transfer
Key data read request
Key data read request
End of key data transfer
Key data read request
Key input
Key-scan
1 2 3 4 1 2 3 4
S S S S S S S S
1 2 3 4 1 2 3 4
S S S S S S S S
CSb
SCL
REQ
DATA
Key data fetching
(1)
REQ
Key data transfer
Key data fetching
Unexpected data
Key data transfer
(2)
(3)
(4)
Fig. 10 Example of Key-scan Operating
-8-
Ver.2009-08-20
Preliminary
!
NJU6010
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER
SYMBOL
RATINGS
UNIT
CONDITION
-0.3 ~ +7.0
Supply Voltage
VDD
V
-0.3 ~ VDD+0.3
V
CSb, SCL, TEST terminals
Input Voltage
VIN1
Operating
-40 ~ +105
Topr
°C
Temperature
Storage
-55 ~ +125
Tstg
°C
Temperature
Power
300
PD
mW
Dissipation
Note 1) If the LSI is used on condition above the absolute maximum ratings, the LSI may be destroyed. Using
the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the
electric characteristics conditions will cause malfunction and poor reliability.
Note 2) All voltage values are specified as VSS = 0V.
Ver.2009-08-20
-9-
NJU6010
Preliminary
! ELECTRICAL CHARACTERISTICS
•
DC Characteristics 1
(VDD=2.4~3.6V, VSS=0V, Ta=-40~+105°C)
PARAMETER
Power Supply
"H" Level Input Voltage (1)
"L" Level Input Voltage (1)
"H" Level Input Voltage (2)
"L" Level Input Voltage (2)
Hysteresis Voltage
SYMBOL
VDD
VIH1
VIL1
VIH2
VIL2
VH
"H" Level Input Current
IIH
"L" Level Input Current
IIL
"H" Level Output Voltage (1)
"L” Level Output Voltage (1)
"H" Level Output Voltage (2)
"L" Level Output Voltage (2)
Pull-up Resistance Current
Oscillating Frequency
Operating Current
•
VOH1
VOL1
VOH2
VOL2
Ip
fosc
IDD
CONDITIONS
CSb, SCL, TEST
CSb, SCL, TEST
K0~K5
K0~K5
CSb, SCL
VIN=VDD
CSb, SCL
VIN=VSS
CSb, SCL
IO=-10uA, VDD=3.0V, S0~S3
IO=+250uA, VDD=3.0V, S0~S3
DATA, IO=1mA, VDD=3.0V
DATA, IO=-1mA, VDD=3.0V
VDD=3.0V, VIN=VDD, K0~K5
MIN
TYP
2.4
0.8VDD
0
0.8VDD
0
MAX
UNIT
3.6
VDD
0.2VDD
VDD
0.2VDD
V
V
V
V
V
V
1.0
uA
1.0
uA
VDD
0.2VDD
0.2VDD
0.8VDD
VSS
2
-5
35
VDD=3V,
Ta=25°C
-15
60
0.5
-25
100
V
V
V
V
uA
kHz
20
40
uA
NO
TE
DC Characteristics 2
(VDD=4.5~5.5V, VSS=0V, Ta=-40~+105°C)
PARAMETER
Power Supply
"H" Level Input Voltage (1)
"L" Level Input Voltage (1)
"H" Level Input Voltage (2)
"L" Level Input Voltage (2)
Hysteresis Voltage
SYMBOL
VDD
VIH1
VIL1
VIH2
VIL2
VH
"H" Level Input Current
IIH
"L" Level Input Current
IIL
"H" Level Output Voltage (1)
"L” Level Output Voltage (1)
"H" Level Output Voltage (2)
"L" Level Output Voltage (2)
Pull-up Resistance Current
Oscillating Frequency
Operating Current
- 10 -
VOH1
VOL1
VOH2
VOL2
Ip
fosc
IDD
CONDITIONS
CSb, SCL, TEST
CSb, SCL, TEST
K0~K5
K0~K5
CSb, SCL
VIN=VDD
CSb, SCL
VIN=VSS
CSb, SCL
IO=-20uA, VDD=5.0V, S0~S3
IO=+500uA, VDD=5.0V, S0~S3
DATA, IO=1mA, VDD=5.0V
DATA, IO=-1mA, VDD=5.0V
VDD=5.0V, VIN=VDD, K0~K5
VDD=5V,
Ta=25°C
MIN
TYP
4.5
0.8VDD
0
0.8VDD
0
MAX
UNIT
5.5
VDD
0.2VDD
VDD
0.2VDD
V
V
V
V
V
V
1.0
uA
1.0
uA
VDD
0.2VDD
0.2VDD
0.8VDD
VSS
4
-10
35
-25
60
0.5
-65
100
V
V
V
V
uA
kHz
45
80
uA
Ver.2009-08-20
NO
TE
Preliminary
•
NJU6010
AC Characteristics 1
(VDD=2.4~3.6V, VSS=0V, Ta=-40~+105°C)
PARAMETER
"L" Level Clock Pulse Width
"H" Level Clock Pulse Width
CSb Wait Time
CSb Set-up Time
CSb Hold Time
Rise Time
Fall Time
Key Data Output Delay Time
•
CONDITIONS
SYMBOL
tWCLL
tWCLH
tCP
tCS
tCH
tr
tf
tKDD
MIN
TYP
MAX
UNIT
20
20
230
ns
ns
ns
ns
ns
ns
ns
ns
260
260
50
180
100
DATA terminal, CL=50pF
NOTE
3
AC Characteristics 2
(VDD=4.5~5.5V, VSS=0V, Ta=-40~+105°C)
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
NOTE
"L" Level Clock Pulse Width
tWCLL
230
ns
"H" Level Clock Pulse Width
tWCLH
230
ns
CSb Wait Time
tCP
50
ns
3
CSb Set-up Time
tCS
180
ns
ns
CSb Hold Time
tCH
100
Rise Time
tr
20
ns
Fall Time
tf
20
ns
ns
DATA terminal, CL=50pF
Key Data Output Delay Time
tKDD
200
Note 3) tCP is the time when SCL is kept at “H” during CSb changed from “H” to “L”. When SCL is “L”, this
specification is not applied.
•
Output Timing
CSb
tCP tCS
tWCLH tWCLL
tf
tr
tCH
SCL
tKDD
DATA
Ver.2009-08-20
- 11 -
Preliminary
NJU6010
•
Power supply condition when hardware reset circuit is used
PARAMETER
Power-on Rising Time
Power-off Time
SYMBOL
trDD
tOFF
CONDITIONS
MIN
0.1
1
TYP
(Ta=-40~105°C)
MAX
UNIT
5
ms
ms
2.2V
VDD
0.2V
0.2V
trDD
0.2V
tOFF
Note 4) tOFF is the off time when power-supply turns off suddenly or cycles on/off.
- 12 -
Ver.2009-08-20
Preliminary
NJU6010
Input and Output terminal structure
VDD
VDD
IN
OUT
VSS
VSS
CSb, SCL, TEST
DATA
VDD
VDD
IN
OUT
VSS
S0~S3
VDD
VSS
K0~K5
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2009-08-20
- 13 -