OKI ML9207-XXGP

OKI Semiconductor
ML9207-xx
FEDL9207-02
Issue Date: May 17, 2005
5 × 7 Dot Character × 24-Digit Display Controller/Driver with Character RAM
GENERAL DESCRIPTION
The ML9207-xx is a dot matrix vacuum fluorescent display tube controller driver IC which displays characters,
numerics and symbols.
Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller.
A display system is easily realized by internal ROM and RAM for character display.
The ML9207-xx has low power consumption since it is made by CMOS process technology.
-01 is available as a general-purpose code.
Custom codes are provided on customer's request.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
: 3.3 V ±10% or 5.0 V ±10%
Logic power supply (VDD)
Fluorescent display tube drive power supply (VDISP) : 3.3 V ±10% or 5.0 V ±10%
Fluorescent display tube drive power supply (VFL) : –20 to –60 V
VFD driver output current
(VFD driver output can be connected directly to the fluorescent display tube. No pull-down resistor is
required.)
• Segment driver (SEG1 to SEG35)
: –5.0 mA
(VFL = –60 V)
• Segment driver (AD1 to AD4)
: –10.0 mA
(VFL = –60 V)
• Grid driver (COM1 to COM24)
: –50.0 mA
(VFL = –60 V)
General output port output current
Output driver (P1 to P4)
: ±1.0 mA (VDD = 3.3 V±10%)
±2.0 mA (VDD = 5.0 V±10%)
Content of display
• CGROM
5 × 7 dots
: 240 types (character data)
• CGRAM
5 × 7 dots
: 16 types (character data)
• ADRAM
24 (display digit) × 4 bits (symbol data)
• DCRAM
24 (display digit) × 8 bits (register for character data display)
• General output port
4 bits (static operation)
Display control function
• Display digit
: 9 to 24 digits
• Display duty (brightness adjustment) : 0/1024 to 960/1024
• All lights ON/OFF
4 interfaces with microcontroller
: DA, CS, CP, RESET
1-byte instruction execution (excluding data write to RAM and Display duty set)
Built-in oscillation circuit
• Crystal oscillation or ceramic oscillation
Package options:
80-pin QFP package (QFP80-P-1414-0.65-K) (Product name : ML9207-xxGP)
80-pin QFP package (QFP80-P-1420-0.80-BK) (Product name : ML9207-xxGA)
xx indicates the code number.
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ML9207-xx
BLOCK DIAGRAM
VDISP
VDD
GND
VFL
DCRAM
24w × 8b
CGRAM
RESET
DA
CP
CS
SEG1
CGROM
240w × 35b
Segment
Driver
16w × 35b
8-bit
Shift
Register
SEG35
AD1
ADRAM
24w × 4b
AD
Driver
AD4
Address
Selector
Command
Decoder
Control
Circuit
Write
Address
Counter
Read
Address
Counter
P1
Port
Driver
P4
Digit
Control
Duty
Control
Timing
Timing
Generator1
Generator2
COM1
Grid
Driver
COM24
OSC0
OSC1
Oscillator
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ML9207-xx
SCHEMATIC DIAGRAM OF DRIVER OUTPUT CIRCUIT
VDISP
VDISP
OUTPUT
VFL
VFL
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ML9207-xx
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AD2
AD1
VDISP2
NC
VFL2
P4
P3
P2
P1
VDD
DA
CP
CS
RESET
OSC1
OSC0
GND
VFL1
COM24
COM23
PIN CONFIGURATION (TOP VIEW)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
VDISP1
COM1
COM2
AD3
AD4
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
NC: No connection
80-Pin Plastic QFP
(QFP80-P-1414-0.65-K)
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65 VFL1
66 GND
67 OSC0
68 OSC1
69 RESET
71 CP
70 CS
72 DA
73 VDD
74 P1
75 P2
76 P3
77 P4
2
64 COM24
63 COM23
3
62 COM22
4
61 COM21
5
60 COM20
6
59 COM19
7
8
58 COM18
57 COM17
1
9
56 COM16
10
55 COM15
11
12
54 COM14
53 COM13
13
52 COM12
14
51 COM11
15
16
50 COM10
49 COM9
17
48 COM8
18
47 COM7
19
46 COM6
20
21
45 COM5
44 COM4
22
43 COM3
23
42 COM2
41 COM1
SEG35 39
VDISP1 40
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
AD1
AD2
AD3
AD4
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
79 NC
78 VFL2
80 VDISP2
ML9207-xx
NC: No connection
80-Pin Plastic QFP
(QFP80-P-1420-0.80-BK)
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ML9207-xx
PIN DESCRIPTION
Pin
QFP-1 *
3 to 37
39 to 62
QFP-2*
5 to 39
Symbol
SEG1 to 35
41 to 64 COM1 to 24
Type
Connects to
Description
O
Fluorescent tube
anode electrode
Fluorescent display tube anode electrode drive
output. Directly connected to fluorescent display
tube and a pull-down resistor is not necessary.
IOH > –5.0 mA
O
Fluorescent tube
grid electrode
Fluorescent display tube grid electrode drive
output. Directly connected to fluorescent display
tube and a pull-down resistor is not necessary.
IOH > –50.0 mA
Fluorescent display tube anode electrode drive
output. Directly connected to fluorescent display
tube and a pull-down resistor is not necessary.
IOH > –10.0 mA
1, 2, 79,
80
1 to 4
AD1 to AD4
O
Fluorescent tube
anode electrode
72 to 75
74 to 77
P1 to P4
O
LED anode
electrode
General port output. Output of these pins in
static operation, so these pins can drive the
LED. IOH > –2.0 mA
71
73
VDD
38, 78
40, 80
VDISP1 to 2
64
66
GND
—
Power supply
63, 76
65, 78
VFL1 to 2
VDD-GND are power supplies for internal logic.
VDISP-VFL are power supplies for driving
fluorescent tubes. Use the same power supply
for VDD and VDISP.
70
72
DA
I
Microcontroller
Serial data input (positive logic). Input from LSB.
69
71
CP
I
Microcontroller
Shift clock input. Serial data is shifted on the
rising edge of CP.
68
70
CS
I
Microcontroller
67
69
RESET
l
Microcontroller
65
67
OSC0
I
Crystal or
ceramic
resonator
66
68
OSC1
O
Chip select input. Serial data transfer is disabled
when CS pin is "H" level.
Reset input.
"Low" initializes all the functions.
Initial status is as follows.
• Address of each RAM ... address "00"H
• Data of each RAM ......... Content is undefined
• Display digit .................. 24 digits
• Brightness adjustment .. 0/1024
• All lights ON or OFF ..... OFF mode
• All outputs .................... "Low" level
Pins for self-oscillation.
(Do not apply external clocks to these pins.)
Connect these pins to the crystal and capacitors
or to the ceramic resonator and capacitors.
The target oscillation frequency is 4.0 MHz.
(Note that the device includes the feed back
resistor of 1 MΩ)
See Application Circuit.
* QFP1 : QFP80-P-1414-0.65-K
QFP2 : QFP80-P-1420-0.80-BK
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ML9207-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage (1)
Symbol
Condition
Rating
Unit
VDD
*1
–0.3 to +6.5
V
VDISP
*1
–0.3 to +6.5
V
Supply Voltage (2)
VFL
—
–80 to VDISP+0.3
V
Input Voltage
VIN
—
–0.3 to VDD+0.3
V
Power Dissipation
Storage Temperature
Output Current
PD
Ta ≥ 25°C
QFP80-P-1414-0.65-K
637
QFP80-P-1420-0.80-BK
764
TSTG
—
–55 to +150
IO1
COM1 to COM24
–60 to 0.0
IO2
AD1 to AD4
–20 to 0.0
IO3
SEG1 to SEG35
–10 to 0.0
IO4
P1 to P4
–4.0 to +4.0
mW
°C
mA
*1: Use the same power supply for VDD and VDISP.
RECOMMENDED OPERATING CONDITIONS
When the power supply voltage is 5V (typ.)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Supply Voltage (1)
VDD, VDISP
—
4.5
5.0
5.5
V
Supply Voltage (2)
VFL
—
–60
—
–20
V
High Level Input Voltage
VIH
All input pins excluding OSC0 pin
0.7 VDD
—
—
V
Low Level Input Voltage
VIL
All input pins excluding OSC0 pin
—
—
0.3 VDD
V
CP Frequency
fC
—
—
—
2.0
MHz
fOSC
Self-oscillation
3.5
4.0
4.5
MHz
Frame Frequency
fFR
DIGIT = 1 to 24, Self-oscillation
142
163
183
Hz
Operating Temperature
TOP
—
–40
—
+85
°C
Oscillation Frequency
When the power supply voltage is 3.3V (typ.)
Symbol
Condition
Min.
Typ .
Max.
Unit
Supply Voltage (1)
Parameter
VDD, VDISP
—
3.0
3.3
3.6
V
Supply Voltage (2)
VFL
—
–60
—
–20
V
High Level Input Voltage
VIH
All input pins excluding OSC0 pin
0.8 VDD
—
—
V
Low Level Input Voltage
VIL
All input pins excluding OSC0 pin
—
—
0.2 VDD
V
CP Frequency
fC
—
—
—
2.0
MHz
Oscillation Frequency
fOSC
Self-oscillation
3.5
4.0
4.5
MHz
Frame Frequency
fFR
DIGIT = 1 to 24, Self-oscillation
142
163
183
Hz
Operating Temperature
TOP
—
–40
—
+85
°C
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ML9207-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics-1
(VDD, VDISP = 5.0 V ±10%, VFL = –60V, Ta = –40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
Condition
Min.
Max.
Unit
High Level Input
Voltage
VIH
CS, CP, DA,
RESET
—
0.7 VDD
—
V
Low Level Input
Voltage
VIL
CS, CP, DA,
RESET
—
—
0.3 VDD
V
High Level Input
Current
IIH
CS, CP, DA,
RESET
VIH = VDD
–1.0
+1.0
µA
Low Level Input
Current
IIL
CS, CP, DA,
RESET
VIL = 0.0 V
–1.0
+1.0
µA
VOH1
COM1 to 24
IOH1 = –50.0 mA
VDISP
–2.0
—
V
VOH2
AD1 to AD4
IOH2 = –10.0 mA
VDISP
–1.5
—
V
VOH3
SEG1 to 35
lOH3 = –5.0 mA
VDISP
–1.5
—
V
VOH4
P1 to P4
IOH4 = –2.0 mA
VDD
–1.0
—
V
VOL1
COM1 to 24
AD1 to AD4
SEG1 to 35
—
—
VFL+1.0
V
VOL2
P1 to P4
IOL1 = 2 mA
High Level Output
Voltage
Low Level Output
Voltage
IDD1
VDD, VDISP
Supply Current
IDD2
fOSC=
4 MHz,
no load
—
1.0
V
Duty = 960/1024
Digit = 1 to 24
All output lights
ON
—
6
mA
Duty = 0/1024
Digit = 1 to 9
All output lights
OFF
—
5
mA
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ML9207-xx
DC Characteristics-2
(VDD, VDISP = 3.3 V ±10%, VFL = –60 V, Ta = –40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
Condition
Min.
Max.
Unit
High Level Input
Voltage
VIH
CS, CP, DA,
RESET
—
0.8 VDD
—
V
Low Level Input
Voltage
VIL
CS, CP, DA,
RESET
—
—
0.2 VDD
V
High Level Input
Current
IIH
CS, CP, DA,
RESET
VIH = VDD
–1.0
+1.0
µA
Low Level Input
Current
IIL
CS, CP, DA,
RESET
VIL = 0.0 V
–1.0
+1.0
µA
VOH1
COM1 to 24
IOH1 = –50.0 mA
VDISP
–2.0
—
V
VOH2
AD1 to AD4
IOH2 = –10.0 mA
VDISP
–1.5
—
V
VOH3
SEG1 to 35
IOH3 = –5.0 mA
VDISP
–1.5
—
V
VOH4
P1 to P4
IOH4 = –1.0 mA
VDD
–1.0
—
V
VOL1
COM1 to 24
AD1 to AD4
SEG1 to 35
—
—
VFL+1.0
V
VOL2
P1 to P4
IOL1 = 1 mA
—
1.0
V
Duty = 960/1024
Digit = 1 to 24
All output lights
ON
—
5
mA
Duty = 0/1024
Digit = 1 to 9
All output lights
OFF
—
4
mA
High Level Output
Voltage
Low Level Output
Voltage
IDD1
VDD, VDISP
Supply Current
IDD2
fOSC =
4 MHz,
no load
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ML9207-xx
AC Characteristics-1
(VDD, VDISP = 5.0 V ±10%, VFL = –60 V, Ta = –40 to +85°C, unless otherwise specified)
Parameter
CP Frequency
Symbol
Condition
Min.
Max.
Unit
fC
—
—
2.0
MHz
CP Pulse Width
tCW
—
250
—
ns
DA Setup Time
tDS
—
250
—
ns
DA Hold Time
tDH
—
250
—
ns
CS Setup Time
tCSS
—
250
—
ns
CS Hold Time
tCSH
Self-oscillation
16
—
µs
CS Wait Time
tCSW
—
250
—
ns
Data Processing Time
tDOFF
Self-oscillation
8
—
µs
RESET Pulse Width
tWRES
When RESET signal is input from
microcontroller, etc. externally
250
—
ns
RESET Time
tRSON
—
tOSCON
—
ns
DA Wait Time
tRSOFF
—
250
—
ns
—
2.0
µs
All Output Slew Rate
tR
CI = 100 pF
tR = 20% to 80%
tF = 80% to 20%
—
2.0
µs
OSC Duty Ratio
duOSC
—
40
60
%
Oscillation Start-up time
tOSCON
—
tF
*1
*1 tOSCON depends on the type of crystal or resonator.
Refer to characteristic data of crystal or resonator used.
AC Characteristics-2
(VDD, VDISP = 3.3 V ±10%, VFL = –60 V, Ta = –40 to +85°C, unless otherwise specified)
Parameter
CP Frequency
Symbol
Condition
Min.
Max.
Unit
fC
—
—
2.0
MHz
CP Pulse Width
tCW
—
250
—
ns
DA Setup Time
tDS
—
250
—
ns
DA Hold Time
tDH
—
250
—
ns
CS Setup Time
tCSS
—
250
—
ns
CS Hold Time
tCSH
Self-oscillation
16
—
µs
CS Wait Time
tCSW
—
250
—
ns
Data Processing Time
tDOFF
Self-oscillation
8
—
µs
RESET Pulse Width
tWRES
When RESET signal is input from
microcontroller, etc. externally
250
—
ns
RESET Time
tRSON
—
tOSCON
—
ns
DA Wait Time
tRSOFF
—
250
—
ns
—
2.0
µs
All Output Slew Rate
tR
CI = 100 pF
tR = 20% to 80%
tF = 80% to 20%
—
2.0
µs
OSC Duty Ratio
duOSC
—
40
60
%
Oscillation Start-up time
tOSCON
—
tF
*1
*1 tOSCON depends on the type of crystal or resonator.
Refer to characteristic data of crystal or resonator used.
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FEDL9207-02
OKI Semiconductor
ML9207-xx
TIMING DIAGRAM
VDD = 3.3 V ±10%
VDD = 5.0 V ±10%
VIH
0.8 VDD
0.7 VDD
VIL
0.2 VDD
0.3 VDD
Symbol
• Data Timing
tCSS
tCSW
CS
1/fC
tDOFF
CP
DA
tCSH
tCW tCW
VIH
VIL
tDH
tDS
VALID VALID
VIH
VIL
VIH
VIL
VALID VALID
• Reset Timing
0.8 VDD
0.0 V
VDD
tWRES
RESET
VIL
tRSOFF
DA
VIH
VIH
VIL
tRSON
• Output Timing
All outputs
t
tF
0.8 VDISP
0.2 VFL
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ML9207-xx
• Digit Output Timing (for 24-digit display, at a duty of 960/1024)
T=1/ fOSC
COM1
COM2
COM3
COM4
COM5
COM6
Frame cycle
Display timing
Blank timing
t1 = 24576T (t1 = 6.144 ms when fOSC = 4.0
t2 = 960T (t
MH
2 = )240 µs when fOSC = 4.0 MHz)
t3 = 64T
(t3 = 16 µs when fOSC = 4.0 MHz)
COM19
COM20
COM21
COM22
COM23
COM24
AD1-4
SEG1-35
VDISP
VFL
VDISP
VFL
• OSC Timing
1/fOSC
OSC1
0.5 VDD
A
B
DuOSC = A/(A+B) × 100
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ML9207-xx
FUNCTIONAL DESCRIPTION
Command List
Command
1
2
3
4
5
6
7
DCRAM data write
CGRAM data write
ADRAM data write
General output port
set
Display duty set
Number of digits
set
All lights ON/OFF
LSB
1st byte
MSB
LSB
2nd byte
MSB
B0
B1
B2
B3
B4
B5
B6
B7
B0
B1
B2
B3
B4
B5
B6
B7
X0
X1
X2
X3
X4
1
0
0
C0
C1
C2
C3
C4
C5
C6
C7
C0
C5
C10
C15
C20
C25
C30
*
2nd byte
C1
C6
C11
C16
C21
C26
C31
*
3rd byte
C2
C7
C12
C17
C22
C27
C32
*
4th byte
C3
C8
C13
C18
C23
C28
C33
*
C4
C9
C14
C19
C24
C29
C34
*
5th byte
6th byte
C0
C1
C2
C3
*
*
*
*
D2
D3
D4
D5
D6
D7
D8
D9
X0
X1
X2
X3
*
0
1
0
X0
X1
X2
X3
X4
1
1
0
P1
P2
P3
P4
*
0
0
1
D0
D1
*
*
*
1
0
1
K0
K1
K2
K3
*
0
1
1
L
H
*
*
*
1
1
1
Test mode
*
: Don't care
Xn
: Address specification for each RAM
Cn
: Character code specification for each RAM
Pn
: General output port status specification
Dn
: Display duty specification
Kn
: Number of digits specification
H
L
: All lights ON instruction
: All lights OFF instruction
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented
automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
Note :
The test mode is used for inspection before shipment.
This is not a user function.
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Positional Relationship Between SEGn and ADn (one digit)
C0 AD1
C1 AD2
ADRAM written data.
Corresponds to 2nd byte
C2 AD3
C3 AD4
C0
SEG1
C5
C1
SEG2
C6
C2
SEG3
C7
C3
SEG4
C8
C4
SEG5
C9
SEG6
SEG7
SEG8
SEG9
SEG10
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
SEG11 SEG12 SEG13 SEG14 SEG15
SEG16 SEG17 SEG18 SEG19 SEG20
SEG21 SEG22 SEG23 SEG24 SEG25
SEG26 SEG27 SEG28 SEG29 SEG30
SEG31 SEG32
CGRAM written data. Corresponds to 2nd byte
CGRAM written data. Corresponds to 3rd byte
CGRAM written data. Corresponds to 4th byte
SEG33 SEG34 SEG35
CGRAM written data. Corresponds to 6th byte
CGRAM written data. Corresponds to 5th byte
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Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to "Low" level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input
into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each
register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin changes from
"High" to "Low" is recognized in 8-bit units.
tDOFF
CS
tCSH
CP
DA
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
LSB
LSB
LSB
1st byte
MSB
When data is written to DCRAM* Command and address data
2nd byte
MSB
Character code data
2nd byte
MSB
Character code data of the
next address
* When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally
incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
Reset Function
Reset is executed when the RESET pin is set to "L", (when turning power on, for example) and initializes all
functions.
Initial status is as follows:
• Address of each RAM ......................................Address "00"H
• Data of each RAM............................................All contents are undefined
• General output port ..........................................All general output ports (P1 to P4) go "Low"
• Display digit.....................................................24 digits
• Brightness adjustment ......................................0/1024
• All display lights ON or OFF ...........................OFF mode
• Segment output ................................................All segment outputs (SEG1 to SEG35) go "Low"
• Common output................................................All common outputs (COM1 to COM24) go "Low"
• AD output ........................................................All AD outputs (AD1 to AD4) go "Low"
Please set the functions again according to "Setting Flowchart" after reset.
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Description of Commands and Functions
1. DCRAM data write
(Specifies the addresses 00H to 1FH of DCRAM and writes the character codes of CGROM and CGRAM.)
DCRAM (Data Control RAM) has a 5-bit address to store the character codes of CGROM and CGRAM.
The character code specified by DCRAM is converted to a 5 × 7 dot matrix character pattern via CGROM or
CGRAM.
(The DCRAM can store 24 characters.)
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3 X4 1
LSB
0
0
MSB
: Selects DCRAM data write mode and specifies DCRAM
address
(Ex: Specifies DCRAM address 00H.)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C1 C2 C3 C4 C5 C6 C7
: Specifies the character codes of CGROM and CGRAM
(written into DCRAM address 00H)
To specify the character code of CGROM and CGRAM continuously to the next address, specify only character
codes as follows.
The addresses of DCRAM are automatically incremented. Specification of an address is unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: Specifies the character codes of CGROM and CGRAM
(written into DCRAM address 01H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: Specifies the character codes of CGROM and CGRAM
(written into DCRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(25th)
C0 C1 C2 C3 C4 C5 C6 C7
: Specifies the character codes of CGROM and CGRAM
(written into DCRAM address 17H)
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The character code setting of CGROM and CGRAM up to 24 digits is completed.
To set a character code from DCRAM address 00H continuously.
Specify a dummy character code between DCRAM addresses 18H and 1FH.
(To increment the DCRAM address automatically and set it to 00H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(26th)
C0 C1 C2 C3 C4 C5 C6 C7
(Operated 8 times)
LSB
: Specifies the character codes of dummy CGROM
and CGRAM
(Not written into DCRAM address)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(33rd)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: Specifies the character codes of dummy CGROM
and CGRAM
(Not written into DCRAM address)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(34th)
C0 C1 C2 C3 C4 C5 C6 C7
: Specifies the character codes of CGROM and CGRAM
(DCRAM address 00H is rewritten)
X0 (LSB) to X4 (MSB): DCRAM addresses (5 bits: 24 characters)
C0 (LSB) to C7 (MSB): Character codes of CGROM and CGRAM (8 bits: 256 characters)
[COM positions and set DCRAM addresses]
HEX
X0
X1
X2
X3
X4
COM position
HEX
X0
X1
X2
X3
X4
COM position
00
0
0
0
0
0
COM1
10
0
0
0
0
1
COM17
01
1
0
0
0
0
COM2
11
1
0
0
0
1
COM18
02
0
1
0
0
0
COM3
12
0
1
0
0
1
COM19
03
1
1
0
0
0
COM4
13
1
1
0
0
1
COM20
04
0
0
1
0
0
COM5
14
0
0
1
0
1
COM21
05
1
0
1
0
0
COM6
15
1
0
1
0
1
COM22
06
0
1
1
0
0
COM7
16
0
1
1
0
1
COM23
07
1
1
1
0
0
COM8
17
1
1
1
0
1
COM24
08
0
0
0
1
0
COM9
18
0
0
0
1
1
Not fixed
09
1
0
0
1
0
COM10
19
1
0
0
1
1
Not fixed
0A
0
1
0
1
0
COM11
1A
0
1
0
1
1
Not fixed
0B
1
1
0
1
0
COM12
1B
1
1
0
1
1
Not fixed
0C
0
0
1
1
0
COM13
1C
0
0
1
1
1
Not fixed
0D
1
0
1
1
0
COM14
1D
1
0
1
1
1
Not fixed
0E
0
1
1
1
0
COM15
1E
0
1
1
1
1
Not fixed
0F
1
1
1
1
0
COM16
1F
1
1
1
1
1
Not fixed
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2. CGRAM data write
(Specifies the addresses of CGRAM and writes character pattern data.)
CGRAM (Character Generator RAM) has a 4-bit address to store 5 × 7 dot matrix character patterns.
A character pattern stored in CGRAM can be displayed by specifying the character code (address) by
DCRAM.
The address of CGRAM is assigned to 00H to 0FH. (All the other addresses are the CGROM addresses.)
(The CGRAM can store 16 types of character patterns.)
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3
*
0
1
LSB
0
MSB
: Selects CGRAM data write mode and specifies
CGRAM address.
(Ex: Specifies CGRAM address 00H.)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C5 C10C15C20 C25 C30
LSB
*
: Specifies 1st column data
(written into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte
(3rd)
C1 C6 C11 C16C21 C26 C31
LSB
*
: Specifies 2nd column data
(written into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
4th byte
(4th)
C2 C7 C12C17C22 C27 C32
LSB
*
: Specifies 3rd column data
(written into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
5th byte
(5th)
C3 C8 C13C18C23 C28 C33
LSB
*
: Specifies 4th column data
(written into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(6th)
C4 C9 C14C19C24 C29 C34
*
: Specifies 5th column data
(written into CGRAM address 00H)
To specify character pattern data continuously to the next address, specify only character pattern data as follows.
The addresses of CGRAM are automatically incremented. Specification of an address is therefore unnecessary.
The 2nd to 6th byte (character pattern data) are regarded as one data item, so 250 ns is sufficient for tDOFF time
between bytes.
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(7th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: Specifies 1st column data
(written into CGRAM address 01H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(11th)
C4 C9 C14 C19 C24 C29 C34
LSB
*
: Specifies 5th column data
(written into CGRAM address 01H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(12th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: Specifies 1st column data
(written into CGRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(16th)
C4 C9 C14 C19 C24 C29 C34
LSB
*
: Specifies 5th column data
(written into CGRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(77th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: Specifies 1st column data
(written into CGRAM address 0FH)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(81st)
C4 C9 C14 C19 C24 C29 C34
LSB
*
: Specifies 5th column data
(written into CGRAM address 0FH)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(82nd)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: Specifies 1st column data
(CGRAM address 00H is written)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(86th)
C4 C9 C14 C19 C24 C29 C34
X0 (LSB) to X3 (MSB)
C0 (LSB) to C34 (MSB)
*
*
: Specifies 5th column data
(CGRAM address 00H is written)
: CGRAM addresses (4 bits: 16 characters)
: Character pattern data (35 bits: 35 outputs per digit)
: Don't care
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[CGROM addresses and set CGRAM addresses]
Refer to ROMCODE table
HEX
X0
X1
X2
X3
CGROM address
HEX
X0
X1
X2
X3
CGROM address
00
0
0
0
0
RAM00(00000000B)
08
0
0
0
1
RAM08(00001000B)
01
1
0
0
0
RAM01(00000001B)
09
1
0
0
1
RAM09(00001001B)
02
0
1
0
0
RAM02(00000010B)
0A
0
1
0
1
RAM0A(00001010B)
03
1
1
0
0
RAM03(00000011B)
0B
1
1
0
1
RAM0B(00001011B)
04
0
0
1
0
RAM04(00000100B)
0C
0
0
1
1
RAM0C(00001100B)
05
1
0
1
0
RAM05(00000101B)
0D
1
0
1
1
RAM0D(00001101B)
06
0
1
1
0
RAM06(00000110B)
0E
0
1
1
1
RAM0E(00001110B)
07
1
1
1
0
RAM07(00000111B)
0F
1
1
1
1
RAM0F(00001111B)
Positional relationship between the output area of CGROM and that of CGRAM
Area that corresponds to 2nd byte (1st column)
Area that corresponds to 3rd byte (2nd column)
Note:
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15 C16
C17
C18
C19
C20 C21
C22
C23
C24
C25 C26
C27
C28
C29
C30 C31
C32
C33
C34
Area that corresponds to 6th byte (5th column)
Area that corresponds to 5th byte (4th column)
Area that corresponds to 4th byte (3rd column)
CGROM (Character Generator ROM) has an 8-bit address to generate 5 × 7 dot matrix character
patterns.
CGRAM can store 240 types of character patterns.
General-purpose code -01 is available and custom codes are provided on customer's request.
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3. ADRAM data write
(Specifies the addresses 00H to 1FH of ADRAM and writes symbol data.)
ADRAM (Additional Data RAM) has a 5-bit address to store symbol data.
Symbol data specified by ADRAM is directly output without CGROM and CGRAM.
(The ADRAM can store 4 types of symbol patterns for each digit.)
The terminal to which the contents of ADRAM are output can be used as a cursor.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3 X4 1
LSB
1
0
MSB
: Selects ADRAM data write mode and specifies ADRAM
address
(Ex: Specifies ADRAM address 00H.)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C1 C2 C3
* * * *
: Sets symbol data
(written into ADRAM address 00H.)
To specify symbol data continuously to the next address, specify only symbol data as follows.
The address of ADRAM is automatically incremented. Specification of addresses is therefore unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3
LSB
* * * *
MSB
: Sets symbol data
(written into ADRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
C0 C1 C2 C3
LSB
* * * *
: Sets symbol data
(written into ADRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(25th)
C0 C1 C2 C3
* * * *
: Sets symbol data
(written into ADRAM address 17H)
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The symbol data setting up to 24 digits is completed.
To set symbol data from ADRAM address 00H continuously.
Specify a dummy symbol data between ADRAM addresses 18H and 1FH.
(To increment the ADRAM address automatically and set it to 00H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(26th)
C0 C1 C2 C3
* * * *
LSB
: Sets dummy symbol data
(Not written into ADRAM address)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(33rd)
C0 C1 C2 C3
* * * *
LSB
: Sets dummy symbol data
(Not written into ADRAM address)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(34th)
C0 C1 C2 C3
* * * *
X0 (LSB) to X4 (MSB)
C0 (LSB) to C3 (MSB)
*
: Sets dummy symbol data
(ADRAM address 00H is rewritten)
: ADRAM addresses (5 bits: 24 characters)
: Symbol data (4 bits: 4-symbol data per digit)
: Don't care
[COM positions and ADRAM addresses]
HEX
X0
X1
X2
X3
X4
COM position
HEX
X0
X1
X2
X3
X4
COM position
00
0
0
0
0
0
COM1
10
0
0
0
0
1
COM17
01
1
0
0
0
0
COM2
11
1
0
0
0
1
COM18
02
0
1
0
0
0
COM3
12
0
1
0
0
1
COM19
03
1
1
0
0
0
COM4
13
1
1
0
0
1
COM20
04
0
0
1
0
0
COM5
14
0
0
1
0
1
COM21
05
1
0
1
0
0
COM6
15
1
0
1
0
1
COM22
06
0
1
1
0
0
COM7
16
0
1
1
0
1
COM23
07
1
1
1
0
0
COM8
17
1
1
1
0
1
COM24
08
0
0
0
1
0
COM9
18
0
0
0
1
1
Not fixed
09
1
0
0
1
0
COM10
19
1
0
0
1
1
Not fixed
0A
0
1
0
1
0
COM11
1A
0
1
0
1
1
Not fixed
0B
1
1
0
1
0
COM12
1B
1
1
0
1
1
Not fixed
0C
0
0
1
1
0
COM13
1C
0
0
1
1
1
Not fixed
0D
1
0
1
1
0
COM14
1D
1
0
1
1
1
Not fixed
0E
0
1
1
1
0
COM15
1E
0
1
1
1
1
Not fixed
0F
1
1
1
1
0
COM16
1F
1
1
1
1
1
Not fixed
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4. General output port set
(Specifies the general output port status.)
The general output port is an output for 4-bit static operation.
When the RESET signal is input, the general output ports go “Low”. (See “Reset Function”)
It is used to control other I/O devices and turn on LED. (static operation)
When at the "High" level, this output becomes the VDD voltage, and when at the "Low" level, it becomes the
ground potential. Therefore, the fluorescent display tube cannot be driven.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
P1 P2 P3 P4
*
0
0
1
: Selects a general output port and specifies
the output status
P1 to P4 : General output ports
*
: Don't care
[Set data and set state of general output port]
Pn
Display state of general output port
0
Sets the output to Low
1
Sets the output to High
(The state when RESET signal is input.)
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5. Display duty set
(Writes a display duty value to the duty cycle register.)
Display duty adjusts brightness in 960 stages (0/1024 to 960/1024) using 10-bit data.
When the RESET signal is input, the duty cycle register value is "0". (See "Reset Function") Always execute
this instruction before turning the display on, then set a desired duty value.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
D0 D1
*
* *
1
0
LSB
1
: Selects display duty set and sets duty value (low-order 2 bits).
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte D2 D3 D4 D5 D6 D7 D8 D9
(2nd)
D0 (LSB) to D9 (MSB)
*
: Sets duty value (high-order 8 bits).
: Display duty data (10 bits: 0/1024 to 960/1024 stages)
: Don't care
[Relation between setup data and controlled COM duty]
HEX
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
COM duty
000
0
0
0
0
0
0
0
0
0
0
0/1024
001
1
0
0
0
0
0
0
0
0
0
1/1024
002
0
1
0
0
0
0
0
0
0
0
2/1024
3BE
0
1
1
1
1
1
0
1
1
1
958/1024
3BF
1
1
1
1
1
1
0
1
1
1
959/1024
3C0
0
0
0
0
0
0
1
1
1
1
960/1024
3C1
1
0
0
0
0
0
1
1
1
1
960/1024
3FE
0
1
1
1
1
1
1
1
1
1
960/1024
3FF
1
1
1
1
1
1
1
1
1
1
960/1024
← (The state when
RESET signal is
input.)
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6. Number of digits set
(Writes the number of display digits to the display digit register.)
The number of digits set can display 9 to 24 digits using 4-bit data.
When the RESET signal is input, the number of digit register value is "0". (See “Reset Function”) Always
execute this instruction to change the number of digits before turning the display on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
K0 K1 K2 K3
*
0
K0 (LSB) to K3 (MSB)
*
1
1
: Selects the number of digit set mode and specifies
the number of digit value
: Number of digit data (4 bits: 16 digits)
: Don't care
[Relation between setup data and controlled COM]
HEX
K0
K1
K2
K3
Number of digits
of COM
HEX
K0
K1
K2
K3
Number of digits
of COM
0
0
0
0
0
COM1 to 24
8
0
0
0
1
COM1 to 16
1
1
0
0
0
COM1 to 9
9
1
0
0
1
COM1 to 17
2
0
1
0
0
COM1 to 10
A
0
1
0
1
COM1 to 18
3
1
1
0
0
COM1 to 11
B
1
1
0
1
COM1 to 19
4
0
0
1
0
COM1 to 12
C
0
0
1
1
COM1 to 20
5
1
0
1
0
COM1 to 13
D
1
0
1
1
COM1 to 21
6
0
1
1
0
COM1 to 14
E
0
1
1
1
COM1 to 22
7
1
1
1
0
COM1 to 15
F
1
1
1
1
COM1 to 23
* The state when RESET signal is input.
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7. All display lights ON/OFF set
(Turns all display lights ON or OFF.)
When the RESET signal is input, all segment, common and AD outputs go “Low”. (See “Reset Function”)
All display lights ON is used primarily for display testing.
All display lights OFF is primarily used for display blink and to prevent malfunction when power is turned on.
This command cannot control the general output port.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
L
H
* * *
1
1
1
L and H: Display operation data
*: Don't care
: Selects all display lights ON or OFF mode and
specifies display operation
[Set data and display state of SEG and AD]
L
H
Display state of SEG and AD
0
0
Normal display
1
0
Sets all outputs to Low
0
1
Sets all outputs to High
1
1
Sets all outputs to High
(The state when RESET signal is input.)
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Setting Flowchart
(Power applying included)
Apply VDD and VDISP
Apply VFL
All display lights OFF
Status of all outputs by RESET
signal input
General output port setting
Number of digits setting
Display duty setting
Select a RAM to be used
DCRAM
CGRAM
ADRAM
Data write mode
Data write mode
Data write mode
(with address setting)
(with address setting)
(with address setting)
Address is automatically
incremented
Address is automatically
incremented
DCRAM
Character code
NO
DCRAM
Is character code
write ended?
Address is automatically
incremented
ADRAM
Character code
CGRAM
Character code
NO
YES
CGRAM
Is character code
write ended?
YES
YES
NO
ADRAM
Is character code
write ended?
YES
Another RAM to
be set?
NO
Releases all display lights
OFF mode
Display operation mode
End
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ML9207-xx
Power-off Flowchart
Display operation mode
Turn off VFL
Turn off VDD and VDISP
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APPLICATION CIRCUIT
*1
Heater Transformer
5 × 7-dot matrix fluorescent display tube
ANODE
ANODE
GRID
(SEGMENT) (SEGMENT) (DIGIT)
VDD
4
VDD
VDD
C3
VDD, AD1-4
VDISP1-2
Microcontroller
Output Port
GND
RESET
CS
CP
DA
35
VDD
24
SEG1-35 COM1-24
R4
LED
ML9207 -xx
P1-4
GND VFL1-2
4
OSC0 OSC1
*2
VFL
C4
GND
*1
ZD
GND
*3
*1
R3
NPN Tr
GND
GND
Crystal or ceramic resonator
Notes: *1. The application circuit indicates a circuit by which fluorescent display tube filaments are ac driven
using a heater transformer. Contact fluorescent display tube manufacturers for the methods and
circuits of driving fluorescent display tube filaments.
*2. Keep the wires between the OSC0 pin and the crystal or ceramic resonator as short as possible to avoid
generating noise.
*3 For oscillation capacitor values, refer to data of the crystal or ceramic resonator used.
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REFERENCE DATA
Graphs illustrating the VFL versus driver output current capability relationship are shown below.
Care must be taken not to use the total power in excess of allowable power dissipation.
0
[Driver output current versus output drop voltage]
VFL = −60V, COMn
[Output current (mA)]
−15 −30 −45 −60 −75 (mA)
0
0
[VDISP−n(V)]
[VDISP−n(V)]
−0.5
−0.5
−1.0
Ta = −40°C
[Driver output current versus output drop voltage]
VFL = −20V, COMn
[Output current (mA)]
−15 −30 −45 −60 −75 (mA)
0
−1.0
Ta = 25°C
−1.5
−2.0
(V)
−2.0
(V)
0
[Driver output current versus output drop voltage]
VFL = −60V, ADn
[Output current (mA)]
0
−4
−8
−12 −16 −20 (mA)
0
[VDISP−n(V)]
[VDISP−n(V)]
−0.5
−0.5
−1.0
−1.5
Ta = −40°C
Ta = 25°C
[Driver output current versus output drop voltage]
VFL = −20V, ADn
[Output current (mA)]
0
−4
−8
−12 −16 −20 (mA)
−1.0
−2.0
(V)
[Driver output current versus output drop voltage]
VFL = −60V, SEGn
[Output current (mA)]
0
−2
−4
−6
−8
−10 (mA)
0
[VDISP−n(V)]
[VDISP−n(V)]
−0.5
−0.5
−1.0
Ta = 85°C Ta = 25°C
Ta = −40°C
−1.5
Ta = 85°C
−2.0
(V)
0
Ta = −40°C
−1.5
Ta = 85°C
Ta = −40°C
Ta = 85°C Ta = 25°C
[Driver output current versus output drop voltage]
VFL = −20V, SEGn
[Output current (mA)]
0
−2
−4
−6
−8
−10 (mA)
−1.0
Ta = 25°C
−1.5
− ٛ– 2.0
(V)
Ta = 85°C
Ta = −40°C
−1.5
−2.0
(V)
Ta = 85°C
Ta = 25°C
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ML9207-01 ROM CODE
00000000B (00H) to 00000111B (0FH) are the CGRAM addresses.
MSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
LSB
0000
RAM0
0001
RAM1
0010
RAM2
0011
RAM3
0100
RAM4
0101
RAM5
0110
RAM6
0111
RAM7
1000
RAM8
1001
RAM9
1010
RAMA
1011
RAMB
1100
RAMC
1101
RAMD
1110
RAME
1111
RAMF
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PACKAGE DIMENSIONS
(Unit: mm)
QFP80-P-1414-0.65-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.85 TYP.
3/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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(Unit: mm)
QFP80-P-1420-0.80-BK
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
1.27 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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REVISION HISTORY
Document
No.
FEDL9207-01
FEDL9207-02
Date
July 2000
Page
Previous Current
Edition
Edition
–
–
1
1
31
31
-
34
May 17, 2005
Description
Final edition 1
TITLE
15×7DotCharacter×16-DigitDisplay
Controller/Driver with Character RAM
↓
15×7DotCharacter×24-DigitDisplay
Controller/Driver with Character RAM
ROM CODE LSB 0001 MSB 0111
→
Added Revision History
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FEDL9207-02
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NOTICE
1.
The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2005 Oki Electric Industry Co., Ltd.
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