PT6302 VF FD Driverr/Controlller IC with Charac cter RAM D DESCR IPTION N PT T6302 is a dot d matrix VFD V Driver/C Controller IC utillizing CMOS S Technology y specially designed to dissplay characters, numerals, and symb bols. PT6302 pro ovides 35 dott matrix, 2 ad dditional segment drivers and d 16 grid drivers. 248 types of cha aracter data (CG GROM), 8 tyypes of chara acter data (C CGRAM), 16 dissplay digits x 2 bits symbol data, 16 disp play digits x 8 bitss register for character da ata display an nd 2 general outtput bits forr static operration are prrovided. Pin asssignments an nd application n circuit are optimized o for eassy PCB layou ut and cost sa aving advanta ages. A APPLIC CATION NS • Microcontro oller peripherral device eo equipment • Audio/Vide FE EATUR RES • • • • • CMOS techn nology Logic powerr supply: VDD D=3.3V±10% or o 5.0V±10% VFD drive power supply: VEE=-20V to o -35V ( RC)) Built-in oscillation circuit (External One-byte insstruction execcution (not including Data Write to RAM M) • Microcontroller interface • Display conttents: - Character generator RO OM (CGROM): 5x7 Dots (248 Chara acter data typ pes) - Character generator RA AM (CGRAM): 5x7 Dots (8 Character data types) - Additional data RAM (A ADRAM): 16 Display D digits x 2 Bits (Syymbol data) - Data contrrol RAM (DCR RAM): 16 Disp play digits x 8 Bits (Chara acter data dissplay register)) - General ou utput port: 2 bits b (Static op peration) • Display conttrol function: - Display digits: 9 to 16 digits d - Display du uty (Contrast adjustment): 8 stages - All displayy lights: ON/O OFF mode B BLOCK K DIAGRAM Te el: 886-662962 288‧Fax: 886-29174598‧ htttp://www.princceton.com.tw‧2F, 233-1, Bao ociao Road, Sin ndian, Taipei 23 3145, Taiwan PT6302 APPLICATION CIRCUIT V2.3 2 June 2012 PT6302 O ORDER R INFORMATION Valid Part Number PT6302L LQ-001 PT6302L LQ-003 PT6302L LQ-005 PT6302L LQ-007 PT6302--001-H PT6302--003-H PT6302--005-H PT6302--007-H Pa ackage Type e 64 4 pins, LQFP P 64 4 pins, LQFP P 64 4 pins, LQFP P 64 4 pins, LQFP P Bare Chip Bare Chip Bare Chip Bare Chip Top Co ode PT6302LQ-001 PT6302LQ-003 PT6302LQ-005 PT6302LQ-007 - P PIN CO ONFIGU URATIO ON P PIN DES SCRIP PTION V2.3 Pin Nam me SG5 to SG35 S SG4 to SG1 S GR1 to GR16 G VEE E VSS S OSCI OSCO O I//O RSTB B I CSB B I CLKB B I DIN VDD D P1 to P2 P AD2 to AD1 A I O O Descrription O Segm ment driver output pin O I O Grid driver d output pin p Powe er supply Groun nd pin Oscillator input pin Oscillator output piin Resett input pin When n this pin is se et to "LOW", all a functions are a initialized. s input pin p Chip select When n this pin is se et to "High" Le evel, the seria al data transfe er is disabled. c input pin n Shift clock The serial s data is shifted s at the rising edge of CLKB. Seriall data input piin Positive power sup pply General purpose output o pin Segm ment driver output pin 3 Pin No. 1 ~ 31 64 4 ~ 61 32 2 ~ 47 48 49 50 51 52 53 54 55 56 57 7 ~ 58 59 9 ~ 60 June 2012 PT6302 IN NPUT & OUT TPUT CONFI C IGURA ATION LO OGIC IN NPUT PIN NS LO OGIC OUTPUT PINS P DRIVER OUTPUT O T PINS V2.3 4 June 2012 PT6302 FUNCTION DESCRIIPTION N O OSCILLA ATION CIIRCUIT An oscillation circuit may be constructed c b connecting external Ressistor (R1) and by d Capacitor (C C1) between the oscillator pin ns -- OSCO and OSCI. The e RC time con nstant depend ds on the valu ue of VDD vo oltage used. The T target osccillation frequency is 2M MHz. Please re efer to the dia agram below. R RESET FUNCTIO ON The Reset Funcction is enable ed when the RSTB R Pin is set s to "Low" Level. All functtions are initia alized. The initial status of the e various funcctions is given n below: 1. Address of each RAM: Address A "00"H H 2. Data of eacch RAM: All co ontents are un ndefined. 3. General Ou utput Ports: Alll General Output Ports are e set to "LOW W". 4. Display Digit: 16 Digits 5. Contrast Ad djustment: 8/1 16 6. All Display Lights: L OFF Mode M 7. Segment Output: All Seg gment Outputs are set to "L LOW". 8. AD Output: All AD Outpu uts are set to "LOW". The RSTB Pin may m be conne ected to eitherr the microcontroller or an external Resistor and capa acitor. For an external RC con nnection, plea ase refer to th he diagram be elow. V2.3 5 June 2012 PT6302 Aftter reset, the PT6302 mustt be set accorrding to the In nitial Setting Flowchart sho own below. V2.3 6 June 2012 PT6302 RELATIO R ONSHIP BETWEE B EN SEGMENT DRIVERS D S SGN AND A ADN N (ONE DIGIT) The following diagram best describes d the relationship between b the Segment S Drivvers -- SGn an nd ADn. C0 AD1 C1 AD2 C0 SG1 C5 SG6 C10 SG11 C15 SG16 C20 SG21 C25 SG26 C30 SG31 C1 SG2 C6 SG7 C11 SG12 C16 SG17 C21 SG22 C26 SG27 C31 SG32 C2 SG3 C7 SG8 C12 SG13 C17 SG18 C22 SG23 C27 SG28 C32 SG33 C C3 SG G4 C C8 SG G9 C1 13 SG G14 C1 18 SG G19 C2 23 SG G24 C2 28 SG G29 C3 33 SG G34 DATA IS WRIITEN BY Y THE CGRAM C S TO THE 6TH THIS CORRESPONDS DATA IS WRITT D TEN BY THE C CGRAM. THIS CORRESPOND C S T THE 2ND BY TO YTE DATA IS WRIITE D EN BY THE CG GRAM THIS C CORRESPONDS S TO THE 3RD D BYTE. C4 SG5 C9 SG10 0 C14 SG15 5 C19 SG20 0 C24 SG25 5 C29 SG30 0 C34 SG35 5 DATA IS WRITT D TEN BY ADRAM M. T THIS CORRESP PONDS TO THE E 2ND BYTE DATA IS WRIT TTEN BY THE CGRAM C THIS CORRES SPONDS TO TH HE 5TH DATA IS WRITTE EN BY THE CG GRAM HIS CORRESP PONDS TO THE E 4TH TH DA ATA TRA ANSFER R The Display Control Command and the da ata are written n by an 8-bit serial s data tra ansfer. Please e refer to the Write W Timing Dia agram below. Notte: When data is written into the RAM R (DCRAM, ADRAM, A CGRAM M) in a continuous manner, the ad ddress are autom matically increme ented. Therefore it is not necessary to o specify the first byte of the 2nd and later bytes when writing the e RAM data. Wh hen the CSB pin is set to "L LOW" Level, data transfer operation is enabled. e 8 bitts of data are sequentially inputted into the e DIN Pin (LSB first). The shift s clock is in nputted into CLKB C pin and the shift regisster reads the e data at rising g edge of the shiift clock. The internal load signals s are au utomatically generated g and d the data is written w to each h register and d RAM. Thus, it iss not necessa ary to input load signals exxternally. Wh hen the CSB Pin is set to "HIGH" " Level,, the data tran nsfer operatio on is disabled. The data inp put when the CSB Pin cha anges from "H HIGH" to "LOW" is recogniized in 8-bit units. u V2.3 7 June 2012 PT6302 COMMANDS The following are the list of commands issued by PT6302. When data is written into the RAM (DCRAM, CGRAM, or ADRAM) in a continuous manner, the addresses are automatically incremented internally. It is therefore not necessary to specify the first byte. LSB NO. 1 2 3 4 COMMAND B0 DCRAM DATA WRITE X0 CGRAM DATA WRITE X0 ADRAM DATA WRITE GENERAL OUTPUT PORT SET FIRST BYTE B 1 X1 X1 B2 B3 B4 B5 X2 X3 1 0 X2 * 0 MSB B 7 0 0 B6 1 0 0 X0 X1 X2 X3 1 1 0 0 P1 P2 * * 0 0 1 0 D2 * 1 0 1 0 K2 * 0 * * * 0 1 0 1 1 0 1 1 0 0 0 1 5 DISPLAY DUTY SET D0 6 7 NO. OF DIGITS SET ALL LIGHTS ON/OFF TEST MODE K0 L 0 D 1 K1 H 0 LSB SECOND BYTE B0 B1 B2 B3 B4 C0 C1 C2 C3 C4 C0 C5 C10 C15 C20 C1 C6 C11 C16 C21 C2 C7 C12 C17 C3 C8 C13 C4 C9 C0 C1 MSB B5 B6 B7 C5 C6 C7 C25 C30 * C26 C31 * C22 C27 C32 * C18 C23 C28 C33 * C14 C19 C24 C29 C34 * * * * * * * 2ND BYTE 3RD BYTE 4TH BYTE 5TH BYTE 6TH BYTE Notes: 1. The Test Mode is not a user function, but an IC internal function 2. *=Not relevant 3. Xn=RAM address bit, n = 0 to 3 4. Cn=RAM character code bit, n=0 to 34 5. Pn=General output port status bit, n=1 to 2 6. Dn=Display duty bit, n=0 to 2 7. Kn=Number of digits bit, n=0 to 2 8. H=All lights on 9. L=All lights off DATA CONTROL RAM (DCRAM) DATA WRITE COMMAND The DCRAM Data Write Command is used to specify the address of the DCRAM and writes the character code of the CGROM and CGRAM. The DCRAM consists of 4 address bits which are used to store the CGRAM & CGROM character codes. The character codes specified by the DCRAM is converted to a 5 x 7 dot matrix character pattern via the CGROM and CGRAM. The DCRAM can store up to 16 characters. The DCRAM Data Write Command Format is shown below. 1st Byte (1st) 2nd Byte (2nd) V2.3 LSB B0 B1 B2 B3 B4 B5 X0 X1 X2 X3 1 0 MSB B6 B7 0 0 LSB B0 B1 B2 B3 B4 B5 MSB B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 8 DCRAM Data Write Mode is selected and the DCRAM Address is specified. (i.e. DCRAM Address = 0H) CGROM & CGRAM Character Codes are specified. (They are written into the DCRAM Address 0H) June 2012 PT6302 During a continuous data write operation from one DCRAM Address to the next, it is not necessary to specify the DCRAM address since they are automatically incremented; however, the character code must be specified. Please refer to the information below. 2nd Byte (3rd) LSB B0 B1 B2 B3 B4 B5 B6 MSB B7 C0 C1 C2 C3 C4 C5 C6 C7 LSB 2nd Byte (4th) Character Code of CGRAM & CGROM are specified and written into the DCRAM Address 1H. MSB B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 Character Code of CGRAM & CGROM are specified and written into the DCRAM Address 2H. : : 2nd Byte (17th) 2nd Byte (18th) LSB B0 B1 B2 B3 B4 B5 MSB B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 LSB B0 B1 B2 B3 B4 B5 B6 MSB B7 C0 C1 C2 C3 C4 C5 C6 C7 Character Code of CGRAM & CGROM are specified and written into the DCRAM Address FH. Character Code of CGRAM & CGROM are specified and rewritten into the DCRAM Address 0 H. where: 1. X0 (LSB) to X3 (MSB): DCRAM Address Bits (16 Characters) 2. C0 (LSB) to C7 (MSB): CGROM & CGRAM Character Code Bits (256 Characters) Please refer to the table below for the GRID position and DCRAM Address setting relationship. Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F V2.3 X0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 9 X3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GRID Position GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 GR12 GR13 GR14 GR15 GR16 June 2012 PT6302 CGRAM DATA WRITE COMMAND The Character Generator RAM (CGRAM) Data Write Command is used to specify the CGRAM address (00H to 07H) and write the character pattern data. It consists of 3 address bits which is used to store the 5 x 7 dot matrix character patterns. The CGRAM can store up to 8 types of character patterns which may be displayed by specifying the Character Code (DCRAM Address). The CGRAM Data Write Command Format is given below. 1st Byte (1st) LSB B0 B1 B2 B3 B4 B5 B6 MSB B7 X0 X1 X2 * 0 1 0 0 LSB 2nd Byte (2nd) MSB B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15 C20 C25 C30 * LSB 3rd Byte (3rd) B0 B1 B2 B3 B4 B5 B6 B7 C1 C6 C11 C16 C21 C26 C31 * B0 B1 B2 B3 B4 B5 B6 B7 C2 C7 C12 C17 C22 C27 C32 * 3rd Column Data is specified and rewritten into the CGRAM Address 00H. MSB B0 B1 B2 B3 B4 B5 B6 B7 C3 C8 C13 C18 C23 C28 C33 * LSB 6th Byte (6th) 2nd Column Data is specified and rewritten into the CGRAM Address 00H. MSB LSB 5th Byte (5th) 1st Column Data is specified and rewritten into the CGRAM Address 00H. MSB LSB 4th Byte (4th) CGRAM Data Write Mode is selected and the CGRAM Address is specified (i.e. CGRAM Address = 00H). 4th Column Data is specified and rewritten into the CGRAM Address 00H. MSB B0 B1 B2 B3 B4 B5 B6 B7 C4 C9 C14 C19 C24 C29 C34 * 5th Column Data is specified and rewritten into the CGRAM Address 00H. During a continuous data write operation from one CGRAM Address to the next, it is not necessary to specify the CGRAM address since they are automatically incremented; however, the character pattern data must be specified. The 2nd to the 6th character pattern data byte are considered as one data item, therefore 300ns is sufficient value for parameter tDOFF between bytes. Please refer to the information below. LSB 2nd Byte (7th) MSB B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15 C20 C25 C30 * 1st Column Data is specified and rewritten into the CGRAM Address 01H. : : LSB 6th Byte (11th) B0 C4 MSB B1 C9 B2 C14 B3 C19 B4 C24 B5 C29 B6 C34 B7 * 5th Column Data is specified and rewritten into the CGRAM Address 01H. where: 1. X0 (LSB) to X2 (MSB): CGRAM Address Bits (8 Characters) 2. C0 (LSB) to C34 (MSB): Character Pattern Data Bits (35 outputs/digit) V2.3 10 June 2012 PT6302 Please refer below for the CGROM Address and CGRAM Address Setting relationship. HEX 00 01 02 03 04 05 06 07 X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 CGROM Address RAM00(00000000B) RAM01(00000001B) RAM02(00000010B) RAM03(00000011B) RAM04(00000100B) RAM05(00000101B) RAM06(00000110B) RAM07(00000111B) The CGROM and CGRAM output area placement is given in the table below. C0 C5 C10 C15 C20 C25 C30 C1 C6 C11 C16 C21 C26 C31 C2 C7 C12 C17 C22 C27 C32 C3 C8 C13 C18 C23 C28 C33 C4 C9 C14 C19 C24 C29 C34 Area corresponds to the 6th Byte (5th Column) Area corresponds to the 5th Byte (4th Column) Area corresponds to the 4th Byte (3rd Column) Area corresponds to the 3rd Byte (2nd Column) Area corresponds to the 2nd Byte (1st Column) Note: The Character Generator ROM (CGROM) consists of 8 CGROM Address bits generating 5 x 7 dot matrix character patterns. It can store up to a maximum of 248 types of character patterns. V2.3 11 June 2012 PT6302 ADRAM DATA WRITE COMMAND The Additional Data RAM (ADRAM) consists of 4 address bits used to store the symbol data. It can store up to 2 types of symbol patterns per digit. The symbol data specified by the ADRAM is directly outputted. The terminals to which the ADRAM data are outputted may be used as a cursor. The ADRAM command format is given below. LSB 1st Byte (1st) MSB B0 B1 B2 B3 B4 B5 B6 B7 X0 X1 X2 X3 1 1 0 0 LSB 2nd Byte (2nd) ADRAM Data Write Mode is selected and the ADRAM address is specified. (i.e. ADRAM Address = 0H) MSB B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 * * * * * * Symbol Data is specified and written into the ADRAM Address 0H. During a continuous data write operation from one ADRAM Address to the next, it is not necessary to specify the ADRAM address since they are automatically incremented; however, the symbol data must be specified. Please refer to the information below. LSB MSB 2nd Byte B0 B1 B2 B3 B4 B5 B6 B7 Symbol Data is specified and written into the ADRAM (3rd) Address 1H. C0 C1 * * * * * * LSB 2nd Byte (4th) MSB B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 * * : : * * * * LSB 2nd Byte (17th) MSB B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 * * * * * * LSB 2nd Byte (18th) Symbol Data is specified and written into the ADRAM Address 2H. Symbol Data is specified and written into the ADRAM Address FH. MSB B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 * * * * * * Symbol Data is specified and rewritten into the ADRAM Address 0H. where: 1. X0 (LSB) to X3 (MSB): ADRAM address bits (16 Characters) 2. C0 (LSB) to C1 (MSB): Symbol data bits (2 symbol data per digit) V2.3 12 June 2012 PT6302 Please refer to the table below for the GRID and ADRAM Address relationship. HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F X0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GRID Position GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 GR12 GR13 GR14 GR15 GR16 GENERAL OUTPUT PORT SET COMMAND The General Output Port Set Command is used to specify the general output port status. The general output port is used to control other input/output devices as well as turn on the LED Display. When the general output port is set to "HIGH", the output is equivalent to the VDD voltage. When the general output port is set to "LOW" Level, the output becomes ground potential. The command format is given below. LSB 1st Byte MSB B0 B1 B2 B3 B4 B5 B6 B7 P1 P2 * * 0 0 1 0 A General Output Port is selected and the output status is specified. where: 1. P1, P2: General output port 2. *=Not relevant The following table shows the data setting in relation to the Status of the General Output Port P1 0 1 0 1 P2 0 0 1 1 General Output Port Display Status P1 ="LOW", P2="LOW" (see note 1) P1="HIGH", P2="LOW" P1="LOW", P2="HIGH" P1="HIGH", P2="HIGH" Note: The state when the power is applied or when the RSTB is inputted. V2.3 13 June 2012 PT6302 DISPLAY DUTY SET COMMAND The Display Duty Set Command is used to write the display duty value to the duty cycle register. Using a 3-bit data, the display duty adjusts the contrast in 8 stages. When the power is turned ON or when the RSTB signal is inputted, the duty cycle register value is set to "0". It is advisable to always execute this command before turning on the display, after which the desired duty value may be set. The command format is given below. LSB MSB 1st Byte B0 B1 B2 B3 B4 B5 B6 B7 Display Duty Set Mode is selected and the duty value is specified. D0 D1 D2 * 1 0 1 0 where: 1. D0 (LSB) to D2 (MSB): Display duty data bits (8 stages) 2. *=Not relevant The Relationship between the Setup Data and the Controlled GRID Duty is given in the table below. HEX D2 D1 D0 GRID Duty The state when the Power is turned ON or when 0 0 0 0 8/16 the RSTB signal is inputted 1 0 0 1 9/16 2 0 1 0 10/16 3 0 1 1 11/16 4 1 0 0 12/16 5 1 0 1 13/16 6 1 1 0 14/16 7 1 1 1 15/16 NUMBER OF DIGITS SET COMMAND The Number of Digits Set Command is used to write the number of display digits into the display digit register. Using a 3-bit data, the Number of Digits Set Command can display 9 to 16 digits. When the power is turned ON or when the RSTB signal is inputted, the value is set to "0". It is advisable to always execute this command before the turning on the display. The command format is given below. LSB MSB 1st Byte The Number of Digits Set Mode is selected and the B0 B1 B2 B3 B4 B5 B6 B7 number of digit value is specified. K0 K1 K2 * 0 1 1 0 The table below shows the relationship between the setup data and the controlled GR. HEX K2 K1 K0 Number of Digits of GR The state when the Power is turned ON or 0 0 0 0 GR1 ~ GR16 when the RSTB signal is inputted. 1 0 0 1 GR1 ~ GR9 2 0 1 0 GR1 ~ GR10 3 0 1 1 GR1 ~ GR11 4 1 0 0 GR1 ~ GR 12 5 1 0 1 GR1~ GR13 6 1 1 0 GR1~ GR14 7 1 1 1 GR1~ GR15 V2.3 14 June 2012 PT6302 DISPLAY Y LIGHT SET S CO OMMAND D The Display Ligh ht Set Comma and is used to o turn all display lights ON or o OFF. All Display Lights ON O Mode is primarily used forr testing the display. d The All A Display Lig ght OFF Mode e is used for the blinking display d and to o prevent anyy malfunction hen the powerr is turned ON N. The genera al output portt cannot be co ontrolled by th his command d. The comma and format is wh givven below. MSB LSB B0 L 1st Byte B B1 H B2 * B3 * B4 B 1 B5 1 B6 1 B7 0 The Display Light Set Command is sellected. ere: whe 1. L=All L display lightts are turned off 2. H=All H display ligh hts are turned on 3. *=Not relevant The table below w shows the SG S and AD Diisplay Status in relation to the Display Light L Set Com mmand data. L 0 1 0 1 H 0 0 1 1 SG and a AD Display y State Norm mal Display Mod de All Outputs="LOW" All Outputs="HIGH"" All Outputs="HIGH"" The state s when the power is applie ed or when the RSTB signa al is inputted All Diisplay Light ON N Mode has the e first priority. R RECOMM MENDED D SOFTW WARE FL LOWCH HART Nottes: 1. Display D light activve mode (ex. 011 11XX00B) 2. Test T mode off (exx. 1000X000B) V2.3 15 June 2012 PT6302 ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage 1 Supply voltage 2 Input voltage Power dissipation Output current 1 Output current 2 Output current 3 Output current 4 Operating temperature Storage temperature Symbol VDD VEE VIN PD IO1 IO2 IO3 IO4 Topr Tstg Condition Ta ≤ 25℃ GR1 to GR16 AD1 to AD2 SG1 to SG35 P1 to P2 - Rating -0.3 to 6.5 -35 to VDD+0.3 -0.3 to VDD+0.3 541 -40 to 0 -20 to 0 -10 to 0 -4.0 to 4.0 -40 to +85 -65 to +150 Unit V V V mW mA mA mA mA ℃ ℃ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Supply voltage 1 VDD Supply voltage 2 VEE High level input voltage VIH Low level input voltage VIL CLKB frequency fc Oscillation frequency Frame frequency RSTB input time Operating temperature V2.3 fosc fFR tRSON Topr Condition Power supply voltage=5V Power supply voltage=3.3V Power supply voltage=5V All input pins except OSCI. Power supply voltage=3.3V All input pins except OSCI. Power supply voltage=5V All input pins except OSCI. Power supply voltage=3.3V All input pins except OSCI. Power supply voltage=5V Power supply voltage=3.3V Power supply voltage=5V R1=3.3KΩ, C1=47pF Power supply voltage=3.3V R1=3.3KΩ, C1=39pF Power supply voltage=5V DIGIT=1 to 16, R1=3.3KΩ, C1=47pF Power supply voltage=3.3V DIGIT=1 to 16, R1=3.3KΩ, C1=39pF Power supply voltage=5V Power supply voltage=3.3V Power supply voltage=5V Power supply voltage=3.3V 16 Min. 4.5 3.0 -35 -35 Typ. 5.0 3.3 - Max. 5.5 3.6 -20 -20 Unit V V V V 0.7VDD - - V 0.8VDD - - V - - 0.3VDD V - - 0.2VDD V - - 1.0 1.0 MHz MHz 1.5 2.0 2.5 MHz 1.5 2.0 2.5 MHz 183 244 305 Hz 183 244 305 Hz 200 200 -40 -40 - 85 85 µs ℃ ℃ June 2012 PT6302 DC ELECTRICAL CHARACTERISTICS (Unless otherwise specified, VEE=-35V, Ta=-40 to +85℃) Parameter High level input voltage Low level input voltage High level input current Low level input current High level output voltage 1 High level output voltage 2 Symbol VIH VIL IIH IIL VOH1 VOH2 VOH3 High level output voltage 3 High level output voltage 4 Low level output voltage 1 Low level output voltage Current consumption 1 Current consumption 2 V2.3 VOH4 VOL1 VOL2 IDD1 IDD2 Condition VDD=5.0±10% CSB, CLKB, DIN, RSTB VDD=3.3±10% CSB, CLKB, DIN, RSTB VDD=5.0±10% CSB, CLKB, DIN, RSTB VDD=3.3±10% CSB, CLKB, DIN, RSTB VDD=5.0±10% CSB, CLKB, DIN, RSTB; VIH=VDD VDD=3.3±10% CSB, CLKB, DIN, RSTB; VIH=VDD VDD=5.0±10% CSB, CLKB, DIN, RSTB; VIL=0V VDD=3.3±10% CSB, CLKB, DIN, RSTB; VIL=0V VDD=5.0±10% GR1 to GR16; IOH=-30mA VDD=3.3±10% GR1 to GR16; IOH=-30mA VDD=5.0±10% AD1 to AD2, IOH=-15mA VDD=3.3±10% AD1 to AD2, IOH=-15mA VDD=5.0±10% SG1 to SG35, IOH=-6mA VDD=3.3±10% SG1 to SG35, IOH=-6mA VDD=5.0±10% P1 to P2, IOH=-5mA VDD=3.3±10% P1 to P2, IOH=-2.5mA VDD=5.0±10% GR1 to GR16, AD1 to AD2,SG1 to SG35 VDD=3.3±10% GR1 to GR16, AD1 to AD2; SG1 to SG35 VDD=5.0±10% P1, P2, IOL=15mA VDD=3.3±10% P1, P2, IOL=7.5mA VDD=5.0±10% VDD, fosc=2MHz, No Load Duty 15/16, DIGIT 1 to 16; All outputs lights ON VDD=3.3±10% VDD, fosc=2MHz, No Load Duty 15/16, DIGIT 1 to 16; All outputs lights ON VDD=5.0±10% VDD, fosc=2MHz, No Load Duty 8/16, DIGIT 1 to 9; All outputs lights OFF VDD=3.3±10% VDD, fosc=2MHz, No Load Duty 8/16, DIGIT 1 to 9; All outputs lights OFF 17 Min. Max. Unit 0.7VDD - V 0.8VDD - V - 0.3VDD V - 0.2VDD V -1.0 1.0 µA -1.0 1.0 µA -1.0 1.0 µA -1.0 1.0 µA VDD-1.5 - V VDD-1.5 - V VDD-1.5 - V VDD-1.5 - V VDD-1.5 - V VDD-1.5 - V VDD-1.0 - V VDD-1.0 - V - VEE+1.0 V VEE+1.0 V - 1.0 V - 1.0 V - 4 mA - 3 mA - 3 mA - 2 mA June 2012 PT6302 AC CHARACTERISTICS (Unless otherwise specified, VEE=-35V, Ta=-40 to +85℃) Parameter Symbol Condition VDD=5.0V+10% CLKB cycle time fc VDD=3.3V+10% VDD=5.0V+10% CLKB pulse width tCW VDD=3.3V+10% VDD=5.0V+10% DIN setup time tDS VDD=3.3V+10% VDD=5.0V+10% DIN hold time tDH VDD=3.3V+10% VDD=5.0V+10% CSB setup time tCSS VDD=3.3V+10% VDD=5.0V+10% R1=3.3KΩ, C1=47pF CSB hold time tCSH VDD=3.3V+10% R1=3.3KΩ, C1=39pF VDD=5.0V+10% CSB wait time tCSW VDD=3.3V+10% VDD=5.0V+10% R1=3.3KΩ, C1=47pF Data processing time tDOFF VDD=3.3V+10% R1=3.3KΩ, C1=39pF VDD=5.0V+10% When the RSTB signal is externally inputted from the microcontroller. RSTB pulse width tWRSTB VDD=3.3V+10% When the RSTB signal is externally inputted from the microcontroller. VDD=5.0V+10% DIN wait time tRSOFF VDD=3.3V+10% VDD=5.0V+10% Ci=100pF, tR=20% to 80% tR VDD=3.3V+10% Ci=100pF, tR=20% to 80% All outputs slew rate VDD=5.0V+10% Ci=100pF, tF=80% to 20% tF VDD=3.3V+10% Ci=100pF, tF=80% to 20% VDD=5.0V+10% Mounted in the Unit VDD rise time tPRZ VDD=3.3V+10% Mounted in the Unit VDD=0V VDD off time tPOF Mounted in the Unit V2.3 18 Min. 1.0 1.0 300 300 300 300 300 300 300 300 Max. - Unit µs µs ns ns ns ns ns ns ns ns 16 - µs 16 - µs 300 300 - ns ns 8 - µs 8 - µs 300 - ns 300 - ns 300 300 - ns ns - 4.0 µs - 4.0 µs - 4.0 µs - 4.0 µs 100 - 100 - 5.0 - µs ms June 2012 PT6302 T TIMING G CHAR RACTE ERISTIICS P Parameter High le evel input volttage Low le evel input volta age Symbol VIH VIL VDD=3.3V±1 10% 0.8VDD 0.2VDD VDD=5.0 0±10% 0.7VDD 0.3VDD DA ATA TIM MING R RESET (R RSTB) TIMING T O OUTPUT TIMING G DIGIT OU UTPUT TIMING T ( (16-DIGI T DISPL LAY, DUT TY= 15/1 16) whe ere: T=8/fosc V2.3 19 June 2012 PT6302 PT6302-001 CHARACTER FONT TABLE V2.3 20 June 2012 PT6302 PT6302-003 CHARACTER FONT TABLE V2.3 21 June 2012 PT6302 PT6302-005 CHARACTER FONT TABLE V2.3 22 June 2012 PT6302 PT6302-007 CHARACTER FONT TABLE V2.3 23 June 2012 PT6302 PAD CONFIGURATION ALIGNMENT MARK DIMENSION Die Size: Chip Thickness: PAD Size: PAD Pitch: V2.3 24 X=2870μm Y=3140μm (Extended Buffer) 300μm X=90μm Y=90μm 110μm June 2012 PT6302 PAD LOCATION Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 V2.3 Pad Name SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 Location [478.600, 2852.100] [50.000, 2637.500] [50.000, 2447.500] [50.000, 2257.500] [50.000, 2107.500] [50.000, 1967.500] [50.000, 1827.500] [50.000, 1687.500] [50.000, 1547.500] [50.000, 1407.500] [50.000, 1267.500] [50.000, 1127.500] [50.000, 987.500] [50.000, 847.500] [50.000, 707.500] [50.000, 567.500] [50.000, 427.500] [50.000, 287.500] [233.800, 50.000] [413.800, 50.000] [593.800, 50.000] [773.800, 50.000] [918.800, 50.000] [1063.800, 50.000] [1208.800, 50.000] [1353.800, 50.000] [1498.800, 50.000] [1643.800, 50.000] [1788.800, 50.000] [1933.800, 50.000] [2078.800, 50.000] [2223.800, 50.000] [2615.800, 267.200] [2615.800, 427.200] [2615.800, 587.200] [2615.800, 747.200] [2615.800, 907.200] [2615.800, 1057.200] [2615.800, 1187.200] [2615.800, 1317.200] [2615.800, 1447.200] [2615.800, 1577.200] 25 June 2012 PT6302 Pad No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 56 57 58 59 60 61 62 63 64 V2.3 Pad Name GR12 GR13 GR14 GR15 GR16 VEE VSS OSCI OSCO RSTB CSB CLKB DIN VDD VDD P1 P2 AD2 AD1 SG1 SG2 SG3 SG4 Location [2615.800, 1707.200] [2615.800, 1837.200] [2615.800, 1967.200] [2615.800, 2097.200] [2615.800, 2227.200] [2615.800, 2357.200] [2615.800, 2487.200] [2543.700, 2772.300] [2395.900, 2772.300] [2277.900, 2772.300] [2167.900, 2772.300] [2057.900, 2772.300] [1947.900, 2772.300] [1837.900, 2772.300] [1727.900, 2772.300] [1615.300, 2772.300] [1490.100, 2772.300] [1258.600, 2852.100] [1128.600, 2852.100] [998.600, 2852.100] [868.600, 2852.100] [738.600, 2852.100] [608.600, 2852.100] 26 June 2012 PT6302 PACKAGE INFORMATION 64 PINS, LQFP Symbol A A1 A2 b c D D1 E E1 e L L1 θ Min. 0.05 1.35 0.30 0.09 Nom. 1.40 0.35 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.80 BSC 0.60 1.00 REF 3.5° 0.45 0° Max. 1.60 0.15 1.45 0.40 0.16 0.75 7° Notes: 1. All dimensions are in millimeter 2. Refer to JEDEC MS-022 BE V2.3 27 June 2012 PT6302 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V2.3 28 June 2012