PEDL9201-03 PEDL9201-03 el Pr Fluorescent Display Tube Controller Driver GENERAL DESCRIPTION The MSM9201-01 is a dot matrix fluorescent display tube controller driver IC which displays characters, numerics and symbols. Dot matrix fluorescent display tube drive signals are generated by serial data sent from a microcontroller. A display system is easily realized by internal ROM and RAM for character display. FEATURES • Logic power supply (VDD) : 3.3 V±10%/5.0 V±10% • Fluorescent display tube drive power supply (VDISP) : 3.3 V±10%/5.0 V±10% • Fluorescent display tube drive power supply (VFL) : –20 to –60 V • VFD driver output current (VFD driver output can directly be connected to the fluorescent display tube. No pull-down resistor is required.) - Segment driver (SEG1 to SEG35) : –5.0 mA (VFL=–60V) - Segment driver (AD1 to AD8) : –10.0 mA (VFL=–60V) - Grid driver (COM1 to COM16) : –20.0 mA (VFL=–60V) • General output port output current - Output driver (P1-4) : ±1.0 mA (VDD=3.3V±10%) ±2.0 mA (VDD=5.0V±10%) • Content of display - CGROM 5¥7 dots, 240 types (character data) - CGRAM 5¥7 dots, 16 types (character data) - ADRAM 24 (display digit) ¥4 bits (symbol data) - DCRAM 24 (display digit) ¥8 bits (register for character data display) - General output port 4 bits (static mode) • Display control function - Display digit : 9 to 24 digits - Display duty (contrast adjustment) : 8 stages - All lights ON/OFF • 3 interfaces with microcontroller : DA, CS, CP (4 interfaces if RESET is added) • 1-byte instruction execution (excluding data write to RAM) • Built-in oscillation circuit (external C and R) • Package options: 80-pin plastic QFP (QFP80-P-1414-0.65-K) (Product name: MSM9201-01GS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM9201-01GS-BK) 1/35 y ar This version: Sep. 2000 MSM9201-01 Previous version: Nov. 1997 in ¡ Semiconductor MSM9201-01 im ¡ Semiconductor PEDL9201-03 ¡ Semiconductor MSM9201-01 BLOCK DIAGRAM VDISP VDD GND VFL DCRAM 24w¥8b SEG1 CGROM 240w¥35b Segment Driver CGRAM 16w¥35b RESET DA CP CS 8-bit Shift Register ADRAM 24w¥8b DCRAM Address Counter SEG35 AD1 AD Driver AD4 Address Selector Command Decoder Write Address Counter Read Address Counter P1 Port Driver Control Circuit P4 Digit Control Duty Control Timing Generator 1 COM1 Grid Driver COM24 Timing Generator 2 OSC0 Oscillator OSC1 2/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 INPUT AND OUTPUT CONFIGURATION Schematic Diagrams of Logic Portion Input and Output Circuits Input pin VDD VDD INPUT GND GND Output pin VDD VDD OUTPUT GND GND Schematic Diagram of Driver Output Circuit VDISP VDISP OUTPUT VFL VFL 3/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AD2 AD1 VDISP2 NC VFL2 P4 P3 P2 P1 VDD DA CP CS RESET OSC1 OSC0 GND VFL1 COM24 COM23 PIN CONFIGURATION (TOP VIEW) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 VDISP1 COM1 COM2 AD3 AD4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 NC: No connection 80-Pin Plastic QFP (QFP80-P-1414-0.65-K) 4/35 PEDL9201-03 ¡ Semiconductor 65 VFL1 66 GND 67 OSC0 68 OSC1 69 RESET 70 CS 71 CP 72 D4 73 VDD 74 P1 75 P2 76 P3 77 P4 2 64 COM24 63 COM23 3 62 COM22 4 61 COM21 5 60 COM20 6 59 COM19 7 8 58 COM18 57 COM17 1 9 56 COM16 10 55 COM15 11 12 54 COM14 53 COM13 13 52 COM12 14 51 COM11 15 16 50 COM10 49 COM9 17 48 COM8 18 47 COM7 19 46 COM6 20 45 COM5 44 COM4 21 23 43 COM3 42 COM2 24 41 COM1 22 SEG21 25 SEG22 26 SEG23 27 SEG24 28 SEG25 29 SEG26 30 SEG27 31 SEG28 32 SEG29 33 SEG30 34 SEG31 35 SEG32 36 SEG33 37 SEG34 38 SEG35 39 VDISP1 40 AD1 AD2 AD3 AD4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 78 VFL2 80 VDISP2 79 NC MSM9201-01 NC: No connection 80-Pin Plastic QFP (QFP80-P-1420-0.80-BK) 5/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 PIN DESCRIPTIONS Pin Symbol Type Connects to: QFP-1* QFP-2* Description Fluorescent Fluorescent display tube anode electrode drive output. 3-27 5-39 SEG1-35 O tube anode Directly connected to fluorescent display tube. No pull-down electrode resistor is required. IOH>–5.0 mA Fluorescent Fluorescent display tube grid electrode drive output. 39-62 41-64 COM1-24 O tube grid Directly connected to fluorescent display tube. No pull-down electrode resistor is required. IOH>–20.0 mA Fluorescent Fluorescent display tube anode electrode drive output. 1, 2, 79, 80 * 1-4 AD1-4 O tube anode Directly connected to fluorescent display tube. No pull-down electrode resistor is required. IOH>–10.0 mA LED drive General port output. control Output of these pins in static operation, so these pins can drive 72-75 74-77 P1-4 O terminals the LED. IOH>–2.0 mA 71 73 VDD — Power VDD-GND are power supplies for internal logic. 38, 78 40, 80 VDISP1-2 — supply 64 66 GND — 63, 76 65, 78 VFL1-2 — 70 72 DA I 69 71 CP I 68 70 CS I VDISP-VFL are power supplies for driving fluorescent tubes. Use the same power supply for VDD and VDISP. Micro- Serial data input (positive logic). controller Input from LSB. Micro- Shift clock input. controller Serial data is shifted on the rising edge of CP. Micro- Chip select input. controller Setting this pin to "H" disables serial data transfer. QFP-1 : QFP80-P-1414-0.65-K QFP-2 : QFP80-P-1420-0.80-BK 6/35 PEDL9201-03 ¡ Semiconductor Pin QFP-1* QFP-2* MSM9201-01 Symbol Type Connects to: Description Reset input. Setting this pin to "Low" initializes all the functions. The initial status is as follows. Micro67 69 RESET I • Address of each RAM address "00"H • Data of each RAM Content is undefined • Number of display digits 24 digits controller • Contrast adjusment or C2, R2 8/16 • All lights ON or OFF OFF mode • All outputs "Low" level RESET (Circuit when R and C are connected externally) C2 R2 See Application Circuit. External RC pin for RC oscillation. 65 67 OSC0 Connect R and C externally. The RC time constant depends on the I C1, R1 VDD voltage used. Set the target oscillation frequency to 2 MHz. OSC0 66 * 68 OSC1 O (RC oscillation circuit) R1 OSC1 C1 See Application Circuit. QFP-1 : QFP80-P-1414-0.65-K QFP-2 : QFP80-P-1420-0.80-BK 7/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage 1 Symbol Condition Rating Unit VDD (*1) –0.3 to +6.5 V VDISP (*1) –0.3 to +6.5 V Supply Voltage 2 VFL — –80 to VDISP+0.3 V Input Voltage VIN — –80 to VDD+0.3 V Power Dissipation PD Storage Temperature Output Current Ta£25°C QFP80-P-1414-0.65-K 565 QFP80-P-1420-0.80-BK 643 mW TSTG — –55 to +150 IO1 COM1-COM24 –30 to 0.0 IO2 AD1-AD4 –20 to 0.0 IO3 SEG1-SEG35 –10 to 0.0 IO4 P1-P4 –4.0 to +4.0 °C mA *1 Use the same power supply for VDD and VDISP. RECOMMENDED OPERATING CONDITIONS (1) When the power supply voltage is 5V (typ) Parameter Supply Voltage 1 Symbol Condition Min. Typ. Max. Unit — 4.5 5.0 5.5 V — –60 — –20 V — — V — 0.3VDD V VDD VDISP Supply Voltage 2 VFL High Level Input Voltage VIH All input pins excluding OSC0 pin 0.7VDD Low Level Input Voltage VIL All input pins excluding OSC0 pin CP Frequency — fC — — — 1.0 MHz Oscillation Frequency fOSC R=3.3kW, C=47pF 1.5 2.0 2.5 MHz Frame Frequency fFR DIGIT=1-24, R=3.3kW, C=47pF 122 163 204 Hz Operating Temperature Top — –40 — 85 °C Condition Min. Typ. Max. Unit — 3.0 3.3 3.6 V — –60 — –20 V — — V RECOMMENDED OPERATING CONDITIONS (2) When the power supply voltage is 3.3V (typ) Parameter Supply Voltage 1 Symbol VDD VDISP Supply Voltage 2 VFL High Level Input Voltage VIH All input pins excluding OSC0 pin 0.8VDD Low Level Input Voltage VIL All input pins excluding OSC0 pin — — 0.2VDD V CP Frequency fC — — — 1.0 MHz fOSC R=3.3kW, C=39pF 1.5 2.0 2.5 MHz Frame Frequency fFR DIGIT=1–24, R=3.3kW, C=39pF 122 163 204 Hz Operating Temperature Top — –40 — 85 °C Oscillation Frequency 8/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 ELECTRICAL CHARACTERISTICS DC Characteristics (1) (VDD=VDISP=5.0V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) Parameter Symbol High Level Input Voltage VIH Low Level Input Voltage VIL High Level Input Current IIH Low Level Input Current IIL Applied pin CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET Condition Min. Max. Unit — 0.7VDD — V — — 0.3VDD V VIH=VDD –1.0 1.0 µA VIL=0.0V –1.0 1.0 µA VOH1 COM1-24 IOH1=–20.0mA VDISP–1.5 — V High Level Output VOH2 AD1-4 IOH2=–10.0mA VDISP–1.5 — V Voltage VOH3 SEG1-35 IOH3=–5.0mA VDISP–1.5 — V VOH4 P1-4 IOH4=–2.0mA VDD–1.0 — V — — VFL+1.0 V IOL1=2mA — 1.0 V — 4 mA — 3 mA COM1-24 Low Level Output VOL1 AD1-4 SEG1-35 Voltage VOL2 P1-4 Duty=15/16 IDD1 fOSC= VDD, VDISP Supply Current IDD2 2MHz, no load Digit=1–24 All outputs go ON Duty=8/16 Digit=1–9 All outputs go OFF 9/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 DC Characteristics (2) (VDD=VDISP=3.3V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) Parameter Symbol High Level Input Voltage VIH Low Level Input Voltage VIL High Level Input Current IIH Low Level Input Current IIL Applied pin CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET Condition Min. Max. Unit — 0.8VDD — V — — 0.2VDD V VIH=VDD –1.0 1.0 µA VIL=0.0V –1.0 1.0 µA VOH1 COM1-24 IOH1=–20.0mA VDISP–1.5 — V High Level Output VOH2 AD1-4 IOH2=–10.0mA VDISP–1.5 — V Voltage VOH3 SEG1-35 IOH3=–5.0mA VDISP–1.5 — V VOH4 P1-4 IOH4=–1.0mA VDD–1.0 — V — — VFL+1.0 V IOL1=2mA — 1.0 V — 3 mA — 2 mA COM1-24 Low Level Output VOL1 AD1-4 SEG1-35 Voltage VOL2 P1-4 Duty=15/16 IDD1 fOSC= VDD, VDISP Supply Current IDD2 2MHz, no load Digit=1–24 All outputs go ON Duty=8/16 Digit=1–9 All outputs go OFF 10/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 AC Characteristics (1) (VDD, VDISP=5.0V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) Parameter CP Frequncy Symbol Condition Min. Max. Unit fC — — 1.0 MHz tCW — 300 — ns DA Setup Time tDS — 300 — ns DA Hold Time tDH — 300 — ns CP Pulse Width CS Setup Time tCSS — 300 — ns CS Hold Time tCSH R1=3.3kW, C1=47pF 16 — ms CS Wait Time tCSW — 300 — ns Data Processing Time tDOFF R1=3.3kW, C1=47pF 8 — ms RESET Pulse Width tWRES When RESET signal is input externally 300 — ns DA Wait Time tRSOFF — Slew Rate (All Drivers) tR Cl=100pF 300 — ms tR=20% to 80% — 4.0 ms tF=80% to 20% — 4.0 ms VDD Rise Time tPRZ When mounted on the unit — 100 ms VDD Off Time tPOF When mounted on the unit, VDD=0.0V 5.0 — ms tF AC Characteristics (2) (VDD, VDISP=3.3V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) Parameter CP Frequncy Symbol Condition Min. Max. Unit fC — — 1.0 MHz tCW — 300 — ns DA Setup Time tDS — 300 — ns DA Hold Time tDH — 300 — ns CP Pulse Width CS Setup Time tCSS — 300 — ns CS Hold Time tCSH R1=3.3kW, C1=39pF 16 — ms CS Wait Time tCSW — 300 — ns Data Processing Time tDOFF R1=3.3kW, C1=39pF 8 — ms RESET Pulse Width tWRES When RESET signal is input externally 300 — ns DA Wait Time tRSOFF — 300 — ms — 4.0 ms Slew Rate (All Drivers) tR Cl=100pF tR=20% to 80% — 4.0 ms VDD Rise Time tPRZ When mounted on the unit — 100 ms VDD Off Time tPOF When mounted on the unit, VDD=0.0V 5.0 — ms tF tF=80% to 20% 11/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 TIMING DIAGRAM Symbol VDD=3.3V±10% VDD=5.0V±10% VIH 0.8 VDD 0.7 VDD VIL 0.2 VDD 0.3 VDD • Data Timing tCSS tCSW CS 0.7 VDD 0.3 VDD tCSH fC tDOFF CP tCW VIH VIL tCW tDH tDS DA VALID VALID VALID VIH VIL VALID • Reset Timing VDD tPRZ tRSON When input externally tWRES RESET 0.8 VDD 0.0 V VIH VIL tRSOFF When external R and C are connected. DA VIH VIL • Output Timing All outputs tR tF 0.8 VDISP 0.2 VFL 12/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 Digit Output Timing (for 24-digit display, at a duty of 15/16) T=8/ fOSC COM1 COM2 COM3 COM4 COM5 COM6 COM19 COM20 COM21 COM22 COM23 COM24 AD1-4 SEG1-35 Frame cycle t1=1536T Display timing t2=60T Blank timing t3=4T (t1=6.144 ms when fosc=2.0 MHz) (t2=240 ms when fosc=2.0 MHz) (t3=16 ms when fosc=2.0 MHz) VDISP VFL VDISP VFL 13/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 FUNCTIONAL DESCRIPTION Command List Command 1 DCRAM data write 2 CGRAM data write 1 3 ADRAM data write 1st byte LSB MSB LSB 2nd byte MSB B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 X0 X1 X2 X3 X4 1 0 0 C0 C1 C2 C3 C4 C5 C6 C7 C0 C5 C10 C15 C20 C25 C30 C1 C6 C11 C16 C21 C26 C31 C2 C7 C12 C17 C22 C27 C32 C3 C8 C13 C18 C23 C28 C33 C4 C9 C14 C19 C24 C29 C34 C0 C1 * * * * * * X0 X0 X1 X1 X2 X3 1 0 X2 X3 X4 1 1 0 * * * * 0 0 1 1 0 1 0 1 1 1 1 1 4 General output port set P1 P2 P3 P4 5 Display duty set D0 D1 D2 * 6 Number of display digits set K0 K1 K2 K3 7 All lights ON/OFF H * * L * 0 Test mode When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte when RAM data for the 2nd and later bytes is written. * Xn Cn Pn Dn Kn H L : : : : : : : : C2 C3 * * * 2nd byte 3rd byte 4th byte 5th byte 6th byte Don't care Address specification for each RAM Character code specification for each RAM General output port status specification Display duty specification Number of display digits specification All lights ON instruction All lights OFF instruction Note: The test mode is used for inspection before shipment. It is not a user function. 14/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 Positional Relationship Between SEGn and ADn (one digit) C0 AD1 C1 AD2 ADRAM written data. Corresponds to 2nd byte C2 AD3 C3 AD4 CGRAM data write mode. Corresponds to 2nd byte CGRAM data write mode. Corresponds to 3rd byte CGRAM data write mode. Corresponds to 4th byte C0 C1 C2 C3 C4 SEG1 SEG2 SEG3 SEG4 SEG5 C5 C6 C7 C8 C9 SEG6 SEG7 SEG8 SEG9 SEG10 C10 C11 C12 C13 C14 SEG11 SEG12 SEG13 SEG14 SEG15 C15 C16 C17 C18 C19 SEG16 SEG17 SEG18 SEG19 SEG20 C20 C21 C22 C23 C24 SEG21 SEG22 SEG23 SEG24 SEG25 C25 C26 C27 C28 C29 SEG26 SEG27 SEG28 SEG29 SEG30 C30 C31 C32 C33 C34 SEG31 SEG32 SEG33 SEG34 SEG35 CGRAM data write mode. Corresponds to 6th byte CGRAM data write mode. Corresponds to 5th byte 15/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 Data Transfer Method and Command Write Method Display control command and data are written by an 8-bit serial transfer. Write timing is shown in the figure below. Setting the CS pin to "Low" level enables a data transfer. Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first). As shown in the figure below, data is read by the shift register at the rise of the shift clock, which is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and RAM. Therefore it is not necessary to input load signals from the outside. Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin changes from "High" to "Low" is recognized in 8-bit units. tDOFF CS tCSH CP DA B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 LSB LSB LSB 1st byte MSB When data is written to DCRAM* Command and address data * 2nd byte MSB Character code data 2nd byte MSB Character code data of the next address When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes. Reset Function Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) which initializes all functions. The initial status is as follows. • Address of each RAM .................. address "00"H • Data of each RAM ........................ All contents are undefined • General output port ..................... All general output ports go "Low" • Number of display digits ............ 24 digits • Contrast adjustment ..................... 8/16 • All display lights ON or OFF ..... OFF mode • Segment output ............................ All segment outputs go "Low" • AD output ..................................... All AD outputs go "Low" After reset is executed, perform settings again according to "Initial Setting Flowchart" shown later. 16/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 Description of Commands and Functions 1. DCRAM data write (Specifies the address (00H to 1FH) of DCRAM and writes the character code of CGROM and CGRAM.) DCRAM (Data Control RAM) has 5-bit addresses to store character code of CGROM and CGRAM. The character code specified in DCRAM is converted to a 5¥7 dot matrix character pattern via CGROM or CGRAM. The DCRAM can store 24 characters. [Command format] LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3 X4 LSB 1 0 0 MSB : selects DCRAM data write mode and specifies DCRAM address. (Ex: Specifies DCRAM address 00H) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM. (written into DCRAM address 00H) To specify the character code of CGROM and CGRAM continuously to the next address, specify only character codes as follows. Since the addresses of DCRAM are automatically incremented, they do not need to be specified. 17/35 PEDL9201-03 ¡ Semiconductor LSB MSM9201-01 MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) C0 C1 C2 C3 C4 C5 C6 C7 LSB : specifies character code of CGROM and CGRAM. (written into DCRAM address 01H) MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (4th) C0 C1 C2 C3 C4 C5 C6 C7 LSB : specifies character code of CGROM and CGRAM. (written into DCRAM address 02H) MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (25th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM. (written into DCRAM address 17H) Setting of CGROM and CGRAM character codes for up to 24 digits is now complete. To further specify character codes continuously from DCRAM address 00H, dummy character codes must be specified for DCRAM address 18H to 1FH (so that DCRAM address will be incremented automatically and will be reset to 00H). LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (26th) C0 C1 C2 C3 C4 C5 C6 C7 LSB : specifies dummy character code of CGROM and CGRAM. (not written into DCRAM address) MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (33th) C0 C1 C2 C3 C4 C5 C6 C7 LSB : specifies dummy character code of CGROM and CGRAM. (not written into DCRAM address) MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (34th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM. (rewritten into DCRAM address 00H) X0 (LSB) to X4 (MSB): DCRAM address (5 bits: 24 characters) C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters) 18/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 [COM positions and set DCRAM address] HEX X0 X1 X2 X3 X4 COM position HEX X0 X1 X2 X3 X4 COM position 00 0 0 0 0 0 COM1 10 0 0 0 0 1 COM17 01 1 0 0 0 0 COM2 11 1 0 0 0 1 COM18 02 0 1 0 0 0 COM3 12 0 1 0 0 1 COM19 03 1 1 0 0 0 COM4 13 1 1 0 0 1 COM20 04 0 0 1 0 0 COM5 14 0 0 1 0 1 COM21 05 1 0 1 0 0 COM6 15 1 0 1 0 1 COM22 06 0 1 1 0 0 COM7 16 0 1 1 0 1 COM23 07 1 1 1 0 0 COM8 17 1 1 1 0 1 COM24 08 0 0 0 1 0 COM9 18 0 0 0 1 1 — 09 1 0 0 1 0 COM10 19 1 0 0 1 1 — 0A 0 1 0 1 0 COM11 1A 0 1 0 1 1 — 0B 1 1 0 1 0 COM12 1B 1 1 0 1 1 — 0C 0 0 1 1 0 COM13 1C 0 0 1 1 1 — 0D 1 0 1 1 0 COM14 1D 1 0 1 1 1 — 0E 0 1 1 1 0 COM15 1E 0 1 1 1 1 — 0F 1 1 1 1 0 COM16 1F 1 1 1 1 1 — 19/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 2. CGRAM data write (Specifies the addresses 00H to 0FH of CGRAM and writes character pattern data.) CGRAM (Character Generator RAM) has 4-bit addresses to store 5¥7 dot matrix character patterns. A character pattern stored in CGRAM can be displayed by specifying the character code (address) in DCRAM. The addresses of CGRAM are assigned to 00H to 0FH. (All the other addresses are the CGROM addresses.) (The CGRAM can store 16 types of character patterns.) [Command format] LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3 * 0 1 LSB 0 MSB : selects CGRAM data write mode and specifies CGRAM address. (Ex: specifies CGRAM address 00H) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C5 C10 C15 C20 C25 C30 LSB * : specifies 1st column data. (written into CGRAM address 00H) MSB B0 B1 B2 B3 B4 B5 B6 B7 3rd byte (3rd) C1 C6 C11 C16 C21 C26 C31 LSB * : specifies 2nd column data. (written into CGRAM address 00H) MSB B0 B1 B2 B3 B4 B5 B6 B7 4th byte (4th) C2 C7 C12 C17 C22 C27 C32 LSB * : specifies 3rd column data. (written into CGRAM address 00H) MSB B0 B1 B2 B3 B4 B5 B6 B7 5th byte (5th) C3 C8 C13 C18 C23 C28 C33 LSB * : specifies 4th column data. (written into CGRAM address 00H) MSB B0 B1 B2 B3 B4 B5 B6 B7 6th byte (6th) C4 C9 C14 C19 C24 C29 C34 * : specifies 5th column data. (written into CGRAM address 00H) To specify character pattern data continuously to the next address, specify only character pattern data as follows. Since the addresses of CGRAM are automatically incremented, they do not need to be specified. The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient for tDOFF time between bytes. 20/35 PEDL9201-03 ¡ Semiconductor LSB MSM9201-01 MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (7th) C0 C5 C10 C15 C20 C25 C30 LSB * : specifies 1st column data. (written into CGRAM address 01H) MSB B0 B1 B2 B3 B4 B5 B6 B7 6th byte (11th) C4 C9 C14 C19 C24 C29 C34 LSB * MSB : specifies 5th column data. (written into CGRAM address 01H) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (12th) C0 C5 C10 C15 C20 C25 C30 LSB * : specifies 1st column data. (written into CGRAM address 02H) MSB B0 B1 B2 B3 B4 B5 B6 B7 6th byte (16th) C4 C9 C14 C19 C24 C29 C34 LSB * : specifies 5th column data. (written into CGRAM address 02H) MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (77th) C0 C5 C10 C15 C20 C25 C30 LSB * : specifies 1st column data. (written into CGRAM address 0FH) MSB B0 B1 B2 B3 B4 B5 B6 B7 6th byte (81th) C4 C9 C14 C19 C24 C29 C34 LSB * MSB : specifies 5th column data. (written into CGRAM address 0FH) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (82th) C0 C5 C10 C15 C20 C25 C30 LSB * : specifies 1st column data. (rewritten into CGRAM address 00H.) MSB B0 B1 B2 B3 B4 B5 B6 B7 6th byte (86th) C4 C9 C14 C19 C24 C29 C34 * : specifies 5th column data. (rewritten into CGRAM address 00H.) X0 (LSB) to X3 (MSB): CGRAM address (4 bits: 16 characters) C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit) 21/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 [CGROM addresses and set CGRAM addresses] Refer to ROM CODE HEX X0 X1 X2 X3 CGROM address HEX X0 X1 X2 X3 CGROM address 00 0 0 0 0 RAM00(00000000B) 08 0 0 0 0 RAM08(00001000B) 01 1 0 0 0 RAM01(00000001B) 09 1 0 0 0 RAM09(00001001B) 02 0 1 0 0 RAM02(00000010B) 0A 0 1 0 0 RAM0A(00001010B) 03 1 1 0 0 RAM03(00000011B) 0B 1 1 0 0 RAM0B(00001011B) 04 0 0 1 0 RAM04(00000100B) 0C 0 0 1 0 RAM0C(00001100B) 05 1 0 1 0 RAM05(00000101B) 0D 1 0 1 0 RAM0D(00001101B) 06 0 1 1 0 RAM06(00000110B) 0E 0 1 1 0 RAM0E(00001110B) 07 1 1 1 0 RAM07(00000111B) 0F 1 1 1 0 RAM0F(00001111B) 22/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 Positional relationship between the output area of CGROM and that of CGRAM Corresponds to 2nd byte (1st column) Corresponds to 3rd byte (2nd column) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 Corresponds to 6th byte (5th column) Corresponds to 5th byte (4th column) Corresponds to 4th byte (3rd column) Note: CGROM (Character Generator ROM) has 8-bit addresses to generate 5¥7 dot matrix character patterns. CGRAM can store 240 types opf character patterns. 23/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 3. ADRAM data write (specifies address of ADRAM and writes symbol data) ADRAM (Additional Data RAM) has 4-bit addresses to store symbol data. Symbol data specified in ADRAM is directly output without CGROM and CGRAM. (The DRAM can store 4 types of symbol patterns for each digit.) The terminal to which the contents of ADRAM are output can be used as a cursor. [Command format] LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3 X4 1 1 0 LSB MSB : selects ADRAM data write mode and specifies ADRAM address. (Ex: specifies ADRAM address 00H) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 * * * : specifies symbol data. (written into ADRAM address 00H) * To specify symbol data continuously to the next address, specify only symbol data as follows. The addresses of ADRAM are automatically incremented. Specification of ADRAM addresses is therefore unnecessary. LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) C0 C1 C2 C3 * * * LSB * MSB : specifies symbol data. (written into ADRAM address 01H) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (4th) C0 C1 C2 C3 * * * LSB * : specifies symbol data. (written into ADRAM address 02H) MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (17th) C0 C1 C2 C3 * * * * : specifies symbol data. (written into ADRAM address 17FH) Setting of symbol data for up to 24 digits is now complete. To further specify symbol data continuously from DCRAM address 00H, dummy symbol data must be specified for ADRAM addresses 18H to 1FH (so that the ADRAM address will be incremented automatically and will be reset to 00H). LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (18th) C0 C1 C2 C3 * * * LSB * : specifies dummy symbol data. (not written into ADRAM address) MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (65th) C0 C1 C2 C3 LSB * * * * MSB : specifies dummy symbol data. (not written into ADRAM address) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (66th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies symbol data. (rewritten into ADRAM address 00H.) X0 (LSB) to X4 (MSB): ADRAM addresses (5 bits: 24 characters) C0 (LSB) to C3 (MSB): Symbol data (4 bits: 4-symbol data per digit) 24/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 [COM positions and ADRAM addresses] HEX X0 X1 X2 X3 X4 COM position HEX X0 X1 X2 X3 X4 COM position 00 0 0 0 0 0 COM1 10 0 0 0 0 1 COM17 01 1 0 0 0 0 COM2 11 1 0 0 0 1 COM18 02 0 1 0 0 0 COM3 12 0 1 0 0 1 COM19 03 1 1 0 0 0 COM4 13 1 1 0 0 1 COM20 04 0 0 1 0 0 COM5 14 0 0 1 0 1 COM21 05 1 0 1 0 0 COM6 15 1 0 1 0 1 COM22 06 0 1 1 0 0 COM7 16 0 1 1 0 1 COM23 07 1 1 1 0 0 COM8 17 1 1 1 0 1 COM24 08 0 0 0 1 0 COM9 18 0 0 0 1 1 — 09 1 0 0 1 0 COM10 19 1 0 0 1 1 — 0A 0 1 0 1 0 COM11 1A 0 1 0 1 1 — 0B 1 1 0 1 0 COM12 1B 1 1 0 1 1 — 0C 0 0 1 1 0 COM13 1C 0 0 1 1 1 — 0D 1 0 1 1 0 COM14 1D 1 0 1 1 1 — 0E 0 1 1 1 0 COM15 1E 0 1 1 1 1 — 0F 1 1 1 1 0 COM16 1F 1 1 1 1 1 — 4. General output port set (specifies the general output port status) The general output port is an output for 4-bit static operation. It is used to control other I/O devices and turn on LED. (Static operation.) The fluorescent display tube cannot be driven by this output port, because when at the "High" level this output becomes the VDD voltage and when at the "Low" level it becomes the ground potential. [Command format] LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte P1 P2 P3 P4 * 0 0 1 : selects general output port and specifies the output status. P1-P4 : general output ports * : don't care [Set data and set state of general output port] Pn Display state of general output port 0 Sets P1-P4 to Low 1 Sets P1-P4 to High (The state when power is applied or when RESET is input) 25/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 5. Display duty set (writes display duty value to duty cycle register) Display duty adjusts contrast in 8 stages using 3-bit data. At the time power is turned on or the RESET signal is input, the duty cycle register value is "0". Always execute this instruction before turning the display on, then set a desired duty value. [Command format] LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte D0 D1 D2 * * 1 0 1 : selects display duty set mode and sets duty value. D0 (LSB) to D2 (MSB) : display duty data (3 bits: 8 stages) * : don't care [Relation between setup data and controlled COM duty] HEX D2 D1 D0 COM duty 0 0 0 0 8/16 (The state at the time power is turned on or RESET 1 0 0 1 9/16 signal is input) 2 0 1 0 10/16 3 0 1 1 11/16 4 1 0 0 12/16 5 1 0 1 13/16 6 1 1 0 14/16 7 1 1 1 15/16 26/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 6. Number of display digits set (writes the number of display digits to the display digit register) The number of display digits set can display 9 to 24 digits using 4-bit data. At the time power is turned on or a RESET signal is input, the display digit register value is "0". Always execute this instruction to change the number of digits before turning the dispaly on. [Command format] LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte K0 K1 K2 K3 * 0 1 1 : selects the number of display digits set mode and specifies the number of digits value. K0 (LSB) to K3 (MSB): number of display digits data (4 bits: 16 digits) [Relation between setup data and controlled COM] HEX K0 K1 K2 K3 Number of digits of COM HEX K0 K1 K2 K3 Number of digits of COM 0 0 0 0 0 COM1-24 8 0 0 0 1 COM1-16 1 1 0 0 0 COM1-9 9 1 0 0 1 COM1-17 2 0 1 0 0 COM1-10 A 0 1 0 1 COM1-18 3 1 1 0 0 COM1-11 B 1 1 0 1 COM1-19 4 0 0 1 0 COM1-12 C 0 0 1 1 COM1-20 5 1 0 1 0 COM1-13 D 1 0 1 1 COM1-21 6 0 1 1 0 COM1-14 E 0 1 1 1 COM1-22 7 1 1 1 0 COM1-15 F 1 1 1 1 COM1-23 The state at the time power is turned on or RESET signal is input 27/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 7. All display lights ON/OFF set (Turns all display lights ON or OFF) The all display lights ON mode is used primarily for display testing. The all display lights OFF mode is primarily used to prevent malfunction on power-up. [Command format] LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte L H * * * 1 1 1 : selects all display lights ON or OFF mode. [Set data and display state of SEG and AD] L H 0 0 All outputs maintain current states 1 0 Sets all outputs to Low 0 1 Sets all outputs to High 1 1 Sets all outputs to High Display state of SEG and AD (The state at the time power is applied or RESET is input) (All lights ON mode has priority.) 28/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 Initial Setting Flowchart Start Power is applied or RESET is input Apply VDD Apply VFL All display lights OFF Status of all outputs by RESET signal input Specify number of display digits Specify display duty Select a RAM to be used DCRAM CGRAM ADRAM Data write mode Data write mode Data write mode (with address set) (with address set) (with address set) Address is automatically incremented Address is automatically incremented DCRAM Character code NO DCRAM Is character code write ended? Address is automatically incremented ADRAM Character code CGRAM Character code NO YES CGRAM Is character code write ended? YES YES NO ADRAM Is character code write ended? YES Another RAM to be set? NO Specify general output port status Release all display lights OFF mode Normal operation status (display ON) End 29/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 APPLICATION CIRCUIT Heater transformer 5¥7-dot matrix fluorescent display tube ANODE (SEGMENT) ANODE GRID (SEGMENT) (DIGIT) VDD 4 R2 VDD C2 VDD C3 Microcontroller Output Port RESET VDD, AD1-4 VDISP1-2 C4 24 SEG1-35 COM1-24 R4 LED MSM9201-01 CS CP DA P1-2 GND VFL VDD 35 GND VFL1-2 R3 GND OSC0 OSC1 R1 4 NPN Tr GND C1 GND ZD Notes: 1. The VDD value depends on the power supply voltage of the microcontroller used. Adjust the values of the constants R1, R2, R4, C1, and C2 to the power supply voltage used. 2. The VFL value depends on the fluorescent display tube used. Adjust the values of the constants R3 and ZD to the power supply voltage used. 30/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 Reference data The figure below shows the relationship between the VFL voltage and the output current of each driver. Take care that the total power consumption to be used does not exceed the power dissipation. VFL Voltage vs. Output Current of Each Driver –30 Output Current (mA) –25 –20 COM1 to COM24 (Condition: VOH=VDISP–1.5 V) –15 –10 AD1 to AD4 (Condition: VOH=VDISP–1.5 V) –5 SEG1 to SEG35 (Condition: VOH=VDISP–1.5 V) 0 –10 –20 –30 –40 –50 –60 (V) VFL Voltage (VDD-n) 31/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 MSM9201-01 ROM CODE 00000000B (00H) to 00001111B (0FH) are the CGRAM addresses. MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LSB 0000 RAM0 0001 RAM1 0010 RAM2 0011 RAM3 0100 RAM4 0101 RAM5 0110 RAM6 0111 RAM7 1000 RAM8 1001 RAM9 1010 RAMA 1011 RAMB 1100 RAMC 1101 RAMD 1110 RAME 1111 RAMF 32/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1414-0.65-K . Mirror finish Oki Electric Industry Co., Ltd. Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5 mm) 0.85 TYP. 3/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 33/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Oki Electric Industry Co., Ltd. Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5 mm) 1.27 TYP. 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 34/35 PEDL9201-03 ¡ Semiconductor MSM9201-01 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 2000 Oki Electric Industry Co., Ltd. Printed in Japan 35/35