This version: Feb. 1999 Previous version: ------- Semiconductor MR53V3252J Preliminary 2,097,152-Word X 16-Bit or 4,194,304-Word X 8-Bit 8Word X 16-Bit or 16Word X 8-Bit/Page Mode MASK ROM DESCRIPTION The MR53V3252J is a 32Mbit Read-Only Memory whose configuration can be electrically switched between 2,097,152 word x 16bit and 4,194,304 word x 8bit. The MR53V3252J operates asynchronously, external clocks are not required, making this device easy-to-use. The MR53V3252J is suitable as large-capacity fixed memory for microcomputers and data terminals. It is manufactured using a CMOS silicon gate technology and is offered in 44-pin SOP or 44-pin TSOP packages. FEATURES · 2,097,152word x 16bit / 4,194,304 word x 8bit electrically switchable configuration · 8word x 16-Bit or 16word x 8-bit / Page read mode · Single +2.7V~3.6V power supply · Normal Access time 100ns (@Vcc=3.0V~3.6V) 120ns (@Vcc=2.7V~3.3V) · Page Access time 30ns (@Vcc=3.0V~3.6V) 40ns (@Vcc=2.7V~3.3V) · VCC power supply current 80mA (@Vcc=3.0V~3.6V) 70mA (@Vcc=2.7V~3.3V) · VCC standby current 10mA · Input / Output TTL compatible · Three-state output · Packages 44-pin plastic SOP (SOP44-P-600-1.27-K) MR53V3252J-XXMA 44-pin plastic TSOP (TSOPII44-P-400-0.80-K) MR53V3252J-XXTP 1/6 MR53V3252J Semiconductor PIN CONFIGURATION (TOP VIEW) NC 1 44 A20 A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 11 34 A16 CE 12 33 BYTE VSS 13 32 VSS OE 14 31 D15/A-1 D0 15 30 D7 D8 15 29 D14 D1 17 28 D6 D9 18 27 D13 D2 19 26 D5 D10 20 25 D12 D3 21 24 D4 D11 22 23 VCC 44-Pin SOP 44-Pin TSOPII PIN NAMES D15/A-1 A0~A20 D0~D14 CE OE BYTE VCC VSS NC FUNCTIONS Data output / Address input Address input Data output Chip enable Output enable Mode switch Power supply voltage GND Non connection 2/6 MR53V3252J Semiconductor BLOCK DIAGRAM A-1 BYTE X8/X16 SWITCH CE CE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 OE OE CONTROL Memory Cell Matrix 2,097,152 x 16 or 4,194,304 x 8 Row Decoder Address Buffer Multiplex Column Decoder Output Buffer D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 FUNCTION TABLE MODE STAND BY OUTPUT DISABLE READ(16-BIT) READ(8-BIT) CE H L L L L OE X H H L L BYTE X H L H L D0~D7 D8~D14 A-1/D15 Hi-Z DOUT DOUT Hi-Z L/H L/H 3/6 MR53V3252J Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Operating temperature under bias Storage temperature Input voltage Output voltage Power supply voltage Power dissipation per package Symbol TOPR TSTG VI VO VCC PD Condition - Value 0 ~ 70 -55 ~ 125 -0.5 ~ VCC+0.5 -0.5 ~ VCC+0.5 -0.5 ~ 5 1.0 Relative to VSS - RECOMMENDED OPERATING CONDITIONS FOR READ Parameter VCC power supply voltage Input “H“ level Input “L“ level Voltage is relative to VSS Symbol VCC VIH VIL Condition VCC=2.7V ~ 3.6V PIN Capacitance Parameter Input Output Symbol CIN COUT Condition VI=0V VO=0V Min. 2.7 2.2 -0.5 Typ. - Unit `C `C V V V W (Ta=0 ~ 70`C) Min. Unit 3.6 `C VCC+0.5 `C 0.8 V (Vcc=3.3V, Ta=25`C, f=1MHz) Min. Typ. Min. Unit 12 pF 15 pF 4/6 MR53V3252J Semiconductor ELECTRICAL CHARACTERISTICS DC Characteristics 1 Parameter Input leakage current Output leakage current VCC power supply current (Standby) VCC power supply current (Active) Input “H“ level Input “L“ level Output “H“ level Output “L“ level Voltage is relative to VSS Symbol CIN COUT ICCSC ICCST ICCA VIH VIL VOH VOL Condition VI=0V~VCC VO=0V~VCC CE= VCC CE= VIH CE= VIL, OE= VIH tc= 120ns IOH=-200 mA IOL=1mA DC Characteristics 2 Parameter Input leakage current Output leakage current VCC power supply current (Standby) VCC power supply current (Active) Input “H“ level Input “L“ level Output “H“ level Output “L“ level Voltage is relative to VSS Symbol CIN COUT ICCSC ICCST ICCA VIH VIL VOH VOL Condition VI=0V~VCC VO=0V~VCC CE= VCC CE= VIH CE= VIL, OE= VIH tc= 100ns IOH=-200 mA IOL=1mA (Vcc=2.7V~3.3V, Ta=0~70`C) Min. Typ. Min. Unit 10 mA 10 mA 10 mA 1 mA - - 70 mA 2.0 -0.5 VCC-0.4 - - VCC+0.5 0.8 0.4 V V V V (Vcc=3.0V~3.6V, Ta=0~70`C) Min. Typ. Min. Unit 10 mA 10 mA 10 mA 1 mA - - 80 mA 2.0 -0.5 VCC-0.4 - - VCC+0.5 0.8 0.4 V V V V 5/6 MR53V3252J Semiconductor AC Characteristics 1 Parameter Address access cycle time Address access time Page set up time Page access cycle time Page access time CE access time OE access time Output disable time Output hold time Symbol TC TACC TPSET TPC TPAC TCE TOE TCHZ TOHZ TOH Condition CE=OE= VIL NOTE.1 OE= VIL CE= VIL OE= VIL CE= VIL CE=OE= VIL AC Characteristics 2 Parameter Address access cycle time Address access time Page set up time Page access cycle time Page access time CE access time OE access time Output disable time Symbol Condition TC TACC CE=OE= VIL TPSET NOTE.1 TPC TPAC TCE OE= VIL TOE CE= VIL TCHZ OE= VIL TOHZ CE= VIL Output hold time TOH CE=OE= VIL NOTE.1 TPSET is defined as the end of either CE falling edge or term until the first page address transition. Measurement condition Input signal level Input timing reference level Output load Output timing reference level (Vcc=2.7V~3.3V, Ta=0~70`C) Min. Min. Unit 120 ns 120 ns 120 ns 40 ns 40 ns 120 ns 40 ns 0 35 ns 0 30 ns 0 ns (Vcc=3.0V~3.6V, Ta=0~70`C) Min. Min. Unit 100 ns 100 ns 100 ns 30 ns 30 ns 100 ns 30 ns 0 30 ns 0 25 ns 0 ns address transition in random access 0V/3V 0.8V/2.0V 100pF 0.8V/2.0V 1.7V 400W Output 100pF 6/6 MR53V3252J Semiconductor TIMING CHART NORMAL MODE READ CYCLE tC ADDRESS tOH tCE CE tCHZ tOE OE tACC DOUT tOHZ Valid Data Hi-Z Hi-Z PAGE MODE READ CYCLE tC A3-A20 tPSET tPSET A0~A2 (x16mode) A-1~A2 (x8mode) tPC tPC tCE tOH CE tCHZ tOE OE tACC DOUT tPA tPA tOHZ Hi-Z 7/6 Semiconductor NOTICE The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-todate. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 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