OKI MSC23Q43657D

This version: Mar. 6. 2000
Semiconductor
MSC23Q43657D-xxBS9/DS9
4,194,304-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSC23Q43657D-xxBS9/DS9 is a 4,194,304-word x 36-bit CMOS dynamic random access memory module
which is composed of eight 16Mb DRAMs (4Mx4) in SOJ packages and one 16Mb DRAM (4/CAS 4Mx4) in SOJ
package mounted with nine decoupling capacitors. This is a 72-pin single in-line memory module. This module
supports any application where high density and large capacity of storage memory are required.
FEATURES
• 4,194,304-word x 36-bit organization
• 72-pin Single In-Line Memory Module
MSC23Q43657D-xxBS9 : Gold tab
MSC23Q43657D-xxDS9 : Solder tab
• Single 5V power supply, ±10% tolerance
• Input
: TTL compatible
• Output : TTL compatible, 3-state
• Refresh : 2048cycles/32ms
• Fast page mode with EDO capability
• /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
• Multi-bit test mode capability
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation (Max.)
tRAC
tAA
tCAC
Cycle Time
(Min.)
MSC23Q43657D-60BS9/DS9
60ns
30ns
15ns
104ns
4455mW
MSC23Q43657D-70BS9/DS9
70ns
35ns
20ns
124ns
3960mW
Family
Operating
Standby
49.5mW
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MSC23Q43657D
MODULE OUTLINE
(Unit : mm)
MSC23Q43657D-xxBS9/DS9
5.28Max.
107.95±0.2*1
101.19Typ.
3.38Typ.
2.03Typ.
1
72
1.27±0.1
R1.57
6.35Typ.
6.35
95.25
1.04Typ.
3.17Min.
6.35Typ.
25.4±0.2
10.16Typ.
φ3.18
+0.1
1.27
−0.08
Note:
1. Tolerance over 12.5mm from board edge is ±0.5.
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Semiconductor
MSC23Q43657D
PIN CONFIGURATION
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
VSS
19
A10
37
DQ17
55
DQ12
2
DQ0
20
DQ4
38
DQ35
56
DQ30
3
DQ18
21
DQ22
39
VSS
57
DQ13
4
DQ1
22
DQ5
40
/CAS0
58
DQ31
5
DQ19
23
DQ23
41
/CAS2
59
VCC
6
DQ2
24
DQ6
42
/CAS3
60
DQ32
7
DQ20
25
DQ24
43
/CAS1
61
DQ14
8
DQ3
26
DQ7
44
/RAS0
62
DQ33
9
DQ21
27
DQ25
45
NC
63
DQ15
10
VCC
28
A7
46
NC
64
DQ34
11
NC
29
NC
47
/WE
65
DQ16
12
A0
30
VCC
48
NC
66
NC
13
A1
31
A8
49
DQ9
67
PD1
14
A2
32
A9
50
DQ27
68
PD2
15
A3
33
NC
51
DQ10
69
PD3
16
A4
34
/RAS2
52
DQ28
70
PD4
17
A5
35
DQ26
53
DQ11
71
NC
18
A6
36
DQ8
54
DQ29
72
VSS
Presence Detect Pins
Pin No.
Pin Name
-60
-70
67
PD1
VSS
VSS
68
PD2
NC
NC
69
PD3
NC
VSS
70
PD4
NC
NC
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Semiconductor
MSC23Q43657D
BLOCK DIAGRAM
/RAS0
/CAS0
/RAS
/CAS
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ
DQ
DQ
DQ
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ9
DQ10
DQ11
DQ12
DQ
DQ
DQ
DQ
DQ13
DQ14
DQ15
DQ16
/RAS
/CAS0
DQ0
/CAS1
DQ1
D8
/CAS2
DQ2
/CAS3
DQ3
DQ8
DQ17
DQ26
DQ35
D0
/RAS
/CAS
D1
/CAS1
/RAS
/CAS
D2
/RAS
/CAS
D3
/RAS
/CAS
D4
/CAS2
/RAS
/CAS
D5
/RAS
/CAS
D6
/CAS3
/RAS
/CAS
D7
DQ
DQ
DQ
DQ
DQ18
DQ19
DQ20
DQ21
DQ
DQ
DQ
DQ
DQ22
DQ23
DQ24
DQ25
DQ
DQ
DQ
DQ
DQ27
DQ28
DQ29
DQ30
DQ
DQ
DQ
DQ
DQ31
DQ32
DQ33
DQ34
/RAS2
A0-A10
/WE
A0-A10 : D0-D8
/WE : D0-D8
VCC
VSS
VCC : D0-D8
C0-C8
VSS & /OE : D0-D8
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MSC23Q43657D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VIN, VOUT
−0.5 to VCC + 0.5
V
Voltage on VCC Any Pin Relative to VSS
VCC
−0.5 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD *
9
W
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature
TSTG
−40 to 125
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4

VCC + 0.3
V
Input Low Voltage
VIL
−0.3

0.8
V
Power Supply Voltage
Capacitance
(VCC = 5V ±10%, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A10)
CIN1

65
pF
Input Capacitance (/WE)
CIN2

73
pF
Input Capacitance (/RAS0, /RAS2)
CIN3

43
pF
Input Capacitance (/CAS0 - /CAS3)
CIN4

28
pF
I/O Capacitance (DQ0 - DQ35)
CI/O

16
pF
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Semiconductor
MSC23Q43657D
DC Characteristics
(VCC = 5V ±10%, Ta = 0°C to 70°C)
Parameter
Symbol
Condition
-60
-70
Unit
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
V
Note
Output High Voltage
VOH
IOH = −5.0mA
Output Low Voltage
VOL
IOL = 4.2mA
Input Leakage Current
ILI
0V ≤ VIN ≤ 6.5V;
All other pins not
under test = 0V
−90
90
−90
90
µA
Output Leakage Current
ILO
DQ disable
0V ≤ VOUT ≤ VCC
−10
10
−10
10
µA
Average Power
Supply Current
(Operating)
ICC1
/RAS, /CAS cycling,
tRC = Min.

810

720
mA
1, 2
/RAS, /CAS = VIH

18

18
/RAS, /CAS
≥ VCC − 0.2V

9

9
mA
1
Power supply current
(Standby)
ICC2
Average Power
Supply Current
(/RAS only refresh)
ICC3
/RAS cycling,
/CAS = VIH,
tRC = Min.

810

720
mA
1, 2
Average Power
Supply Current
(/CAS before /RAS refresh)
ICC6
/RAS cycling,
/CAS before /RAS

810

720
mA
1, 2
Average Power
Supply Current
(Fast Page Mode)
ICC7
/RAS = VIL,
/CAS cycling,
tHPC = Min.

810

720
mA
1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while /RAS = VIL.
3. The address can be changed once or less while /CAS = VIH.
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MSC23Q43657D
AC Characteristics (1/2)
(VCC = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 10, 11
Parameter
Symbol
-60
-70
Min.
Max.
Min.
Max.
Unit
Note
Random Read or Write Cycle Time
tRC
104

124

ns
Fast Page Mode Cycle Time
tHPC
25

30

ns
Access Time from /RAS
tRAC

60

70
ns
4, 5, 6
Access Time from /CAS
tCAC

15

20
ns
4, 5
Access Time from Column Address
tAA

30

35
ns
4, 6
Access Time from /CAS Precharge
tCPA

35

40
ns
4
Output Low Impedance Time from /CAS
tCLZ
0

0

ns
4
Data Output Hold After /CAS Low
tDOH
5

5

ns
/CAS to Data Output Buffer Turn-off Delay Time
tCEZ
0
15
0
20
ns
7, 8
/RAS to Data Output Buffer Turn-off Delay Time
tREZ
0
15
0
20
ns
7, 8
/WE to Data Output Buffer Turn-off Delay Time
tWEZ
0
15
0
20
ns
7
Transition Time
tT
1
50
1
50
ns
3
Refresh Period
tREF

32

32
ms
/RAS Precharge Time
tRP
40

50

ns
/RAS Pulse Width
tRAS
60
10K
70
10K
ns
/RAS Pulse Width (Fast Page Mode)
tRASP
60
100K
70
100K
ns
/RAS Hold Time
tRSH
10

13

ns
/CAS Precharge Time (Fast Page Mode)
tCP
10

10

ns
/CAS Pulse Width
tCAS
10
10K
13
10K
ns
/CAS Hold Time
tCSH
40

45

ns
/CAS to /RAS Precharge Time
tCRP
5

5

ns
/RAS Hold Time from /CAS Precharge
tRHCP
35

40

ns
/RAS to /CAS Delay Time
tRCD
14
45
14
50
ns
5
/RAS to Column Address Delay Time
tRAD
12
30
12
35
ns
6
Row Address Set-up Time
tASR
0

0

ns
Row Address Hold Time
tRAH
10

13

ns
Column Address Set-up Time
tASC
0

0

ns
Column Address Hold Time
tCAH
10

13

ns
Column Address to /RAS Lead Time
tRAL
30

35

ns
Read Command Set-up Time
tRCS
0

0

ns
Read Command Hold Time
tRCH
0

0

ns
9
Read Command Hold Time referenced to /RAS
tRRH
0

0

ns
9
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Semiconductor
MSC23Q43657D
AC Characteristics (2/2)
(VCC = 5V ±10%, Ta = 0°C to 70°C) Note: 1, 2, 3, 10, 11
Parameter
Symbol
-60
-70
Min.
Max.
Min.
Max.
Unit
Write Command Set-up Time
tWCS
0

0

ns
Write Command Hold Time
tWCH
10

13

ns
Write Command Pulse Width
tWP
10

10

ns
/WE Pulse Width (DQ Disable)
tWPE
10

10

ns
Write Command to /RAS Lead Time
tRWL
10

13

ns
Write Command to /CAS Lead Time
tCWL
10

13

ns
Data-in Set-up Time
tDS
0

0

ns
Data-in Hold Time
tDH
10

13

ns
/CAS Active Delay Time from /RAS Precharge
tRPC
5

5

ns
/RAS to /CAS Set-up Time (/CAS before /RAS)
tCSR
5

5

ns
/RAS to /CAS Hold Time (/CAS before /RAS)
tCHR
10

10

ns
/WE to /RAS Precharge Time (/CAS before /RAS)
tWRP
10

10

ns
/WE Hold Time from /RAS (/CAS before /RAS)
tWRH
10

10

ns
/RAS to /WE Set-up Time (Test Mode)
tWTS
10

10

ns
/RAS to /WE Hold Time (Test Mode)
tWTH
10

10

ns
Note
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MSC23Q43657D
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.
2. The AC characteristics assumes tT = 2ns.
3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are
measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100pF.
5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.
tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then
the access time is controlled by tCAC.
6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the access time is controlled by tAA.
7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by a /RAS only
refresh or /CAS before /RAS refresh cycle.
11. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
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