SCLS566A − JANUARY 2004 − REVISED MAY 2004
D Controlled Baseline
D
D
D
D
D
D
D
D Typical VOHV (Output VOH Undershoot)
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−40°C to 105°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
2-V to 5.5-V VCC Operation
Max tpd of 14.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D
D
D
D
>2.3 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down-Mode
Operation
Dual 4-Bit Binary Counters With Individual
Clocks
Direct Clear for Each 4-Bit Counter
Can Significantly Improve System
Densities by Reducing Counter Package
Count by 50 Percent
PW PACKAGE
(TOP VIEW)
1CLK
1CLR
1QA
1QB
1QC
1QD
GND
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2CLK
2CLR
2QA
2QB
2QC
2QD
description/ordering information
The SN74LV393A contains eight flip-flops and additional gating to implement two individual 4-bit counters in
a single package. This device is designed for 2-V to 5.5-V VCC operation.
This device comprises two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)
input. The device changes state on the negative-going transition of the CLK pulse. N-bit binary counters can
be implemented with each package, providing the capability of divide by 256. The SN74LV393A has parallel
outputs from each counter stage so that any submultiple of the input count frequency is available for system
timing signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
ORDERABLE
PART NUMBER
PACKAGE‡
TOP-SIDE
MARKING
−40°C to 105°C
TSSOP − PW
Tape and reel
SN74LV393ATPWREP LV393EP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
FUNCTION
CLK
CLR
↑
L
No change
↓
L
Advance to next stage
X
H
All outputs L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS566A − JANUARY 2004 − REVISED MAY 2004
logic diagram, each counter (positive logic)
R
CLR
CLK
Q
QA
Q
QB
Q
QC
Q
QD
T
R
T
R
T
R
T
timing diagram
CLK
CLR
QA
QB
Outputs
QC
QD
Count Up
Clear
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS566A − JANUARY 2004 − REVISED MAY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
IOH
IOL
∆t/∆v
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
2
5.5
0.5
VCC × 0.3
VCC × 0.3
0
0
High-level output current
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
Input transition rise or fall rate
V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
VCC = 2.3 V to 2.7 V
V
1.5
VCC × 0.7
VCC × 0.7
VCC = 2 V
VCC = 2.3 V to 2.7 V
Output voltage
UNIT
V
VCC × 0.3
5.5
V
VCC
−50
µA
V
−2
−6
mA
−12
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
µA
2
mA
12
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
200
VCC = 4.5 V to 5.5 V
20
100
ns/V
TA
Operating free-air temperature
−40
105
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCLS566A − JANUARY 2004 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
2 V to 5.5 V
2.3 V
IOH = −6 mA
IOH = −12 mA
IOL = 50 µA
IOL = 2 mA
VI = 5.5 V or GND
VI = VCC or GND,
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
TYP
IO = 0
MAX
UNIT
VCC−0.1
2
3V
2.48
4.5 V
3.8
V
2 V to 5.5 V
IOL = 6 mA
IOL = 12 mA
II
ICC
MIN
VCC
0.1
2.3 V
0.4
3V
0.44
4.5 V
0.55
V
0 to 5.5 V
±1
µA
5.5 V
20
µA
0
5
µA
3.3 V
1.8
pF
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
MIN
CLK high or low
5
5
CLR high
5
5
CLR inactive before CLK↓
6
6
MAX
UNIT
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
MIN
CLK high or low
5
5
CLR high
5
5
CLR inactive before CLK↓
5
5
MAX
UNIT
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
4
tw
Pulse duration
tsu
Setup time
POST OFFICE BOX 655303
MIN
CLK high or low
5
5
CLR high
5
5
CLR inactive before CLK↓
4
4
• DALLAS, TEXAS 75265
MAX
UNIT
ns
ns
SCLS566A − JANUARY 2004 − REVISED MAY 2004
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
CL = 50 pF
MIN
30
QA
tpd
CLK
QB
QC
CL = 50 pF
QD
tPHL
CLR
Qn
CL = 50 pF
TA = 25°C
TYP
MAX
70
MIN
MAX
25
UNIT
MHz
9.3
21.3
1
24.5
10.9
23.9
1
27.5
12.3
26.1
1
30
13.4
27.8
1
32
9.1
17.4
1
20
ns
ns
switching characteristics over recommended operation free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
CL = 50 pF
MIN
45
QA
tpd
CLK
QB
QC
CL = 50 pF
QD
tPHL
CLR
Qn
CL = 50 pF
TA = 25°C
TYP
MAX
105
MIN
MAX
35
UNIT
MHz
6.7
16.7
1
19
7.8
19.3
1
22
8.7
21.5
1
24.5
9.5
23.2
1
26.5
6.8
15.8
1
18
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
CL = 50 pF
QA
tpd
CLK
tPHL
CLR
QB
QC
CL = 50 pF
QD
Qn
POST OFFICE BOX 655303
CL = 50 pF
• DALLAS, TEXAS 75265
MIN
85
TA = 25°C
TYP
MAX
150
MIN
MAX
75
UNIT
MHz
4.9
10.5
1
12
5.6
11.8
1
13.5
6.2
13.2
1
15
6.6
14.5
1
16.5
5.2
10.1
1
11.5
ns
ns
5
SCLS566A − JANUARY 2004 − REVISED MAY 2004
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.3
0.8
V
Quiet output, minimum dynamic VOL
−0.2
−0.8
V
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
2.8
High-level dynamic input voltage
V
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.
0.99
V
VCC
3.3 V
TYP
UNIT
5V
17.3
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 10 MHz
15.2
pF
SCLS566A − JANUARY 2004 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV393ATPWREP
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04695-01XE
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV393A-EP :
SN74LV393A
• Catalog:
• Automotive: SN74LV393A-Q1
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LV393ATPWREP
Package Package Pins
Type Drawing
TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV393ATPWREP
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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