SCAS182 − APRIL 1989 − REVISED APRIL 1993 • • • • • • DW OR NT PACKAGE (TOP VIEW) Specifically Designed for Data Synchronization Applications 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS ) 1-µm Process Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OE 1D 2D 3D 4D VCC VCC 5D 6D 7D 8D CLK description The 74AC11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization applications in which the normal setup and hold time specifications are frequently violated. Synchronization of two digital signals operating at different frequencies is a common system problem. This problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution, however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output hangs up in the region between VIL and VIH. The metastable condition lasts until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum propagation delay. The problem of metastability is typically solved by adding an additional layer of synchronization. This dual-rank approach is employed in the 74AC11478. The probability of the second stage entering the metastable state is exponentially reduced by this dual-rank architecture. The 74AC11478 provides a one-chip solution for system designers in asynchronous applications. The 74AC11478 is characterized for operation from − 40°C to 85°C. FUNCTION TABLE OE INPUTS CLK† D Q H L L L X ↑ ↑ L X L H X Z L H Q0 OUTPUT † Data presented at the D inputs requires two clock cycles to appear at the Q outputs. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 SCAS182 − APRIL 1989 − REVISED APRIL 1993 logic symbol† OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 24 13 23 22 logic diagram (positive logic) EN OE 24 C1 1D 1D 1 2 21 3 20 4 17 9 16 10 15 11 14 12 CLK 1Q 2Q 1D 3Q 13 23 C1 1D 4Q C1 1D 1 1Q 5Q 6Q To 7 Other Channels 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS182 − APRIL 1989 − REVISED APRIL 1993 recommended operating conditions (see Note 2) VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VI VO ∆t/∆v 3 5 5.5 0.9 1.35 VCC VCC 0 VCC = 3 V VCC = 4.5 V Low-level output current V 1.65 0 High-level output current V V VCC = 4.5 V VCC = 5.5 V Low-level input voltage UNIT 3.85 Output voltage IOL MAX 3.15 Input voltage IOH NOM 2.1 VCC = 5.5 V VCC = 3 V VIL MIN V V −4 −24 VCC = 5.5 V VCC = 3 V −24 VCC = 4.5 V VCC = 5.5 V 24 mA 12 mA 24 Input transition rise or fall rate TA Operating free-air temperature NOTE 2: Unused or floating inputs must be held high or low. 0 10 ns/V −40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C PARAMETER TEST CONDITIONS IOH = − 50 µA VOH IOH = − 4 mA ICC Ci Co TYP MAX MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 3.94 3.8 IOL = − 24 mA 5.5 V 4.94 4.8 IOH = − 75 mA† 5.5 V IOL = 12 mA IOL = 24 mA II IOZ MIN 4.5 V IOL = 50 µA VOL VCC MAX UNIT V 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V IOL = 75 mA† VI = VCC or GND 5.5 V 5.5 V ± 0.1 ±1 µA VO = VCC or GND VI = VCC or GND, 5.5 V ± 0.5 ±5 µA 5.5 V 8 80 µA IO = 0 VI = VCC or GND VO = VCC or GND 1.65 5V 4.5 pF 5V 10 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SCAS182 − APRIL 1989 − REVISED APRIL 1993 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock tsu Clock frequency th tw Hold time, data after CLK↑ MIN MAX UNIT 55 MHz 55 Setup time, data before CLK↑ Pulse duration, CLK high or low 3 3 ns 1.5 1.5 ns 9 9 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX MIN MAX UNIT 83 MHz fclock tsu Clock frequency Setup time, data before CLK↑ 2.5 83 2.5 ns th tw Hold time, data after CLK↑ 1.5 1.5 ns 6 6 ns Pulse duration, CLK high or low switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 55 CLK Q OE Q OE Q MIN MAX 55 UNIT MHz 3.8 10.5 13.3 3.8 15 5.5 13.2 16.8 5.5 18.4 3.7 10.8 13.9 3.7 16 5.4 14.7 19.2 5.4 22.5 3.9 7.1 9.3 3.9 10.1 4 6.9 8.9 4 9.6 ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 83 CLK Q OE Q OE Q MIN MAX 83 UNIT MHz 2.9 6.1 8.9 2.9 10 4.3 7.9 11.2 4.3 12.3 2.9 6.4 9.6 2.9 10.8 4.1 8.1 12.3 4.1 14.0 3.2 5.7 8 3.2 8.6 3.5 5.4 7.4 3.5 8 ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance per flip-flop TEST CONDITIONS Outputs enabled Outputs disabled • CL = 50 pF, POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • f = 1 MHz TYP 46 33 UNIT pF SCAS182 − APRIL 1989 − REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) S1 Open 2 × VCC GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 500 Ω tw LOAD CIRCUIT FOR OUTPUTS VCC Input 50% 50% 0V VCC Timing Input 50% VOLTAGE WAVEFORMS PULSE DURATION 0V tsu th VCC Data Input 50% 50% VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input (see Note B) 0V Output (see Note D) tPHL Output Waveform 2 S1 at GND (see Note C) VOH 50% VCC VOL 50% VCC 50% 0V tPLZ ≈ VCC Output Waveform 1 S1 at 2 × VCC (see Note C) 50% tPLH 50% tPZL VCC 50% VCC Output Control (low-level enabling) 0V 50% VCC tPZH 20% VCC VOL tPHZ VOH 50% VCC 80% VCC 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74AC11478DW OBSOLETE SOIC DW 24 TBD Call TI Call TI 74AC11478NT OBSOLETE PDIP NT 24 TBD Call TI Call TI 74AC11478NT OBSOLETE PDIP NT 24 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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