SCLS197B − FEBRUARY 1993 − REVISED APRIL 1996
D EPIC (Enhanced-Performance Implanted
D
D
D
D
CMOS) 2-µ Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54LV374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
VCC
8Q
D
SN54LV374 . . . J OR W PACKAGE
SN74LV374 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
description
2D
2Q
3Q
3D
4D
These octal edge-triggered D-type flip-flops are
designed for 2.7-V to 5.5-V VCC operation.
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
The ’LV374 feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. These devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
4
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either as normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN74LV374 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV374 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV374 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$% !%&% %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/,
("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++
)&(&#$$(,
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1
SCLS197B − FEBRUARY 1993 − REVISED APRIL 1996
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
OE
CLK
1
11
logic diagram (positive logic)
OE
EN
C1
CLK
1
11
C1
1D
2D
3D
4D
5D
6D
7D
8D
3
1D
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
1D
1Q
3
1D
2
1Q
2Q
3Q
4Q
5Q
To Seven Other Channels
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DB, DW, J, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 70 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
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•
SCLS197B − FEBRUARY 1993 − REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV374
VCC
Supply voltage
MIN
MAX
MIN
MAX
2.7
5.5
2.7
5.5
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOL
Low-level output current
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
∆t / ∆v
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
SN74LV374
2
2
3.15
3.15
0.8
0.8
1.65
0
0
V
V
1.65
VCC
VCC
UNIT
VCC
VCC
−8
−8
−16
−16
8
8
16
16
V
V
V
mA
mA
0
100
0
100
ns / V
−55
125
−40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
VCC†
TEST CONDITIONS
IOH = − 100 µA
IOH = − 8 mA
MIN to MAX
IOH = − 16 mA
IOL = 100 µA
4.5 V
3V
SN54LV374
MIN
TYP
II
VI = VCC or GND
IOZ
VO = VCC or GND
ICC
VI = VCC or GND,
nICC
One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
Co
VO = VCC or GND
MIN
VCC −0.2
2.4
VCC −0.2
2.4
3.6
3.6
MIN to MAX
IOL = 8 mA
IOL = 16 mA
SN54LV374
MAX
TYP
MAX
V
0.2
0.2
3V
0.4
0.4
4.5 V
0.55
0.55
3.6 V
±1
±1
5.5 V
±1
±1
3.6 V
±5
±5
5.5 V
±5
±5
3.6 V
20
20
5.5 V
20
20
3 V to 3.6 V
500
500
IO = 0
UNIT
3.3 V
2.5
2.5
5V
3
3
3.3 V
7
7
5V
8
8
V
µA
A
µA
A
µA
A
µA
pF
pF
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
%'(#&% !%!$(% )("! % $ '(#&1$ (
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)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
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•
3
SCLS197B − FEBRUARY 1993 − REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV374
VCC = 5 V
± 0.5 V
MIN
MAX
45
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
40
VCC = 2.7 V
MIN
MAX
0
35
UNIT
fclock
tw
Clock frequency
0
Pulse duration, CLK high or low
9
10
13
ns
tsu
Setup time before CLK↑
7
10
11
ns
th
Hold time, data after CLK↑
3
2
2
ns
High or low
MHz
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV374
VCC = 5 V
± 0.5 V
MIN
MAX
45
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
40
VCC = 2.7 V
MIN
MAX
0
35
UNIT
fclock
tw
Clock frequency
0
Pulse duration, CLK high or low
9
10
13
ns
tsu
Setup time before CLK↑
7
10
11
ns
th
Hold time, data after CLK↑
3
2
2
ns
High or low
MHz
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1))
SN54LV374
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V ± 0.5 V
MIN
TYP
MAX
fmax
45
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
80
40
70
VCC = 2.7 V
MIN
MAX
35
UNIT
MHz
tpd
CLK
Q
11
19
15
24
29
ns
ten
OE
Q
10
20
13
24
28
ns
Q
8
21
12
24
29
ns
tdis
OE
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74LV374
FROM
(INPUT)
TO
(OUTPUT)
tpd
CLK
Q
11
19
15
24
29
ns
ten
OE
Q
10
20
13
24
28
ns
tdis
OE
Q
8
21
12
24
29
ns
PARAMETER
VCC = 5 V ± 0.5 V
MIN
TYP
MAX
fmax
45
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
80
40
%'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
4
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•
70
VCC = 2.7 V
MIN
MAX
35
UNIT
MHz
SCLS197B − FEBRUARY 1993 − REVISED APRIL 1996
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCC
Outputs enabled
Power dissipation capacitance per flip-flop
Outputs enabled
CL = 50 pF,
Outputs disabled
•
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•
UNIT
52
3.3 V
Outputs disabled
Cpd
TYP
f = 10 MHz
34
60
5V
pF
35
5
SCLS197B − FEBRUARY 1993 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
S1
1 kΩ
From Output
Under Test
Vz
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
1 kΩ
WAVEFORM
CONDITION
Vm
Vi
Vz
LOAD CIRCUIT
VCC = 4.5 V
to 5.5 V
0.5 × VCC
VCC
2 × VCC
VCC = 2.7 V
to 3.6 V
1.5 V
2.7 V
6V
Vi
Vm
Timing Input
0V
tw
tsu
Vi
Input
Vm
th
Vi
Vm
Vm
Data Input
Vm
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Vi
Vm
Input
0V
Vm
Vm
VOL
Output
tPLH
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
Vm
0V
tPLZ
Output
Waveform 1
S1 at Vz
(see Note B)
VOH
Output
Vm
Vm
tPZL
tPHL
tPLH
Vi
Output
Control
Vm
Vm
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Vm
tPZH
0.5 × Vz
VOL + 0.3 V
VOL
tPHZ
Vm
VOH − 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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•
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
SN74LV374DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74LV374DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LV374DWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LV374PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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